; -------------------------------------------------------------------------------- ; @Title: IMX7 On-Chip Peripherals ; @Props: Released ; @Author: TER, JRK, WMA, KST, PAK ; @Changelog: 2015-11-16 TER ; 2016-06-03 JRK ; 2017-03-30 KST ; 2020-05-26 PAK ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: imx7d_rm_rev_b.pdf (Rev. B, 2015-10) ; IMX7DualCEC.pdf (Rev. 2, 2016-06) ; IMX7DualRM.pdf (Rev. 0, 2016-05) ; IMX7SoloCEC.pdf (Rev. 2, 2016-06) ; IMX7SoloRM.pdf (Rev. 0, 2016-05) ; IMX7DRM_Rev1.pdf (Rev. 1, 2018-01) ; @Core: Cortex-A7MPCore, Cortex-M4F ; @Chip: IMX7SOLO-CM4, IMX7SOLO-CA7, IMX7DUAL-CM4, IMX7DUAL-CA7 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perimx7.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems: ; Module Register Description ; -------------------------------------------------------------------------------- ; NIC-301 Whole module Lack of base address and registers' descriptions ; DDRC_MP PCFGR_0 DDRC_RDWR_ORDERED_0 parameter missing ; DDRC_MP Whole module DDRC_INCL_ARB parameter missing ; DDRC_MP Whole module DDRC_PORT_n parameter missing ; DDRC_MP PCFGR_0 DDRC_A_RDWR_ORDERED_0 parameter missing ; DDRC_MP Whole module DDRC_A_AXI_n parameter missing ; DDRC_MP Whole module DDRC_PORT_CHm_0 parameter missing ; DDRC_MP PCFGQOS0_0 DDRC_A_USE2RAQ_0 parameter missing ; USBNC PHY_STATUS USBC_n_USBMODE[1:0] bits are missing ; CSI CSICR1 CCIR_MODE bit missing sif ((CORENAME()=="CORTEXA7")||(CORENAME()=="CORTEXA7MPCORE")) tree "Core Registers (Cortex-A7MPCore)" AUTOINDENT.PUSH AUTOINDENT.OFF ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- width 10. tree "ID Registers" group.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..." endif rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..." rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" textline " " bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4" rgroup.long c15:0x400++0x0 line.long 0x0 "MIDR2,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x700++0x0 line.long 0x0 "MIDR3,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." endif rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..." endif rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..." bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." textline " " bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented" textline " " bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" textline " " bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented" textline " " bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented" textline " " bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented" bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented" textline " " bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented" bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented" textline " " bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented" bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented" bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" textline " " bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" textline " " bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" endif tree.end width 12. tree "System Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" textline " " bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled" bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified" bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented" bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented" textline " " bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled" bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced" bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced" bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes" textline " " bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes" bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes" bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes" textline " " bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes" bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled" bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced" textline " " bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited" bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed" bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed" textline " " bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced" bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced" bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes" textline " " bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled" bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes" bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes" textline " " bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited" bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes" bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes" bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes" bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches" textline " " bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes" textline " " bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x140F++0x00 line.long 0x0 "ACTLR2,Auxiliary Control Register 2" bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled" bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled" textline " " else hgroup.long c15:0x140F++0x00 hide.long 0x0 "ACTLR2,Auxiliary Control Register 2" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" endif group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled" bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes" textline " " bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" textline " " bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" endif group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address" textline " " rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" else hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x1609))&0x3)==0x3) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes" bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" textline " " bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x2) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" textline " " bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x1) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" textline " " bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x0) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " endif group.long c15:0x410F++0x00 line.long 0x00 "FILASTARTR,Peripheral port start address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region" bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid" group.long c15:0x420F++0x00 line.long 0x00 "FILAENDR,Peripheral port end address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") hgroup.long c15:0x1609++0x00 hide.long 0x00 "SCUCTLR,SCU Control Register" hgroup.long c15:0x410F++0x00 hide.long 0x00 "FILASTARTR,Peripheral port start address register" hgroup.long c15:0x420F++0x00 hide.long 0x00 "FILAENDR,Peripheral port end address register" endif tree.end width 12. tree "Memory Management Unit" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " endif if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes" bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High" bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes" textline " " bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1" bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7" endif textline " " group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." endif endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" else hgroup.long c15:0x0015++0x00 hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif endif group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA" hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable" bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred" textline " " bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved" textline " " bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable" bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" textline " " bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate" bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection" bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..." textline " " bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " endif if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x003A++0x00 hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x013A++0x00 hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" endif else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" textline " " bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " endif if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif textline " " if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier" hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hyp Software Thread ID Register" tree.end width 15. tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x0 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hyp Configuration Register" bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system" bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted" bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override" bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override" textline " " bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hyp Debug Control Register" bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid" textline " " bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid" textline " " bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register" bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped" textline " " bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hyp System Trap Register" bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled" bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped" textline " " bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped" bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped" bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped" textline " " bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped" bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped" bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped" textline " " bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped" bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped" bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped" textline " " bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped" bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped" bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped" textline " " bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hyp Translation Table Base Register" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hyp Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved" bitfld.long 0x00 4. " S ,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" endif group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hyp Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..." textline " " bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hyp IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits" textline " " hgroup.long c15:0x407++0x00 hide.long 0x00 "NOP,No Operation Register" in wgroup.long c15:0x17++0x00 line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x617++0x00 line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x57++0x00 line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x157++0x00 line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x457++0x00 line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x657++0x00 line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x757++0x00 line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x167++0x00 line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x267++0x00 line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write" wgroup.long c15:0x1a7++0x00 line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x2a7++0x00 line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x4a7++0x00 line.long 0x00 "CP15DSB,Data Synchronization Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x5a7++0x00 line.long 0x00 "CP15DMB,Data Memory Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x1b7++0x00 line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x1e7++0x00 line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x2e7++0x00 line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,Invalidate instruction TLB" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,Invalidate data TLB" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,Invalidate unified TLB" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" else hgroup.long c15:0x403A++0x00 hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x413A++0x00 hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" endif group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hyp Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address" tree.end width 12. tree "Cache Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..." bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..." endif group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c15:0x10EF++0x00 line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved" else hgroup.long c15:0x10EF++0x00 hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" endif tree "Level 1 memory system" width 10. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" wgroup.long c15:0x004F++0x00 line.long 0x00 "RAMINDEX,RAM Index Register" hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier" bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" textline " " group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High" bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High" bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High" textline " " bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High" bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High" hexmask.long 0x00 0.--26. 1. " TA ,Tag Address" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long 0x00 6.--30. 1. " SI ,Set index" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--15. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--16. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--17. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--18. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--19. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--20. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" else hgroup.long c15:0x314F++0x0 hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" endif if (((d.l(c15:0x324F))&0x100)==0x100) wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" else wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" endif endif tree.end tree "Level 2 memory system" width 11. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" textline " " bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid" textline " " bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle" textline " " bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191." rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes" bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes" bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced" bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced" bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled" bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes" bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes" bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes" textline " " bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes" bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled" bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes" textline " " bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes" bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes" textline " " bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled" bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes" group.long c15:0x130F++0x00 line.long 0x00 "L2PFR,L2 Prefetch Control Register" bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes" bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled" bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes" textline " " bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines" textline " " group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" hgroup.quad c15:0x110F0++0x01 hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes" rgroup.long c15:0x1609++0x00 line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register" bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1" bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location" textline " " bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA" bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid" endif tree.end tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" textline " " bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" textline " " bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes" bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes" bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes" bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes" textline " " bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed" bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled" tree.end width 12. tree "System Timer Register" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline " " bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline "" group.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" textline "" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" textline "" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" tree.end width 11. width 15. tree "Debug Registers" rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" textline " " hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") wgroup.long c14:6.++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" endif group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled" group.long c14:9.++0x0 line.long 0x00 "DBGECR,Debug Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group.long c14:32.++0x0 line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Debug Instruction Transfer Register" rgroup.long c14:33.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif endif wgroup.long c14:35.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" textline " " bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request" bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled" bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running" textline " " elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" endif rgroup.long c14:40.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..." rgroup.long c14:41.++0x0 line.long 0x00 "DBGCIDSR,DBGCIDSR" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register" bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure" bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated" hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,DBGVIDSR" endif width 15. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register" bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High" bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High" bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High" bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register" bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High" bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High" bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c14:959.++0x0 line.long 0x00 "DBGITISR,Debug Integration Input Status Register" bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High" bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High" bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " rgroup.long c14:959.++0x0 line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register" bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High" bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) rgroup.quad c14:128.++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address" bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.quad c14:256.++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" else rgroup.long c14:128.++0x0 line.long 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address" bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.long c14:256.++0x0 line.long 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" endif group.long c14:195.++0x00 line.long 0x00 "DBGOSDLR,OS Double Lock Register" bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked" else hgroup.quad c14:128.++0x1 hide.quad 0x0 "DBGDRAR,Debug ROM Address Register" hgroup.quad c14:256.++0x1 hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hgroup.long c14:195.++0x00 hide.long 0x00 "DBGOSDLR,OS Double Lock Register" endif wgroup.long c14:192.++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:193.++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..." group.long c14:196.++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High" bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset" bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High" bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High" bitfld.long 0x00 4. " HALTED ,Halted" "Low,High" textline " " bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High" bitfld.long 0x00 2. " RS ,Reset Status" "Low,High" bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High" textline " " bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High" tree "Processor ID registers" rgroup.long c14:(832.+0.)++0x00 line.long 0x00 "PIDR0,Processor ID register 0" rgroup.long c14:(832.+1.)++0x00 line.long 0x00 "PIDR1,Processor ID register 1" rgroup.long c14:(832.+2.)++0x00 line.long 0x00 "PIDR2,Processor ID register 2" rgroup.long c14:(832.+3.)++0x00 line.long 0x00 "PIDR3,Processor ID register 3" rgroup.long c14:(832.+4.)++0x00 line.long 0x00 "PIDR4,Processor ID register 4" rgroup.long c14:(832.+5.)++0x00 line.long 0x00 "PIDR5,Processor ID register 5" rgroup.long c14:(832.+6.)++0x00 line.long 0x00 "PIDR6,Processor ID register 6" rgroup.long c14:(832.+7.)++0x00 line.long 0x00 "PIDR7,Processor ID register 7" rgroup.long c14:(832.+8.)++0x00 line.long 0x00 "PIDR8,Processor ID register 8" rgroup.long c14:(832.+9.)++0x00 line.long 0x00 "PIDR9,Processor ID register 9" rgroup.long c14:(832.+10.)++0x00 line.long 0x00 "PIDR10,Processor ID register 10" rgroup.long c14:(832.+11.)++0x00 line.long 0x00 "PIDR11,Processor ID register 11" rgroup.long c14:(832.+12.)++0x00 line.long 0x00 "PIDR12,Processor ID register 12" rgroup.long c14:(832.+13.)++0x00 line.long 0x00 "PIDR13,Processor ID register 13" rgroup.long c14:(832.+14.)++0x00 line.long 0x00 "PIDR14,Processor ID register 14" rgroup.long c14:(832.+15.)++0x00 line.long 0x00 "PIDR15,Processor ID register 15" rgroup.long c14:(832.+16.)++0x00 line.long 0x00 "PIDR16,Processor ID register 16" rgroup.long c14:(832.+17.)++0x00 line.long 0x00 "PIDR17,Processor ID register 17" rgroup.long c14:(832.+18.)++0x00 line.long 0x00 "PIDR18,Processor ID register 18" rgroup.long c14:(832.+19.)++0x00 line.long 0x00 "PIDR19,Processor ID register 19" rgroup.long c14:(832.+20.)++0x00 line.long 0x00 "PIDR20,Processor ID register 20" rgroup.long c14:(832.+21.)++0x00 line.long 0x00 "PIDR21,Processor ID register 21" rgroup.long c14:(832.+22.)++0x00 line.long 0x00 "PIDR22,Processor ID register 22" rgroup.long c14:(832.+23.)++0x00 line.long 0x00 "PIDR23,Processor ID register 23" rgroup.long c14:(832.+24.)++0x00 line.long 0x00 "PIDR24,Processor ID register 24" rgroup.long c14:(832.+25.)++0x00 line.long 0x00 "PIDR25,Processor ID register 25" rgroup.long c14:(832.+26.)++0x00 line.long 0x00 "PIDR26,Processor ID register 26" rgroup.long c14:(832.+27.)++0x00 line.long 0x00 "PIDR27,Processor ID register 27" rgroup.long c14:(832.+28.)++0x00 line.long 0x00 "PIDR28,Processor ID register 28" rgroup.long c14:(832.+29.)++0x00 line.long 0x00 "PIDR29,Processor ID register 29" rgroup.long c14:(832.+30.)++0x00 line.long 0x00 "PIDR30,Processor ID register 30" rgroup.long c14:(832.+31.)++0x00 line.long 0x00 "PIDR31,Processor ID register 31" rgroup.long c14:(832.+32.)++0x00 line.long 0x00 "PIDR32,Processor ID register 32" rgroup.long c14:(832.+33.)++0x00 line.long 0x00 "PIDR33,Processor ID register 33" rgroup.long c14:(832.+34.)++0x00 line.long 0x00 "PIDR34,Processor ID register 34" rgroup.long c14:(832.+35.)++0x00 line.long 0x00 "PIDR35,Processor ID register 35" rgroup.long c14:(832.+36.)++0x00 line.long 0x00 "PIDR36,Processor ID register 36" rgroup.long c14:(832.+37.)++0x00 line.long 0x00 "PIDR37,Processor ID register 37" rgroup.long c14:(832.+38.)++0x00 line.long 0x00 "PIDR38,Processor ID register 38" rgroup.long c14:(832.+39.)++0x00 line.long 0x00 "PIDR39,Processor ID register 39" rgroup.long c14:(832.+40.)++0x00 line.long 0x00 "PIDR40,Processor ID register 40" rgroup.long c14:(832.+41.)++0x00 line.long 0x00 "PIDR41,Processor ID register 41" rgroup.long c14:(832.+42.)++0x00 line.long 0x00 "PIDR42,Processor ID register 42" rgroup.long c14:(832.+43.)++0x00 line.long 0x00 "PIDR43,Processor ID register 43" rgroup.long c14:(832.+44.)++0x00 line.long 0x00 "PIDR44,Processor ID register 44" rgroup.long c14:(832.+45.)++0x00 line.long 0x00 "PIDR45,Processor ID register 45" rgroup.long c14:(832.+46.)++0x00 line.long 0x00 "PIDR46,Processor ID register 46" rgroup.long c14:(832.+47.)++0x00 line.long 0x00 "PIDR47,Processor ID register 47" rgroup.long c14:(832.+48.)++0x00 line.long 0x00 "PIDR48,Processor ID register 48" rgroup.long c14:(832.+49.)++0x00 line.long 0x00 "PIDR49,Processor ID register 49" rgroup.long c14:(832.+50.)++0x00 line.long 0x00 "PIDR50,Processor ID register 50" rgroup.long c14:(832.+51.)++0x00 line.long 0x00 "PIDR51,Processor ID register 51" rgroup.long c14:(832.+52.)++0x00 line.long 0x00 "PIDR52,Processor ID register 52" rgroup.long c14:(832.+53.)++0x00 line.long 0x00 "PIDR53,Processor ID register 53" rgroup.long c14:(832.+54.)++0x00 line.long 0x00 "PIDR54,Processor ID register 54" rgroup.long c14:(832.+55.)++0x00 line.long 0x00 "PIDR55,Processor ID register 55" rgroup.long c14:(832.+56.)++0x00 line.long 0x00 "PIDR56,Processor ID register 56" rgroup.long c14:(832.+57.)++0x00 line.long 0x00 "PIDR57,Processor ID register 57" rgroup.long c14:(832.+58.)++0x00 line.long 0x00 "PIDR58,Processor ID register 58" rgroup.long c14:(832.+59.)++0x00 line.long 0x00 "PIDR59,Processor ID register 59" rgroup.long c14:(832.+60.)++0x00 line.long 0x00 "PIDR60,Processor ID register 60" rgroup.long c14:(832.+61.)++0x00 line.long 0x00 "PIDR61,Processor ID register 61" rgroup.long c14:(832.+62.)++0x00 line.long 0x00 "PIDR62,Processor ID register 62" rgroup.long c14:(832.+63.)++0x00 line.long 0x00 "PIDR63,Processor ID register 63" tree.end tree "Coresight Management Registers" group.long c14:960.++0x0 line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register" bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group.long c14:1000.++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set" group.long c14:1001.++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" textline " " rgroup.long c14:1006.++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" textline " " bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..." endif textline " " rgroup.long c14:1010.++0x0 line.long 0x0 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..." bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..." bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." textline " " rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Debug Device Type Register" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:1016.++0x00 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup.long c14:1017.++0x00 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup.long c14:1018.++0x00 line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup.long c14:1019.++0x00 line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup.long c14:1012.++0x00 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup.long c14:1020.++0x00 line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup.long c14:1021.++0x00 line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup.long c14:1022.++0x00 line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup.long c14:1023.++0x00 line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 10. tree "Breakpoint Registers" if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+0.)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+1.)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+2.)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+3.)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+4.)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+5.)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" group.long c14:148.++0x0 line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" group.long c14:149.++0x0 line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" tree.end width 10. tree "Watchpoint Control Registers" group.long c14:(96.+0.)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+1.)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+2.)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+3.)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif tree.end width 0xb tree.open "Interrupt Controller (GIC-400)" width 17. width 17. base ad:0x31001000 tree "Distributor Interface" if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(ad:0x31001000) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" if PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0080) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)" else group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0084)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0088)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x008C)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0090)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0094)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x0098)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x009C)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00A0)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00A4)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00A8)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00AC)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00B0)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00B4)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00B8)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00BC)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00C0)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00C4)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00C8)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00CC)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00D0)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00D4)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00D8)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00DC)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00E0)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x0E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00E4)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00E8)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00EC)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00F0)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x0F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00F4)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00F8)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(ad:0x31001000+0x00FC)) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0x31001000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else rgroup.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else rgroup.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Not pending,Pending" else rgroup.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(ad:0x31001000+0x08))&0xFF000000)==(0x0000000||0x1000000)) rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x037C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else rgroup.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" rgroup.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" rgroup.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" rgroup.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" rgroup.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" rgroup.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" rgroup.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(ad:0x31001000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" rgroup.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else rgroup.long 0x0D60++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0x31001000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xFD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" rgroup.byte 0xFD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" rgroup.byte 0xFDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end width 0x0B base ad:0x31002000 width 17. tree "CPU Interface" if (((per.l(ad:0x31001000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " else if PER.ADDRESS.isSECUREEX(ad:0x31002000) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Secure access)" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " endif endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(ad:0x31002000+0x0008) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif hgroup.long 0x0020++0x003 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) wgroup.long 0x0024++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" else hgroup.long 0x0024++0x03 hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hgroup.long 0x0028++0x03 hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" endif group.long 0x00D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" if (((per.l(ad:0x31001000+0x04))&0x400)==0x400) group.long 0x00E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" else hgroup.long 0x00E0++0x03 hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end sif CPU.FEATURE(hypervisor) base ad:0x31004000 width 12. tree "Virtual CPU Control Interface" group.long 0x0000++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x008++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1" bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1" textline " " bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1" bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1" bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1" rgroup.long 0x0010++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt" rgroup.long 0x020++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x0030++0x03 line.long 0x00 "GICH_ELSR0,Empty List register Status Register" bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty" bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty" bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty" textline " " bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty" group.long 0x00F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" if (((per.l(ad:0x31004000+0x100))&0x80000000)==0x80000000) group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0x31004000+0x104))&0x80000000)==0x80000000) group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0x31004000+0x108))&0x80000000)==0x80000000) group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0x31004000+0x10C))&0x80000000)==0x80000000) group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif tree.end base ad:0x31006000 width 12. tree "Virtual CPU Interface" group.long 0x0000++0x03 line.long 0x00 "GICV_CTLR,Virtual Machine Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs" textline " " bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x0004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x000C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICV_EOIR,VM End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x001C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x0020++0x03 hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" in wgroup.long 0x0024++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x00D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" rgroup.long 0x00FC++0x03 line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end endif width 0x0B tree.end AUTOINDENT.POP tree.end else tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. tree.open "RDC (Resource Domain Control)" tree "RDC Common Registers" base ad:0x303D0000 width 13. rgroup.long 0x00++0x03 line.long 0x00 "RDC_VIR,Version Information" hexmask.long.byte 0x00 20.--27. 1. " NRGN ,Number of memory regions" hexmask.long.byte 0x00 12.--19. 1. " NPER ,Number of peripherals" hexmask.long.byte 0x00 4.--11. 1. " NMSTR ,Number of masters" bitfld.long 0x00 0.--3. " NDID ,Number of domains" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x24++0x0B line.long 0x00 "RDC_STAT,Status" bitfld.long 0x00 8. " PDS ,Power domain status" "Off,On" bitfld.long 0x00 0.--3. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3,Domain 4,Domain 5,Domain 6,Domain 7,Domain 8,Domain 9,Domain 10,Domain 11,Domain 12,Domain 13,Domain 14,Domain 15" line.long 0x04 "RDC_INTCTRL,Interrupt And Control" bitfld.long 0x04 0. " RCI_EN ,Restoration complete interrupt" "Disabled,Enabled" line.long 0x08 "RDC_INTSTAT,Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt status" "No interrupt,Interrupt" width 7. tree "Master Domain Assignment" group.long 0x200++0x03 line.long 0x00 "MDA0,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x204++0x03 line.long 0x00 "MDA1,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x208++0x03 line.long 0x00 "MDA2,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x20C++0x03 line.long 0x00 "MDA3,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x210++0x03 line.long 0x00 "MDA4,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x214++0x03 line.long 0x00 "MDA5,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x218++0x03 line.long 0x00 "MDA6,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x21C++0x03 line.long 0x00 "MDA7,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x220++0x03 line.long 0x00 "MDA8,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x224++0x03 line.long 0x00 "MDA9,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x228++0x03 line.long 0x00 "MDA10,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x22C++0x03 line.long 0x00 "MDA11,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x230++0x03 line.long 0x00 "MDA12,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x234++0x03 line.long 0x00 "MDA13,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x238++0x03 line.long 0x00 "MDA14,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x23C++0x03 line.long 0x00 "MDA15,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x240++0x03 line.long 0x00 "MDA16,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x244++0x03 line.long 0x00 "MDA17,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x248++0x03 line.long 0x00 "MDA18,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x24C++0x03 line.long 0x00 "MDA19,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x250++0x03 line.long 0x00 "MDA20,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x254++0x03 line.long 0x00 "MDA21,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x258++0x03 line.long 0x00 "MDA22,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x25C++0x03 line.long 0x00 "MDA23,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x260++0x03 line.long 0x00 "MDA24,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x264++0x03 line.long 0x00 "MDA25,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x268++0x03 line.long 0x00 "MDA26,Master Domain Assignment" bitfld.long 0x00 31. " LCK ,LCK" "Not locked,Locked" bitfld.long 0x00 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" tree.end width 9. tree "Peripheral Domain Access Permissions" group.long 0x400++0x03 line.long 0x00 "PDAP0,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x404++0x03 line.long 0x00 "PDAP1,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x408++0x03 line.long 0x00 "PDAP2,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x40C++0x03 line.long 0x00 "PDAP3,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x410++0x03 line.long 0x00 "PDAP4,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x414++0x03 line.long 0x00 "PDAP5,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x418++0x03 line.long 0x00 "PDAP6,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x41C++0x03 line.long 0x00 "PDAP7,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x420++0x03 line.long 0x00 "PDAP8,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x424++0x03 line.long 0x00 "PDAP9,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x428++0x03 line.long 0x00 "PDAP10,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x42C++0x03 line.long 0x00 "PDAP11,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x430++0x03 line.long 0x00 "PDAP12,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x434++0x03 line.long 0x00 "PDAP13,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x438++0x03 line.long 0x00 "PDAP14,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x43C++0x03 line.long 0x00 "PDAP15,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x440++0x03 line.long 0x00 "PDAP16,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x444++0x03 line.long 0x00 "PDAP17,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x448++0x03 line.long 0x00 "PDAP18,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x44C++0x03 line.long 0x00 "PDAP19,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x450++0x03 line.long 0x00 "PDAP20,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x454++0x03 line.long 0x00 "PDAP21,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x458++0x03 line.long 0x00 "PDAP22,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x45C++0x03 line.long 0x00 "PDAP23,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x460++0x03 line.long 0x00 "PDAP24,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x464++0x03 line.long 0x00 "PDAP25,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x468++0x03 line.long 0x00 "PDAP26,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x46C++0x03 line.long 0x00 "PDAP27,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x470++0x03 line.long 0x00 "PDAP28,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x474++0x03 line.long 0x00 "PDAP29,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x478++0x03 line.long 0x00 "PDAP30,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x47C++0x03 line.long 0x00 "PDAP31,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x480++0x03 line.long 0x00 "PDAP32,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x484++0x03 line.long 0x00 "PDAP33,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x488++0x03 line.long 0x00 "PDAP34,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x48C++0x03 line.long 0x00 "PDAP35,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x490++0x03 line.long 0x00 "PDAP36,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x494++0x03 line.long 0x00 "PDAP37,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x498++0x03 line.long 0x00 "PDAP38,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x49C++0x03 line.long 0x00 "PDAP39,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4A0++0x03 line.long 0x00 "PDAP40,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4A4++0x03 line.long 0x00 "PDAP41,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4A8++0x03 line.long 0x00 "PDAP42,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4AC++0x03 line.long 0x00 "PDAP43,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4B0++0x03 line.long 0x00 "PDAP44,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4B4++0x03 line.long 0x00 "PDAP45,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4B8++0x03 line.long 0x00 "PDAP46,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4BC++0x03 line.long 0x00 "PDAP47,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4C0++0x03 line.long 0x00 "PDAP48,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4C4++0x03 line.long 0x00 "PDAP49,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4C8++0x03 line.long 0x00 "PDAP50,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4CC++0x03 line.long 0x00 "PDAP51,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4D0++0x03 line.long 0x00 "PDAP52,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4D4++0x03 line.long 0x00 "PDAP53,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4D8++0x03 line.long 0x00 "PDAP54,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4DC++0x03 line.long 0x00 "PDAP55,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4E0++0x03 line.long 0x00 "PDAP56,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4E4++0x03 line.long 0x00 "PDAP57,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4E8++0x03 line.long 0x00 "PDAP58,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4EC++0x03 line.long 0x00 "PDAP59,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4F0++0x03 line.long 0x00 "PDAP60,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4F4++0x03 line.long 0x00 "PDAP61,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4F8++0x03 line.long 0x00 "PDAP62,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x4FC++0x03 line.long 0x00 "PDAP63,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x500++0x03 line.long 0x00 "PDAP64,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x504++0x03 line.long 0x00 "PDAP65,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x508++0x03 line.long 0x00 "PDAP66,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x50C++0x03 line.long 0x00 "PDAP67,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x510++0x03 line.long 0x00 "PDAP68,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x514++0x03 line.long 0x00 "PDAP69,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x518++0x03 line.long 0x00 "PDAP70,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x51C++0x03 line.long 0x00 "PDAP71,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x520++0x03 line.long 0x00 "PDAP72,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x524++0x03 line.long 0x00 "PDAP73,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x528++0x03 line.long 0x00 "PDAP74,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x52C++0x03 line.long 0x00 "PDAP75,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x530++0x03 line.long 0x00 "PDAP76,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x534++0x03 line.long 0x00 "PDAP77,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x538++0x03 line.long 0x00 "PDAP78,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x53C++0x03 line.long 0x00 "PDAP79,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x540++0x03 line.long 0x00 "PDAP80,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x544++0x03 line.long 0x00 "PDAP81,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x548++0x03 line.long 0x00 "PDAP82,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x54C++0x03 line.long 0x00 "PDAP83,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x550++0x03 line.long 0x00 "PDAP84,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x554++0x03 line.long 0x00 "PDAP85,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x558++0x03 line.long 0x00 "PDAP86,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x55C++0x03 line.long 0x00 "PDAP87,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x560++0x03 line.long 0x00 "PDAP88,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x564++0x03 line.long 0x00 "PDAP89,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x568++0x03 line.long 0x00 "PDAP90,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x56C++0x03 line.long 0x00 "PDAP91,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x570++0x03 line.long 0x00 "PDAP92,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x574++0x03 line.long 0x00 "PDAP93,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x578++0x03 line.long 0x00 "PDAP94,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x57C++0x03 line.long 0x00 "PDAP95,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x580++0x03 line.long 0x00 "PDAP96,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x584++0x03 line.long 0x00 "PDAP97,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x588++0x03 line.long 0x00 "PDAP98,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x58C++0x03 line.long 0x00 "PDAP99,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x590++0x03 line.long 0x00 "PDAP100,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x594++0x03 line.long 0x00 "PDAP101,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x598++0x03 line.long 0x00 "PDAP102,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x59C++0x03 line.long 0x00 "PDAP103,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5A0++0x03 line.long 0x00 "PDAP104,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5A4++0x03 line.long 0x00 "PDAP105,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5A8++0x03 line.long 0x00 "PDAP106,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5AC++0x03 line.long 0x00 "PDAP107,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5B0++0x03 line.long 0x00 "PDAP108,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5B4++0x03 line.long 0x00 "PDAP109,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5B8++0x03 line.long 0x00 "PDAP110,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5BC++0x03 line.long 0x00 "PDAP111,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5C0++0x03 line.long 0x00 "PDAP112,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5C4++0x03 line.long 0x00 "PDAP113,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5C8++0x03 line.long 0x00 "PDAP114,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5CC++0x03 line.long 0x00 "PDAP115,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5D0++0x03 line.long 0x00 "PDAP116,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" textline " " group.long 0x5D4++0x03 line.long 0x00 "PDAP117,Peripheral Domain Access Permissions" bitfld.long 0x00 31. " LCK ,Peripheral permissions lock" "Not locked,Locked" bitfld.long 0x00 30. " SREQ ,Semaphore required" "Not required,Required" textline " " bitfld.long 0x00 7. " D3R ,Domain 3 read access" "Not allowed,Allowed" bitfld.long 0x00 6. " D3W ,Domain 3 write access" "Not allowed,Allowed" bitfld.long 0x00 5. " D2R ,Domain 2 read access" "Not allowed,Allowed" bitfld.long 0x00 4. " D2W ,Domain 2 write access" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " D1R ,Domain 1 read access" "Not allowed,Allowed" bitfld.long 0x00 2. " D1W ,Domain 1 write access" "Not allowed,Allowed" bitfld.long 0x00 1. " D0R ,Domain 0 read access" "Not allowed,Allowed" bitfld.long 0x00 0. " D0W ,Domain 0 write access" "Not allowed,Allowed" tree.end width 8. tree "Memory Region Registers" group.long 0x800++0x0F "Memory Region 0" line.long 0x00 "MRSA0,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA0,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC0,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS0,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x810++0x0F "Memory Region 1" line.long 0x00 "MRSA1,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA1,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC1,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS1,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x820++0x0F "Memory Region 2" line.long 0x00 "MRSA2,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA2,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC2,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS2,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x830++0x0F "Memory Region 3" line.long 0x00 "MRSA3,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA3,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC3,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS3,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x840++0x0F "Memory Region 4" line.long 0x00 "MRSA4,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA4,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC4,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS4,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x850++0x0F "Memory Region 5" line.long 0x00 "MRSA5,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA5,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC5,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS5,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x860++0x0F "Memory Region 6" line.long 0x00 "MRSA6,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA6,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC6,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS6,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x870++0x0F "Memory Region 7" line.long 0x00 "MRSA7,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA7,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC7,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS7,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x880++0x0F "Memory Region 8" line.long 0x00 "MRSA8,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA8,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC8,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS8,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x890++0x0F "Memory Region 9" line.long 0x00 "MRSA9,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA9,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC9,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS9,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8A0++0x0F "Memory Region 10" line.long 0x00 "MRSA10,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA10,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC10,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS10,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8B0++0x0F "Memory Region 11" line.long 0x00 "MRSA11,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA11,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC11,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS11,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8C0++0x0F "Memory Region 12" line.long 0x00 "MRSA12,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA12,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC12,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS12,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8D0++0x0F "Memory Region 13" line.long 0x00 "MRSA13,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA13,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC13,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS13,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8E0++0x0F "Memory Region 14" line.long 0x00 "MRSA14,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA14,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC14,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS14,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x8F0++0x0F "Memory Region 15" line.long 0x00 "MRSA15,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA15,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC15,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS15,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x900++0x0F "Memory Region 16" line.long 0x00 "MRSA16,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA16,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC16,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS16,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x910++0x0F "Memory Region 17" line.long 0x00 "MRSA17,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA17,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC17,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS17,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x920++0x0F "Memory Region 18" line.long 0x00 "MRSA18,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA18,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC18,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS18,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x930++0x0F "Memory Region 19" line.long 0x00 "MRSA19,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA19,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC19,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS19,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x940++0x0F "Memory Region 20" line.long 0x00 "MRSA20,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA20,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC20,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS20,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x950++0x0F "Memory Region 21" line.long 0x00 "MRSA21,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA21,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC21,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS21,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x960++0x0F "Memory Region 22" line.long 0x00 "MRSA22,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA22,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC22,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS22,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x970++0x0F "Memory Region 23" line.long 0x00 "MRSA23,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA23,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC23,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS23,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x980++0x0F "Memory Region 24" line.long 0x00 "MRSA24,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA24,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC24,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS24,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x990++0x0F "Memory Region 25" line.long 0x00 "MRSA25,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA25,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC25,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS25,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9A0++0x0F "Memory Region 26" line.long 0x00 "MRSA26,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA26,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC26,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS26,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9B0++0x0F "Memory Region 27" line.long 0x00 "MRSA27,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA27,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC27,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS27,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9C0++0x0F "Memory Region 28" line.long 0x00 "MRSA28,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA28,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC28,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS28,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9D0++0x0F "Memory Region 29" line.long 0x00 "MRSA29,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA29,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC29,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS29,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9E0++0x0F "Memory Region 30" line.long 0x00 "MRSA30,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA30,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC30,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS30,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x9F0++0x0F "Memory Region 31" line.long 0x00 "MRSA31,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA31,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC31,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS31,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA00++0x0F "Memory Region 32" line.long 0x00 "MRSA32,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA32,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC32,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS32,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA10++0x0F "Memory Region 33" line.long 0x00 "MRSA33,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA33,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC33,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS33,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA20++0x0F "Memory Region 34" line.long 0x00 "MRSA34,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA34,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC34,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS34,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA30++0x0F "Memory Region 35" line.long 0x00 "MRSA35,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA35,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC35,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS35,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA40++0x0F "Memory Region 36" line.long 0x00 "MRSA36,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA36,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC36,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS36,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA50++0x0F "Memory Region 37" line.long 0x00 "MRSA37,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA37,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC37,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS37,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA60++0x0F "Memory Region 38" line.long 0x00 "MRSA38,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA38,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC38,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS38,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA70++0x0F "Memory Region 39" line.long 0x00 "MRSA39,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA39,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC39,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS39,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA80++0x0F "Memory Region 40" line.long 0x00 "MRSA40,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA40,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC40,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS40,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xA90++0x0F "Memory Region 41" line.long 0x00 "MRSA41,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA41,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC41,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS41,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAA0++0x0F "Memory Region 42" line.long 0x00 "MRSA42,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA42,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC42,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS42,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAB0++0x0F "Memory Region 43" line.long 0x00 "MRSA43,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA43,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC43,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS43,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAC0++0x0F "Memory Region 44" line.long 0x00 "MRSA44,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA44,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC44,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS44,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAD0++0x0F "Memory Region 45" line.long 0x00 "MRSA45,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA45,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC45,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS45,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAE0++0x0F "Memory Region 46" line.long 0x00 "MRSA46,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA46,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC46,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS46,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xAF0++0x0F "Memory Region 47" line.long 0x00 "MRSA47,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA47,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC47,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS47,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xB00++0x0F "Memory Region 48" line.long 0x00 "MRSA48,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA48,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC48,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS48,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xB10++0x0F "Memory Region 49" line.long 0x00 "MRSA49,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA49,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC49,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS49,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xB20++0x0F "Memory Region 50" line.long 0x00 "MRSA50,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA50,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC50,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS50,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0xB30++0x0F "Memory Region 51" line.long 0x00 "MRSA51,Memory Region Start Address" hexmask.long 0x00 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x04 "MREA51,Memory Region End Address" hexmask.long 0x04 7.--31. 0x80 " EADR ,Upper bound for memory region" line.long 0x08 "MRC51,Memory Region Control" bitfld.long 0x08 31. " LCK ,Region lock" "Not locked,Locked" bitfld.long 0x08 30. " ENA ,Region enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " D3R ,Domain 3 read access to region" "No access,Access" bitfld.long 0x08 6. " D3W ,Domain 3 write access to region" "No access,Access" bitfld.long 0x08 5. " D2R ,Domain 2 read access to region" "No access,Access" bitfld.long 0x08 4. " D2W ,Domain 2 write access to region" "No access,Access" textline " " bitfld.long 0x08 3. " D1R ,Domain 1 read access to region" "No access,Access" bitfld.long 0x08 2. " D1W ,Domain 1 write access to region" "No access,Access" bitfld.long 0x08 1. " D0R ,Domain 0 read access to region" "No access,Access" bitfld.long 0x08 0. " D0W ,Domain 0 write access to region" "No access,Access" line.long 0x0C "MRVS51,Memory Region Violation Status" hexmask.long 0x0C 5.--31. 0x20 " VADR ,Violating address" eventfld.long 0x0C 4. " AD ,Access denied" "Allowed,Denied" rbitfld.long 0x0C 0.--1. " VDID ,Violating domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" tree.end width 0x0B tree.end tree.open "RDC SEMA42 (Resource Domain Control Semaphore)" tree "Semaphore 1" base ad:0x303B0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "GATE0,Gate Register 0" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "GATE1,Gate Register 1" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "GATE2,Gate Register 2" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "GATE3,Gate Register 3" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "GATE4,Gate Register 4" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "GATE5,Gate Register 5" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "GATE6,Gate Register 6" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "GATE7,Gate Register 7" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "GATE8,Gate Register 8" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "GATE9,Gate Register 9" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "GATE10,Gate Register 10" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "GATE11,Gate Register 11" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "GATE12,Gate Register 12" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "GATE13,Gate Register 13" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "GATE14,Gate Register 14" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "GATE15,Gate Register 15" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "GATE16,Gate Register 16" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "GATE17,Gate Register 17" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "GATE18,Gate Register 18" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "GATE19,Gate Register 19" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "GATE20,Gate Register 20" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "GATE21,Gate Register 21" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "GATE22,Gate Register 22" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "GATE23,Gate Register 23" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "GATE24,Gate Register 24" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "GATE25,Gate Register 25" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "GATE26,Gate Register 26" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "GATE27,Gate Register 27" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "GATE28,Gate Register 28" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "GATE29,Gate Register 29" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "GATE30,Gate Register 30" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "GATE31,Gate Register 31" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "GATE32,Gate Register 32" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "GATE33,Gate Register 33" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "GATE34,Gate Register 34" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "GATE35,Gate Register 35" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "GATE36,Gate Register 36" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "GATE37,Gate Register 37" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "GATE38,Gate Register 38" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "GATE39,Gate Register 39" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "GATE40,Gate Register 40" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "GATE41,Gate Register 41" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "GATE42,Gate Register 42" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "GATE43,Gate Register 43" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "GATE44,Gate Register 44" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "GATE45,Gate Register 45" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "GATE46,Gate Register 46" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "GATE47,Gate Register 47" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "GATE48,Gate Register 48" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "GATE49,Gate Register 49" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "GATE50,Gate Register 50" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "GATE51,Gate Register 51" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "GATE52,Gate Register 52" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "GATE53,Gate Register 53" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "GATE54,Gate Register 54" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "GATE55,Gate Register 55" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "GATE56,Gate Register 56" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "GATE57,Gate Register 57" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "GATE58,Gate Register 58" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "GATE59,Gate Register 59" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "GATE60,Gate Register 60" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "GATE61,Gate Register 61" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "GATE62,Gate Register 62" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "GATE63,Gate Register 63" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" textline " " group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset gate data pattern" group.word 0x40++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" rbitfld.word 0x00 4.--5. " RSTGMS ,Reset gate finite state machine" "Idle,Wait for 2nd data pattern write,2-write completed,?..." textline " " rbitfld.word 0x00 0.--3. " RSTGBM ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "Semaphore 2" base ad:0x303C0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "GATE0,Gate Register 0" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "GATE1,Gate Register 1" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "GATE2,Gate Register 2" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "GATE3,Gate Register 3" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "GATE4,Gate Register 4" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "GATE5,Gate Register 5" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "GATE6,Gate Register 6" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "GATE7,Gate Register 7" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "GATE8,Gate Register 8" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "GATE9,Gate Register 9" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "GATE10,Gate Register 10" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "GATE11,Gate Register 11" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "GATE12,Gate Register 12" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "GATE13,Gate Register 13" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "GATE14,Gate Register 14" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "GATE15,Gate Register 15" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "GATE16,Gate Register 16" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "GATE17,Gate Register 17" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "GATE18,Gate Register 18" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "GATE19,Gate Register 19" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "GATE20,Gate Register 20" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "GATE21,Gate Register 21" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "GATE22,Gate Register 22" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "GATE23,Gate Register 23" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "GATE24,Gate Register 24" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "GATE25,Gate Register 25" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "GATE26,Gate Register 26" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "GATE27,Gate Register 27" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "GATE28,Gate Register 28" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "GATE29,Gate Register 29" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "GATE30,Gate Register 30" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "GATE31,Gate Register 31" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "GATE32,Gate Register 32" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "GATE33,Gate Register 33" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "GATE34,Gate Register 34" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "GATE35,Gate Register 35" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "GATE36,Gate Register 36" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "GATE37,Gate Register 37" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "GATE38,Gate Register 38" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "GATE39,Gate Register 39" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "GATE40,Gate Register 40" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "GATE41,Gate Register 41" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "GATE42,Gate Register 42" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "GATE43,Gate Register 43" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "GATE44,Gate Register 44" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "GATE45,Gate Register 45" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "GATE46,Gate Register 46" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "GATE47,Gate Register 47" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "GATE48,Gate Register 48" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "GATE49,Gate Register 49" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "GATE50,Gate Register 50" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "GATE51,Gate Register 51" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "GATE52,Gate Register 52" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "GATE53,Gate Register 53" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "GATE54,Gate Register 54" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "GATE55,Gate Register 55" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "GATE56,Gate Register 56" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "GATE57,Gate Register 57" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "GATE58,Gate Register 58" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "GATE59,Gate Register 59" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "GATE60,Gate Register 60" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "GATE61,Gate Register 61" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "GATE62,Gate Register 62" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "GATE63,Gate Register 63" rbitfld.byte 0x00 4.--5. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" textline " " group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset gate data pattern" group.word 0x40++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" rbitfld.word 0x00 4.--5. " RSTGMS ,Reset gate finite state machine" "Idle,Wait for 2nd data pattern write,2-write completed,?..." textline " " rbitfld.word 0x00 0.--3. " RSTGBM ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree.end tree.end tree "LMEM (Local Memory Controller)" base ad:0xE0082000 width 8. group.long 0x00++0x07 line.long 0x00 "PCCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Not active,Active" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "No operation,Operation" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "No operation,Operation" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "No operation,Operation" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "No operation,Operation" bitfld.long 0x00 3. " PCCR3 ,Forces no allocation on cache misses" "Not forced,Forced" newline bitfld.long 0x00 2. " PCCR2 ,Forces all cacheable spaces to write through" "Not forced,Forced" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" line.long 0x04 "PCCLCR,Cache Line Control Register" bitfld.long 0x04 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x04 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x04 24.--25. " LCMD ,Line command" "Search & read|write,Invalidate,Push,Clear" newline rbitfld.long 0x04 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x04 21. " LCIMB ,Line command initial modified bit" "Not modified,Modified" rbitfld.long 0x04 20. " LCIVB ,Line command initial valid bit" "Invalid,Valid" newline bitfld.long 0x04 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x04 14. " WSEL ,Way select" "Way 0,Way 1" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x04 3.--13. 0x08 " CACHEADDR ,Cache address" else hexmask.long.word 0x04 2.--12. 0x04 " CACHEADDR ,Cache address" endif newline bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Inactive,Active" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x08++0x03 line.long 0x00 "PCCSAR,Cache Search Address Register" hexmask.long 0x00 3.--31. 0x08 " PHYADDR ,Physical address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Inactive,Active" if ((per.l(ad:0xE0082000+0x04)&0x10000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/write Value Register" hexmask.long 0x00 0.--31. 1. " CCVR[31:0] ,Data array" else group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " CCVR[31:12] ,Tag array" hexmask.long.word 0x00 5.--11. 0x20 " CCVR[11:5] ,Tag address" bitfld.long 0x00 1. " CCVR[1] ,Tag modify" "0,1" newline bitfld.long 0x00 0. " CCVR[0] ,Tag valid" "0,1" endif else group.long 0x08++0x07 line.long 0x00 "PCCSAR,Cache Search Address Register" hexmask.long 0x00 2.--31. 0x04 " PHYADDR ,Physical address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Inactive,Active" line.long 0x04 "PCCCVR,Cache Read/write Value Register" group.long 0x800++0x0F line.long 0x00 "PSCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Inactive,Active" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "No operation,Operation" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "No operation,Operation" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "No operation,Operation" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "No operation,Operation" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" line.long 0x04 "PSCLCR,Cache Line Control Register" bitfld.long 0x04 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x04 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x04 24.--25. " LCMD ,Line command" "Search & read|write,Invalidate,Push,Clear" newline rbitfld.long 0x04 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x04 21. " LCIMB ,Line command initial modified bit" "Not modified,Modified" rbitfld.long 0x04 20. " LCIVB ,Line command initial valid bit" "Invalid,Valid" newline bitfld.long 0x04 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x04 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.word 0x04 2.--12. 0x04 " CACHEADDR ,Cache address" newline bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Inactive,Active" line.long 0x08 "PSCSAR,Cache Search Address Register" hexmask.long 0x08 2.--31. 0x04 " PHYADDR ,Physical address" bitfld.long 0x08 0. " LGO ,Initiate cache line command" "Inactive,Active" line.long 0x0C "PSCCVR,Cache Read/write Value Register" endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Bus slave connection to AXBS input port 7" "Absent,Present" bitfld.word 0x00 6. " [6] ,Bus slave connection to AXBS input port 6" "Absent,Present" bitfld.word 0x00 5. " [5] ,Bus slave connection to AXBS input port 5" "Absent,Present" bitfld.word 0x00 4. " [4] ,Bus slave connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x00 3. " [3] ,Bus slave connection to AXBS input port 3" "Absent,Present" bitfld.word 0x00 2. " [2] ,Bus slave connection to AXBS input port 2" "Absent,Present" bitfld.word 0x00 1. " [1] ,Bus slave connection to AXBS input port 1" "Absent,Present" bitfld.word 0x00 0. " [0] ,Bus slave connection to AXBS input port 0" "Absent,Present" line.word 0x02 "PLAMC,Crossbar Switch Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Bus master connection to AXBS input port 7" "Absent,Present" bitfld.word 0x02 6. " [6] ,Bus master connection to AXBS input port 6" "Absent,Present" bitfld.word 0x02 5. " [5] ,Bus master connection to AXBS input port 5" "Absent,Present" bitfld.word 0x02 4. " [4] ,Bus master connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x02 3. " [3] ,Bus master connection to AXBS input port 3" "Absent,Present" bitfld.word 0x02 2. " [2] ,Bus master connection to AXBS input port 2" "Absent,Present" bitfld.word 0x02 1. " [1] ,Bus master connection to AXBS input port 1" "Absent,Present" bitfld.word 0x02 0. " [0] ,Bus master connection to AXBS input port 0" "Absent,Present" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x0C++0x03 line.long 0x00 "PLACR,Crossbar Switch (AXBS) Control Register" bitfld.long 0x00 30. " TCRAML_Write_Protect ,TCRAML_Write_Protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " TCRAML_Priority ,TCRAML_Priority" "0,1,2,3" newline bitfld.long 0x00 26. " TCRAMU_Write_Protect ,TCRAMU_Write_Protect" "Not protected,Protected" bitfld.long 0x00 24.--25. " TCRAMU_Priority ,TCRAMU_Priority" "0,1,2,3" newline bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-Priority,Round-robin" newline endif rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "No error,Error" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" ",1,?..." bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MUA (MU Processor A-side)" base ad:0x30AA0000 width 7. if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x14)))==(1<<(0x14))) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x15)))==(1<<(0x15))) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x16)))==(1<<(0x16))) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x17)))==(1<<(0x17))) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x18)))==(1<<(0x18))) hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in. else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x19)))==(1<<(0x19))) hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in. else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x1A)))==(1<<(0x1A))) hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in. else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" endif if (((per.l(ad:0x30AA0000+0x20))&(1<<(0x1B)))==(1<<(0x1B))) hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in. else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" eventfld.long 0x00 31. " GIP3 ,Processor A general interrupt request 3 pending" "Not pending,Pending" eventfld.long 0x00 30. " GIP2 ,Processor A general interrupt request 2 pending" "Not pending,Pending" eventfld.long 0x00 29. " GIP1 ,Processor A general interrupt request 1 pending" "Not pending,Pending" eventfld.long 0x00 28. " GIP0 ,Processor A general interrupt request 0 pending" "Not pending,Pending" textline " " rbitfld.long 0x00 27. " RF3 ,Processor A receive register 3 full" "Not full,Full" rbitfld.long 0x00 26. " RF2 ,Processor A receive register 2 full" "Not full,Full" rbitfld.long 0x00 25. " RF1 ,Processor A receive register 1 full" "Not full,Full" rbitfld.long 0x00 24. " RF0 ,Processor A receive register 0 full" "Not full,Full" textline " " rbitfld.long 0x00 23. " TE3 ,Processor A transmit register 3 empty" "Not empty,Empty" rbitfld.long 0x00 22. " TE2 ,Processor A transmit register 2 empty" "Not empty,Empty" rbitfld.long 0x00 21. " TE1 ,Processor A transmit register 1 empty" "Not empty,Empty" rbitfld.long 0x00 20. " TE0 ,Processor A transmit register 0 empty" "Not empty,Empty" textline " " eventfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" rbitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" rbitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" rbitfld.long 0x00 4. " EP ,Processor A-Side event pending" "Not pending,Pending" textline " " rbitfld.long 0x00 2. " F2 ,Reflects the values written to the BAF2 bit in the processor B control register" "0,1" rbitfld.long 0x00 1. " F1 ,Reflects the values written to the baf1 bit in the processor B control register" "0,1" rbitfld.long 0x00 0. " F0 ,Reflects the values written to the baf0 bit in the processor B control register" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE3 ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " GIE2 ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " GIE1 ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " GIE0 ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE3 ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " RIE2 ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " RIE1 ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " RIE0 ,Processor A receive interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE3 ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " TIE2 ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " TIE1 ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " TIE0 ,Processor A transmit interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR3 ,Processor A general purpose interrupt request 3" "Not requested,Requested" bitfld.long 0x04 18. " GIR2 ,Processor A general purpose interrupt request 2" "Not requested,Requested" bitfld.long 0x04 17. " GIR1 ,Processor A general purpose interrupt request 1" "Not requested,Requested" bitfld.long 0x04 16. " GIR0 ,Processor A general purpose interrupt request 0" "Not requested,Requested" textline " " bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" textline " " bitfld.long 0x04 2. " ABF2 ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " ABF1 ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " ABF0 ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MUB (MU Processor B-side)" base ad:0x30AB0000 width 7. if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x14)))==(1<<(0x14))) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x15)))==(1<<(0x15))) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x16)))==(1<<(0x16))) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x17)))==(1<<(0x17))) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x18)))==(1<<(0x18))) hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in. else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x19)))==(1<<(0x19))) hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in. else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x1A)))==(1<<(0x1A))) hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in. else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" endif if (((per.l(ad:0x30AB0000+0x20))&(1<<(0x1B)))==(1<<(0x1B))) hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in. else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" eventfld.long 0x00 31. " GIP3 ,Processor B general interrupt request 3 pending" "Not pending,Pending" eventfld.long 0x00 30. " GIP2 ,Processor B general interrupt request 2 pending" "Not pending,Pending" eventfld.long 0x00 29. " GIP1 ,Processor B general interrupt request 1 pending" "Not pending,Pending" eventfld.long 0x00 28. " GIP0 ,Processor B general interrupt request 0 pending" "Not pending,Pending" textline " " rbitfld.long 0x00 27. " RF3 ,Processor B receive register 3 full" "Not full,Full" rbitfld.long 0x00 26. " RF2 ,Processor B receive register 2 full" "Not full,Full" rbitfld.long 0x00 25. " RF1 ,Processor B receive register 1 full" "Not full,Full" rbitfld.long 0x00 24. " RF0 ,Processor B receive register 0 full" "Not full,Full" textline " " rbitfld.long 0x00 23. " TE3 ,Processor B transmit register 3 empty" "Not empty,Empty" rbitfld.long 0x00 22. " TE2 ,Processor B transmit register 2 empty" "Not empty,Empty" rbitfld.long 0x00 21. " TE1 ,Processor B transmit register 1 empty" "Not empty,Empty" rbitfld.long 0x00 20. " TE0 ,Processor B transmit register 0 empty" "Not empty,Empty" textline " " rbitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" rbitfld.long 0x00 7. " ARS ,Processor A-side reset state" "Not reset,Reset" rbitfld.long 0x00 5.--6. " APM ,Processor A power mode" "Run,WAIT,,STOP" rbitfld.long 0x00 4. " EP ,Processor B-Side event pending" "Not pending,Pending" textline " " rbitfld.long 0x00 2. " F2 ,Reflects the values written to the ABF2 bit in the processor A control register" "0,1" rbitfld.long 0x00 1. " F1 ,Reflects the values written to the ABF1 bit in the processor A control register" "0,1" rbitfld.long 0x00 0. " F0 ,Reflects the values written to the ABF0 bit in the processor A control register" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE3 ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " GIE2 ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " GIE1 ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " GIE0 ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE3 ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " RIE2 ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " RIE1 ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " RIE0 ,Processor B receive interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE3 ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " TIE2 ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " TIE1 ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " TIE0 ,Processor B transmit interrupt enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR3 ,Processor B general purpose interrupt request 3" "Not requested,Requested" bitfld.long 0x04 18. " GIR2 ,Processor B general purpose interrupt request 2" "Not requested,Requested" bitfld.long 0x04 17. " GIR1 ,Processor B general purpose interrupt request 1" "Not requested,Requested" bitfld.long 0x04 16. " GIR0 ,Processor B general purpose interrupt request 0" "Not requested,Requested" textline " " bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" bitfld.long 0x04 2. " BAF2 ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " BAF1 ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " BAF0 ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree.end tree "SEMA4 (Semaphore)" base ad:0x30AC0000 width 9. group.byte 0x0++0x00 line.byte 0x00 "GATE00,Semaphores Gate 0 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x1++0x00 line.byte 0x00 "GATE01,Semaphores Gate 1 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x2++0x00 line.byte 0x00 "GATE02,Semaphores Gate 2 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x3++0x00 line.byte 0x00 "GATE03,Semaphores Gate 3 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x4++0x00 line.byte 0x00 "GATE04,Semaphores Gate 4 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x5++0x00 line.byte 0x00 "GATE05,Semaphores Gate 5 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x6++0x00 line.byte 0x00 "GATE06,Semaphores Gate 6 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x7++0x00 line.byte 0x00 "GATE07,Semaphores Gate 7 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x8++0x00 line.byte 0x00 "GATE08,Semaphores Gate 8 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0x9++0x00 line.byte 0x00 "GATE09,Semaphores Gate 9 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xA++0x00 line.byte 0x00 "GATE10,Semaphores Gate 10 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xB++0x00 line.byte 0x00 "GATE11,Semaphores Gate 11 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xC++0x00 line.byte 0x00 "GATE12,Semaphores Gate 12 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xD++0x00 line.byte 0x00 "GATE13,Semaphores Gate 13 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xE++0x00 line.byte 0x00 "GATE14,Semaphores Gate 14 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." group.byte 0xF++0x00 line.byte 0x00 "GATE15,Semaphores Gate 15 Register" bitfld.byte 0x00 6.--7. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,?..." newline group.word 0x40++0x01 line.word 0x00 "CP0INE,Semaphores Processor N IRQ Notification Enable" bitfld.word 0x00 15. " INE8 ,Interrupt request notification enable 8" "Disabled,Enabled" bitfld.word 0x00 14. " INE9 ,Interrupt request notification enable 9" "Disabled,Enabled" bitfld.word 0x00 13. " INE10 ,Interrupt request notification enable 10" "Disabled,Enabled" bitfld.word 0x00 12. " INE11 ,Interrupt request notification enable 11" "Disabled,Enabled" newline bitfld.word 0x00 11. " INE12 ,Interrupt request notification enable 12" "Disabled,Enabled" bitfld.word 0x00 10. " INE13 ,Interrupt request notification enable 13" "Disabled,Enabled" bitfld.word 0x00 9. " INE14 ,Interrupt request notification enable 14" "Disabled,Enabled" bitfld.word 0x00 8. " INE15 ,Interrupt request notification enable 15" "Disabled,Enabled" newline bitfld.word 0x00 7. " INE0 ,Interrupt request notification enable 0" "Disabled,Enabled" bitfld.word 0x00 6. " INE1 ,Interrupt request notification enable 1" "Disabled,Enabled" bitfld.word 0x00 5. " INE2 ,Interrupt request notification enable 2" "Disabled,Enabled" bitfld.word 0x00 4. " INE3 ,Interrupt request notification enable 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " INE4 ,Interrupt request notification enable 4" "Disabled,Enabled" bitfld.word 0x00 2. " INE5 ,Interrupt request notification enable 5" "Disabled,Enabled" bitfld.word 0x00 1. " INE6 ,Interrupt request notification enable 6" "Disabled,Enabled" bitfld.word 0x00 0. " INE7 ,Interrupt request notification enable 7" "Disabled,Enabled" rgroup.word (0x40+0x40)++0x01 line.word 0x00 "CP0NTF,Semaphores Processor N IRQ Notification" bitfld.word 0x00 15. " GN8 ,Gate 8 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 14. " GN9 ,Gate 9 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 13. " GN10 ,Gate 10 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 12. " GN11 ,Gate 11 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 11. " GN12 ,Gate 12 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 10. " GN13 ,Gate 13 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 9. " GN14 ,Gate 14 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 8. " GN15 ,Gate 15 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 7. " GN0 ,Gate 0 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 6. " GN1 ,Gate 1 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 5. " GN2 ,Gate 2 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 4. " GN3 ,Gate 3 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 3. " GN4 ,Gate 4 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 2. " GN5 ,Gate 5 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 1. " GN6 ,Gate 6 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 0. " GN7 ,Gate 7 failed lock attempt IRQ notification" "No interrupt,Interrupt" group.word 0x48++0x01 line.word 0x00 "CP1INE,Semaphores Processor N IRQ Notification Enable" bitfld.word 0x00 15. " INE8 ,Interrupt request notification enable 8" "Disabled,Enabled" bitfld.word 0x00 14. " INE9 ,Interrupt request notification enable 9" "Disabled,Enabled" bitfld.word 0x00 13. " INE10 ,Interrupt request notification enable 10" "Disabled,Enabled" bitfld.word 0x00 12. " INE11 ,Interrupt request notification enable 11" "Disabled,Enabled" newline bitfld.word 0x00 11. " INE12 ,Interrupt request notification enable 12" "Disabled,Enabled" bitfld.word 0x00 10. " INE13 ,Interrupt request notification enable 13" "Disabled,Enabled" bitfld.word 0x00 9. " INE14 ,Interrupt request notification enable 14" "Disabled,Enabled" bitfld.word 0x00 8. " INE15 ,Interrupt request notification enable 15" "Disabled,Enabled" newline bitfld.word 0x00 7. " INE0 ,Interrupt request notification enable 0" "Disabled,Enabled" bitfld.word 0x00 6. " INE1 ,Interrupt request notification enable 1" "Disabled,Enabled" bitfld.word 0x00 5. " INE2 ,Interrupt request notification enable 2" "Disabled,Enabled" bitfld.word 0x00 4. " INE3 ,Interrupt request notification enable 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " INE4 ,Interrupt request notification enable 4" "Disabled,Enabled" bitfld.word 0x00 2. " INE5 ,Interrupt request notification enable 5" "Disabled,Enabled" bitfld.word 0x00 1. " INE6 ,Interrupt request notification enable 6" "Disabled,Enabled" bitfld.word 0x00 0. " INE7 ,Interrupt request notification enable 7" "Disabled,Enabled" rgroup.word (0x48+0x40)++0x01 line.word 0x00 "CP1NTF,Semaphores Processor N IRQ Notification" bitfld.word 0x00 15. " GN8 ,Gate 8 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 14. " GN9 ,Gate 9 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 13. " GN10 ,Gate 10 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 12. " GN11 ,Gate 11 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 11. " GN12 ,Gate 12 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 10. " GN13 ,Gate 13 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 9. " GN14 ,Gate 14 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 8. " GN15 ,Gate 15 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 7. " GN0 ,Gate 0 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 6. " GN1 ,Gate 1 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 5. " GN2 ,Gate 2 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 4. " GN3 ,Gate 3 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline bitfld.word 0x00 3. " GN4 ,Gate 4 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 2. " GN5 ,Gate 5 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 1. " GN6 ,Gate 6 failed lock attempt IRQ notification" "No interrupt,Interrupt" bitfld.word 0x00 0. " GN7 ,Gate 7 failed lock attempt IRQ notification" "No interrupt,Interrupt" newline rgroup.word 0x100++0x01 line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate N (Read-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" bitfld.word 0x00 4.--5. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 0.--2. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7" wgroup.word 0x100++0x01 line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate N (Write-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset gate number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset gate data pattern" rgroup.word 0x104++0x01 line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification (Read-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTNTN ,Reset notification number" bitfld.word 0x00 4.--5. " RSTNSM ,Reset notification finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 0.--2. " RSTNMS ,Reset notification bus master" "0,1,2,3,4,5,6,7" wgroup.word 0x104++0x01 line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification (Write-only)" hexmask.word.byte 0x00 8.--15. 1. " RSTNTN ,Reset notification number" hexmask.word.byte 0x00 0.--7. 1. " RSTNDP ,Reset notification data pattern" width 0x0B tree.end tree.open "AIPSTZ (AHB to IP Bridge)" tree "AIPSTZ 1" base ad:0x301F0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Priviledge Registers" bitfld.long 0x00 31. " MPROT0_MBW ,Master 0 buffer control" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0_MTR ,Master 0 read control" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0_MTW ,Master 0 write control" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0_MPL ,Master 0 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1_MBW ,Master 1 buffer control" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1_MTR ,Master 1 read control" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1_MTW ,Master 1 write control" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1_MPL ,Master 1 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2_MBW ,Master 2 buffer control" "Disabled,Enabled" bitfld.long 0x00 22. " MPRO21_MTR ,Master 2 read control" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2_MTW ,Master 2 write control" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2_MPL ,Master 2 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3_MBW ,Master 3 buffer control" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3_MTR ,Master 3 read control" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3_MTW ,Master 3 write control" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3_MPL ,Master 3 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5_MBW ,Master 5 buffer control" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5_MTR ,Master 5 read control" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5_MTW ,Master 5 write control" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5_MPL ,Master 5 priviledge control" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x00 30. " OPAC0_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 29. " OPAC0_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 28. " OPAC0_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 26. " OPAC1_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 25. " OPAC1_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 24. " OPAC1_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 22. " OPAC2_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 21. " OPAC2_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 20. " OPAC2_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 18. " OPAC3_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 17. " OPAC3_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 16. " OPAC3_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 14. " OPAC4_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 13. " OPAC4_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 12. " OPAC4_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 10. " OPAC5_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 9. " OPAC5_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 8. " OPAC5_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 6. " OPAC6_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 5. " OPAC6_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 4. " OPAC6_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 2. " OPAC7_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 1. " OPAC7_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 0. " OPAC7_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Registers" bitfld.long 0x04 30. " OPAC8_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 29. " OPAC8_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 28. " OPAC8_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 26. " OPAC9_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 25. " OPAC9_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 24. " OPAC9_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 22. " OPAC10_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 21. " OPAC10_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 20. " OPAC10_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 18. " OPAC11_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 17. " OPAC11_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 16. " OPAC11_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 14. " OPAC12_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 13. " OPAC12_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 12. " OPAC12_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 10. " OPAC13_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 9. " OPAC13_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 8. " OPAC13_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 6. " OPAC14_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 5. " OPAC14_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 4. " OPAC14_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 2. " OPAC15_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 1. " OPAC15_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 0. " OPAC15_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Registers" bitfld.long 0x08 30. " OPAC16_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 29. " OPAC16_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 28. " OPAC16_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 26. " OPAC17_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 25. " OPAC17_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 24. " OPAC17_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 22. " OPAC18_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 21. " OPAC18_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 20. " OPAC18_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 18. " OPAC19_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 17. " OPAC19_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 16. " OPAC19_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 14. " OPAC20_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 13. " OPAC20_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 12. " OPAC20_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 10. " OPAC21_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 9. " OPAC21_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 8. " OPAC21_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 6. " OPAC22_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 5. " OPAC22_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 4. " OPAC22_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 2. " OPAC23_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 1. " OPAC23_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 0. " OPAC23_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0C 30. " OPAC24_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 29. " OPAC24_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 28. " OPAC24_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 26. " OPAC25_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 25. " OPAC25_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 24. " OPAC25_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 22. " OPAC26_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 21. " OPAC26_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 20. " OPAC26_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 18. " OPAC27_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 17. " OPAC27_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 16. " OPAC27_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 14. " OPAC28_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 13. " OPAC28_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 12. " OPAC28_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 10. " OPAC29_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 9. " OPAC29_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 8. " OPAC29_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 6. " OPAC30_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 5. " OPAC30_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 4. " OPAC30_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 2. " OPAC31_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 1. " OPAC31_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 0. " OPAC31_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 30. " OPAC32_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 29. " OPAC32_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 28. " OPAC32_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x10 26. " OPAC33_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 25. " OPAC33_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 24. " OPAC33_TP ,Untrusted master" "Allowed,Not allowed" width 0x0B tree.end tree "AIPSTZ 2" base ad:0x305F0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Priviledge Registers" bitfld.long 0x00 31. " MPROT0_MBW ,Master 0 buffer control" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0_MTR ,Master 0 read control" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0_MTW ,Master 0 write control" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0_MPL ,Master 0 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1_MBW ,Master 1 buffer control" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1_MTR ,Master 1 read control" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1_MTW ,Master 1 write control" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1_MPL ,Master 1 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2_MBW ,Master 2 buffer control" "Disabled,Enabled" bitfld.long 0x00 22. " MPRO21_MTR ,Master 2 read control" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2_MTW ,Master 2 write control" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2_MPL ,Master 2 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3_MBW ,Master 3 buffer control" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3_MTR ,Master 3 read control" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3_MTW ,Master 3 write control" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3_MPL ,Master 3 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5_MBW ,Master 5 buffer control" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5_MTR ,Master 5 read control" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5_MTW ,Master 5 write control" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5_MPL ,Master 5 priviledge control" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x00 30. " OPAC0_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 29. " OPAC0_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 28. " OPAC0_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 26. " OPAC1_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 25. " OPAC1_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 24. " OPAC1_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 22. " OPAC2_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 21. " OPAC2_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 20. " OPAC2_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 18. " OPAC3_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 17. " OPAC3_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 16. " OPAC3_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 14. " OPAC4_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 13. " OPAC4_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 12. " OPAC4_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 10. " OPAC5_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 9. " OPAC5_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 8. " OPAC5_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 6. " OPAC6_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 5. " OPAC6_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 4. " OPAC6_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 2. " OPAC7_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 1. " OPAC7_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 0. " OPAC7_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Registers" bitfld.long 0x04 30. " OPAC8_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 29. " OPAC8_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 28. " OPAC8_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 26. " OPAC9_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 25. " OPAC9_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 24. " OPAC9_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 22. " OPAC10_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 21. " OPAC10_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 20. " OPAC10_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 18. " OPAC11_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 17. " OPAC11_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 16. " OPAC11_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 14. " OPAC12_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 13. " OPAC12_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 12. " OPAC12_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 10. " OPAC13_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 9. " OPAC13_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 8. " OPAC13_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 6. " OPAC14_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 5. " OPAC14_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 4. " OPAC14_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 2. " OPAC15_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 1. " OPAC15_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 0. " OPAC15_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Registers" bitfld.long 0x08 30. " OPAC16_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 29. " OPAC16_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 28. " OPAC16_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 26. " OPAC17_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 25. " OPAC17_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 24. " OPAC17_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 22. " OPAC18_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 21. " OPAC18_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 20. " OPAC18_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 18. " OPAC19_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 17. " OPAC19_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 16. " OPAC19_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 14. " OPAC20_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 13. " OPAC20_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 12. " OPAC20_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 10. " OPAC21_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 9. " OPAC21_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 8. " OPAC21_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 6. " OPAC22_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 5. " OPAC22_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 4. " OPAC22_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 2. " OPAC23_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 1. " OPAC23_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 0. " OPAC23_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0C 30. " OPAC24_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 29. " OPAC24_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 28. " OPAC24_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 26. " OPAC25_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 25. " OPAC25_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 24. " OPAC25_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 22. " OPAC26_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 21. " OPAC26_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 20. " OPAC26_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 18. " OPAC27_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 17. " OPAC27_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 16. " OPAC27_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 14. " OPAC28_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 13. " OPAC28_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 12. " OPAC28_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 10. " OPAC29_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 9. " OPAC29_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 8. " OPAC29_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 6. " OPAC30_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 5. " OPAC30_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 4. " OPAC30_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 2. " OPAC31_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 1. " OPAC31_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 0. " OPAC31_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 30. " OPAC32_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 29. " OPAC32_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 28. " OPAC32_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x10 26. " OPAC33_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 25. " OPAC33_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 24. " OPAC33_TP ,Untrusted master" "Allowed,Not allowed" width 0x0B tree.end tree "AIPSTZ 3" base ad:0x309F0000 width 8. group.long 0x00++0x03 line.long 0x00 "MPR,Master Priviledge Registers" bitfld.long 0x00 31. " MPROT0_MBW ,Master 0 buffer control" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0_MTR ,Master 0 read control" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0_MTW ,Master 0 write control" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0_MPL ,Master 0 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MPROT1_MBW ,Master 1 buffer control" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1_MTR ,Master 1 read control" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1_MTW ,Master 1 write control" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1_MPL ,Master 1 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MPROT2_MBW ,Master 2 buffer control" "Disabled,Enabled" bitfld.long 0x00 22. " MPRO21_MTR ,Master 2 read control" "Not trusted,Trusted" bitfld.long 0x00 21. " MPROT2_MTW ,Master 2 write control" "Not trusted,Trusted" bitfld.long 0x00 20. " MPROT2_MPL ,Master 2 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MPROT3_MBW ,Master 3 buffer control" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3_MTR ,Master 3 read control" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3_MTW ,Master 3 write control" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3_MPL ,Master 3 priviledge control" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MPROT5_MBW ,Master 5 buffer control" "Disabled,Enabled" bitfld.long 0x00 10. " MPROT5_MTR ,Master 5 read control" "Not trusted,Trusted" bitfld.long 0x00 9. " MPROT5_MTW ,Master 5 write control" "Not trusted,Trusted" bitfld.long 0x00 8. " MPROT5_MPL ,Master 5 priviledge control" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "OPACR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x00 30. " OPAC0_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 29. " OPAC0_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 28. " OPAC0_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 26. " OPAC1_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 25. " OPAC1_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 24. " OPAC1_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 22. " OPAC2_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 21. " OPAC2_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 20. " OPAC2_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 18. " OPAC3_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 17. " OPAC3_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 16. " OPAC3_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 14. " OPAC4_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 13. " OPAC4_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 12. " OPAC4_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 10. " OPAC5_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 9. " OPAC5_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 8. " OPAC5_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 6. " OPAC6_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 5. " OPAC6_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 4. " OPAC6_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x00 2. " OPAC7_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 1. " OPAC7_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 0. " OPAC7_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Registers" bitfld.long 0x04 30. " OPAC8_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 29. " OPAC8_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 28. " OPAC8_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 26. " OPAC9_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 25. " OPAC9_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 24. " OPAC9_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 22. " OPAC10_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 21. " OPAC10_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 20. " OPAC10_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 18. " OPAC11_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 17. " OPAC11_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 16. " OPAC11_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 14. " OPAC12_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 13. " OPAC12_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 12. " OPAC12_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 10. " OPAC13_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 9. " OPAC13_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 8. " OPAC13_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 6. " OPAC14_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 5. " OPAC14_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 4. " OPAC14_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x04 2. " OPAC15_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 1. " OPAC15_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 0. " OPAC15_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Registers" bitfld.long 0x08 30. " OPAC16_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 29. " OPAC16_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 28. " OPAC16_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 26. " OPAC17_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 25. " OPAC17_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 24. " OPAC17_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 22. " OPAC18_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 21. " OPAC18_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 20. " OPAC18_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 18. " OPAC19_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 17. " OPAC19_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 16. " OPAC19_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 14. " OPAC20_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 13. " OPAC20_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 12. " OPAC20_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 10. " OPAC21_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 9. " OPAC21_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 8. " OPAC21_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 6. " OPAC22_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 5. " OPAC22_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 4. " OPAC22_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x08 2. " OPAC23_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 1. " OPAC23_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 0. " OPAC23_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0C 30. " OPAC24_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 29. " OPAC24_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 28. " OPAC24_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 26. " OPAC25_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 25. " OPAC25_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 24. " OPAC25_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 22. " OPAC26_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 21. " OPAC26_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 20. " OPAC26_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 18. " OPAC27_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 17. " OPAC27_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 16. " OPAC27_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 14. " OPAC28_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 13. " OPAC28_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 12. " OPAC28_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 10. " OPAC29_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 9. " OPAC29_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 8. " OPAC29_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 6. " OPAC30_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 5. " OPAC30_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 4. " OPAC30_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x0C 2. " OPAC31_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 1. " OPAC31_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 0. " OPAC31_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 30. " OPAC32_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 29. " OPAC32_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 28. " OPAC32_TP ,Untrusted master" "Allowed,Not allowed" textline " " bitfld.long 0x10 26. " OPAC33_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 25. " OPAC33_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 24. " OPAC33_TP ,Untrusted master" "Allowed,Not allowed" width 0x0B tree.end tree.end tree "SPBA (Shared Peripheral Bus Arbiter)" base ad:0x308F0000 width 7. group.long 0x0++0x03 line.long 0x00 "PRR0,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x4++0x03 line.long 0x00 "PRR1,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x8++0x03 line.long 0x00 "PRR2,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0xC++0x03 line.long 0x00 "PRR3,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x10++0x03 line.long 0x00 "PRR4,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x14++0x03 line.long 0x00 "PRR5,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x18++0x03 line.long 0x00 "PRR6,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x1C++0x03 line.long 0x00 "PRR7,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x20++0x03 line.long 0x00 "PRR8,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x24++0x03 line.long 0x00 "PRR9,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x28++0x03 line.long 0x00 "PRR10,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x2C++0x03 line.long 0x00 "PRR11,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x30++0x03 line.long 0x00 "PRR12,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x34++0x03 line.long 0x00 "PRR13,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x38++0x03 line.long 0x00 "PRR14,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x3C++0x03 line.long 0x00 "PRR15,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x40++0x03 line.long 0x00 "PRR16,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x44++0x03 line.long 0x00 "PRR17,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x48++0x03 line.long 0x00 "PRR18,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x4C++0x03 line.long 0x00 "PRR19,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x50++0x03 line.long 0x00 "PRR20,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x54++0x03 line.long 0x00 "PRR21,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x58++0x03 line.long 0x00 "PRR22,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x5C++0x03 line.long 0x00 "PRR23,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x60++0x03 line.long 0x00 "PRR24,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x64++0x03 line.long 0x00 "PRR25,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x68++0x03 line.long 0x00 "PRR26,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x6C++0x03 line.long 0x00 "PRR27,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x70++0x03 line.long 0x00 "PRR28,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x74++0x03 line.long 0x00 "PRR29,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x78++0x03 line.long 0x00 "PRR30,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" group.long 0x7C++0x03 line.long 0x00 "PRR31,Peripheral Rights Register" rbitfld.long 0x00 30.--31. " RMO ,Requesting master owner" "Unowned,,Another master,Requesting master" rbitfld.long 0x00 16.--17. " ROI ,Resource owner ID" "Unowned,Master A port,Master B port,Master C port" bitfld.long 0x00 2. " RARC ,Resource access right control and status bit for master C" "Prohibited,Allowed" bitfld.long 0x00 1. " RARB ,Resource access right control and status bit for master B" "Prohibited,Allowed" bitfld.long 0x00 0. " RARA ,Resource access right control and status bit for master A" "Prohibited,Allowed" width 0x0B tree.end tree "ROMCP (ROM Controller with Patch)" base ad:0x30310000 width 14. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) group.long 0xD4++0x03 line.long 0x00 "ROMPATCH7D,Data Registers" group.long 0xD8++0x03 line.long 0x00 "ROMPATCH6D,Data Registers" group.long 0xDC++0x03 line.long 0x00 "ROMPATCH5D,Data Registers" group.long 0xE0++0x03 line.long 0x00 "ROMPATCH4D,Data Registers" group.long 0xE4++0x03 line.long 0x00 "ROMPATCH3D,Data Registers" group.long 0xE8++0x03 line.long 0x00 "ROMPATCH2D,Data Registers" group.long 0xEC++0x03 line.long 0x00 "ROMPATCH1D,Data Registers" group.long 0xF0++0x03 line.long 0x00 "ROMPATCH0D,Data Registers" else group.long 0xD4++0x03 line.long 0x00 "ROMPATCH0D,Data Registers" group.long 0xD8++0x03 line.long 0x00 "ROMPATCH1D,Data Registers" group.long 0xDC++0x03 line.long 0x00 "ROMPATCH2D,Data Registers" group.long 0xE0++0x03 line.long 0x00 "ROMPATCH3D,Data Registers" group.long 0xE4++0x03 line.long 0x00 "ROMPATCH4D,Data Registers" group.long 0xE8++0x03 line.long 0x00 "ROMPATCH5D,Data Registers" group.long 0xEC++0x03 line.long 0x00 "ROMPATCH6D,Data Registers" group.long 0xF0++0x03 line.long 0x00 "ROMPATCH7D,Data Registers" endif newline group.long 0xF4++0x03 line.long 0x00 "ROMPATCHCNTL,Control Register" bitfld.long 0x00 29. " DIS ,ROMC disable" "No,Yes" newline bitfld.long 0x00 7. " DATAFIX[7] ,Data fix enable 7" "Opcode patch,Data fix" bitfld.long 0x00 6. " [6] ,Data fix enable 6" "Opcode patch,Data fix" bitfld.long 0x00 5. " [5] ,Data fix enable 5" "Opcode patch,Data fix" bitfld.long 0x00 4. " [4] ,Data fix enable 4" "Opcode patch,Data fix" newline bitfld.long 0x00 3. " [3] ,Data fix enable 3" "Opcode patch,Data fix" bitfld.long 0x00 2. " [2] ,Data fix enable 2" "Opcode patch,Data fix" bitfld.long 0x00 1. " [1] ,Data fix enable 1" "Opcode patch,Data fix" bitfld.long 0x00 0. " [0] ,Data fix enable 0" "Opcode patch,Data fix" group.long 0xFC++0x03 line.long 0x00 "ROMPATCHENL,Enable Register Low" bitfld.long 0x00 15. " ENABLE[15] ,Enable address comparator 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable address comparator 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable address comparator 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable address comparator 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable address comparator 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable address comparator 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable address comparator 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable address comparator 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable address comparator 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable address comparator 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable address comparator 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable address comparator 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable address comparator 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable address comparator 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable address comparator 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable address comparator 0" "Disabled,Enabled" newline group.long 0x100++0x03 line.long 0x00 "ROMPATCH0A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x104++0x03 line.long 0x00 "ROMPATCH1A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x108++0x03 line.long 0x00 "ROMPATCH2A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x10C++0x03 line.long 0x00 "ROMPATCH3A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x110++0x03 line.long 0x00 "ROMPATCH4A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x114++0x03 line.long 0x00 "ROMPATCH5A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x118++0x03 line.long 0x00 "ROMPATCH6A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x11C++0x03 line.long 0x00 "ROMPATCH7A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x120++0x03 line.long 0x00 "ROMPATCH8A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x124++0x03 line.long 0x00 "ROMPATCH9A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x128++0x03 line.long 0x00 "ROMPATCH10A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x12C++0x03 line.long 0x00 "ROMPATCH11A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x130++0x03 line.long 0x00 "ROMPATCH12A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x134++0x03 line.long 0x00 "ROMPATCH13A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x138++0x03 line.long 0x00 "ROMPATCH14A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x13C++0x03 line.long 0x00 "ROMPATCH15A,Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" newline group.long 0x208++0x03 line.long 0x00 "ROMPATCHSR,Status Register" eventfld.long 0x00 17. " SW ,ROMC AHB multiple address comparator matches indicator" "No collision,Collision" newline rbitfld.long 0x00 0.--5. " SOURCE ,ROMC source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." width 0x0B tree.end tree.open "CCM (Clock Control Module)" tree "CCM" base ad:0x30380000 sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") width 10. group.long 0x00++0x0F line.long 0x00 "GPR0,General Purpose Register" line.long 0x04 "GPR0_SET,General Purpose Set Register" line.long 0x08 "GPR0_CLR,General Purpose Clear Register" line.long 0x0C "GPR0_TOG,General Purpose Toggle Register" width 16. tree "Input Clocks Registers" group.long 0x800++0x0F "PLL Control 0" line.long 0x00 "PLL_CTRL0,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL0_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL0_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL0_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x810++0x0F "PLL Control 1" line.long 0x00 "PLL_CTRL1,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL1_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL1_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL1_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x820++0x0F "PLL Control 2" line.long 0x00 "PLL_CTRL2,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL2_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL2_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL2_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x830++0x0F "PLL Control 3" line.long 0x00 "PLL_CTRL3,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL3_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL3_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL3_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x840++0x0F "PLL Control 4" line.long 0x00 "PLL_CTRL4,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL4_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL4_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL4_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x850++0x0F "PLL Control 5" line.long 0x00 "PLL_CTRL5,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL5_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL5_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL5_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x860++0x0F "PLL Control 6" line.long 0x00 "PLL_CTRL6,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL6_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL6_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL6_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x870++0x0F "PLL Control 7" line.long 0x00 "PLL_CTRL7,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL7_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL7_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL7_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x880++0x0F "PLL Control 8" line.long 0x00 "PLL_CTRL8,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL8_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL8_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL8_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x890++0x0F "PLL Control 9" line.long 0x00 "PLL_CTRL9,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL9_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL9_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL9_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8A0++0x0F "PLL Control 10" line.long 0x00 "PLL_CTRL10,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL10_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL10_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL10_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8B0++0x0F "PLL Control 11" line.long 0x00 "PLL_CTRL11,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL11_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL11_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL11_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8C0++0x0F "PLL Control 12" line.long 0x00 "PLL_CTRL12,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL12_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL12_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL12_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8D0++0x0F "PLL Control 13" line.long 0x00 "PLL_CTRL13,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL13_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL13_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL13_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8E0++0x0F "PLL Control 14" line.long 0x00 "PLL_CTRL14,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL14_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL14_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL14_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8F0++0x0F "PLL Control 15" line.long 0x00 "PLL_CTRL15,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL15_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL15_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL15_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x900++0x0F "PLL Control 16" line.long 0x00 "PLL_CTRL16,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL16_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL16_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL16_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x910++0x0F "PLL Control 17" line.long 0x00 "PLL_CTRL17,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL17_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL17_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL17_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x920++0x0F "PLL Control 18" line.long 0x00 "PLL_CTRL18,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL18_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL18_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL18_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x930++0x0F "PLL Control 19" line.long 0x00 "PLL_CTRL19,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL19_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL19_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL19_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x940++0x0F "PLL Control 20" line.long 0x00 "PLL_CTRL20,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL20_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL20_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL20_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x950++0x0F "PLL Control 21" line.long 0x00 "PLL_CTRL21,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL21_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL21_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL21_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x960++0x0F "PLL Control 22" line.long 0x00 "PLL_CTRL22,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL22_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL22_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL22_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x970++0x0F "PLL Control 23" line.long 0x00 "PLL_CTRL23,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL23_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL23_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL23_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x980++0x0F "PLL Control 24" line.long 0x00 "PLL_CTRL24,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL24_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL24_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL24_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x990++0x0F "PLL Control 25" line.long 0x00 "PLL_CTRL25,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL25_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL25_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL25_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9A0++0x0F "PLL Control 26" line.long 0x00 "PLL_CTRL26,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL26_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL26_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL26_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9B0++0x0F "PLL Control 27" line.long 0x00 "PLL_CTRL27,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL27_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL27_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL27_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9C0++0x0F "PLL Control 28" line.long 0x00 "PLL_CTRL28,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL28_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL28_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL28_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9D0++0x0F "PLL Control 29" line.long 0x00 "PLL_CTRL29,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL29_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL29_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL29_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9E0++0x0F "PLL Control 30" line.long 0x00 "PLL_CTRL30,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL30_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL30_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL30_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9F0++0x0F "PLL Control 31" line.long 0x00 "PLL_CTRL31,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL31_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL31_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL31_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0xA00++0x0F "PLL Control 32" line.long 0x00 "PLL_CTRL32,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL32_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL32_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL32_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" tree.end width 13. tree "Clock Gating Interface Registers" group.long 0x4000++0x0F "Clock Gating 0" line.long 0x00 "CCGR0,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR0_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR0_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR0_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4010++0x0F "Clock Gating 1" line.long 0x00 "CCGR1,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR1_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR1_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR1_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4020++0x0F "Clock Gating 2" line.long 0x00 "CCGR2,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR2_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR2_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR2_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4030++0x0F "Clock Gating 3" line.long 0x00 "CCGR3,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR3_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR3_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR3_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4040++0x0F "Clock Gating 4" line.long 0x00 "CCGR4,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR4_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR4_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR4_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4050++0x0F "Clock Gating 5" line.long 0x00 "CCGR5,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR5_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR5_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR5_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4060++0x0F "Clock Gating 6" line.long 0x00 "CCGR6,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR6_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR6_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR6_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4070++0x0F "Clock Gating 7" line.long 0x00 "CCGR7,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR7_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR7_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR7_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4080++0x0F "Clock Gating 8" line.long 0x00 "CCGR8,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR8_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR8_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR8_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4090++0x0F "Clock Gating 9" line.long 0x00 "CCGR9,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR9_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR9_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR9_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40A0++0x0F "Clock Gating 10" line.long 0x00 "CCGR10,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR10_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR10_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR10_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40B0++0x0F "Clock Gating 11" line.long 0x00 "CCGR11,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR11_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR11_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR11_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40C0++0x0F "Clock Gating 12" line.long 0x00 "CCGR12,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR12_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR12_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR12_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40D0++0x0F "Clock Gating 13" line.long 0x00 "CCGR13,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR13_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR13_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR13_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40E0++0x0F "Clock Gating 14" line.long 0x00 "CCGR14,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR14_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR14_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR14_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40F0++0x0F "Clock Gating 15" line.long 0x00 "CCGR15,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR15_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR15_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR15_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4100++0x0F "Clock Gating 16" line.long 0x00 "CCGR16,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR16_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR16_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR16_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4110++0x0F "Clock Gating 17" line.long 0x00 "CCGR17,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR17_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR17_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR17_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4120++0x0F "Clock Gating 18" line.long 0x00 "CCGR18,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR18_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR18_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR18_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4130++0x0F "Clock Gating 19" line.long 0x00 "CCGR19,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR19_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR19_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR19_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4140++0x0F "Clock Gating 20" line.long 0x00 "CCGR20,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR20_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR20_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR20_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4150++0x0F "Clock Gating 21" line.long 0x00 "CCGR21,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR21_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR21_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR21_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4160++0x0F "Clock Gating 22" line.long 0x00 "CCGR22,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR22_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR22_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR22_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4170++0x0F "Clock Gating 23" line.long 0x00 "CCGR23,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR23_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR23_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR23_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4180++0x0F "Clock Gating 24" line.long 0x00 "CCGR24,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR24_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR24_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR24_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4190++0x0F "Clock Gating 25" line.long 0x00 "CCGR25,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR25_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR25_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR25_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41A0++0x0F "Clock Gating 26" line.long 0x00 "CCGR26,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR26_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR26_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR26_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41B0++0x0F "Clock Gating 27" line.long 0x00 "CCGR27,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR27_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR27_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR27_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41C0++0x0F "Clock Gating 28" line.long 0x00 "CCGR28,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR28_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR28_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR28_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41D0++0x0F "Clock Gating 29" line.long 0x00 "CCGR29,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR29_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR29_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR29_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41E0++0x0F "Clock Gating 30" line.long 0x00 "CCGR30,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR30_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR30_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR30_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41F0++0x0F "Clock Gating 31" line.long 0x00 "CCGR31,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR31_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR31_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR31_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4200++0x0F "Clock Gating 32" line.long 0x00 "CCGR32,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR32_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR32_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR32_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4210++0x0F "Clock Gating 33" line.long 0x00 "CCGR33,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR33_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR33_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR33_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4220++0x0F "Clock Gating 34" line.long 0x00 "CCGR34,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR34_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR34_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR34_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4230++0x0F "Clock Gating 35" line.long 0x00 "CCGR35,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR35_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR35_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR35_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4240++0x0F "Clock Gating 36" line.long 0x00 "CCGR36,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR36_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR36_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR36_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4250++0x0F "Clock Gating 37" line.long 0x00 "CCGR37,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR37_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR37_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR37_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4260++0x0F "Clock Gating 38" line.long 0x00 "CCGR38,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR38_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR38_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR38_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4270++0x0F "Clock Gating 39" line.long 0x00 "CCGR39,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR39_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR39_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR39_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4280++0x0F "Clock Gating 40" line.long 0x00 "CCGR40,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR40_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR40_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR40_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4290++0x0F "Clock Gating 41" line.long 0x00 "CCGR41,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR41_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR41_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR41_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42A0++0x0F "Clock Gating 42" line.long 0x00 "CCGR42,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR42_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR42_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR42_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42B0++0x0F "Clock Gating 43" line.long 0x00 "CCGR43,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR43_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR43_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR43_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42C0++0x0F "Clock Gating 44" line.long 0x00 "CCGR44,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR44_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR44_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR44_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42D0++0x0F "Clock Gating 45" line.long 0x00 "CCGR45,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR45_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR45_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR45_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42E0++0x0F "Clock Gating 46" line.long 0x00 "CCGR46,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR46_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR46_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR46_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42F0++0x0F "Clock Gating 47" line.long 0x00 "CCGR47,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR47_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR47_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR47_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4300++0x0F "Clock Gating 48" line.long 0x00 "CCGR48,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR48_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR48_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR48_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4310++0x0F "Clock Gating 49" line.long 0x00 "CCGR49,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR49_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR49_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR49_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4320++0x0F "Clock Gating 50" line.long 0x00 "CCGR50,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR50_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR50_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR50_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4330++0x0F "Clock Gating 51" line.long 0x00 "CCGR51,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR51_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR51_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR51_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4340++0x0F "Clock Gating 52" line.long 0x00 "CCGR52,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR52_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR52_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR52_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4350++0x0F "Clock Gating 53" line.long 0x00 "CCGR53,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR53_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR53_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR53_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4360++0x0F "Clock Gating 54" line.long 0x00 "CCGR54,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR54_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR54_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR54_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4370++0x0F "Clock Gating 55" line.long 0x00 "CCGR55,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR55_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR55_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR55_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4380++0x0F "Clock Gating 56" line.long 0x00 "CCGR56,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR56_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR56_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR56_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4390++0x0F "Clock Gating 57" line.long 0x00 "CCGR57,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR57_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR57_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR57_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43A0++0x0F "Clock Gating 58" line.long 0x00 "CCGR58,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR58_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR58_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR58_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43B0++0x0F "Clock Gating 59" line.long 0x00 "CCGR59,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR59_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR59_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR59_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43C0++0x0F "Clock Gating 60" line.long 0x00 "CCGR60,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR60_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR60_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR60_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43D0++0x0F "Clock Gating 61" line.long 0x00 "CCGR61,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR61_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR61_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR61_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43E0++0x0F "Clock Gating 62" line.long 0x00 "CCGR62,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR62_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR62_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR62_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43F0++0x0F "Clock Gating 63" line.long 0x00 "CCGR63,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR63_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR63_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR63_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4400++0x0F "Clock Gating 64" line.long 0x00 "CCGR64,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR64_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR64_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR64_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4410++0x0F "Clock Gating 65" line.long 0x00 "CCGR65,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR65_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR65_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR65_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4420++0x0F "Clock Gating 66" line.long 0x00 "CCGR66,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR66_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR66_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR66_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4430++0x0F "Clock Gating 67" line.long 0x00 "CCGR67,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR67_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR67_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR67_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4440++0x0F "Clock Gating 68" line.long 0x00 "CCGR68,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR68_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR68_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR68_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4450++0x0F "Clock Gating 69" line.long 0x00 "CCGR69,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR69_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR69_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR69_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4460++0x0F "Clock Gating 70" line.long 0x00 "CCGR70,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR70_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR70_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR70_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4470++0x0F "Clock Gating 71" line.long 0x00 "CCGR71,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR71_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR71_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR71_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4480++0x0F "Clock Gating 72" line.long 0x00 "CCGR72,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR72_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR72_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR72_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4490++0x0F "Clock Gating 73" line.long 0x00 "CCGR73,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR73_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR73_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR73_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44A0++0x0F "Clock Gating 74" line.long 0x00 "CCGR74,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR74_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR74_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR74_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44B0++0x0F "Clock Gating 75" line.long 0x00 "CCGR75,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR75_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR75_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR75_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44C0++0x0F "Clock Gating 76" line.long 0x00 "CCGR76,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR76_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR76_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR76_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44D0++0x0F "Clock Gating 77" line.long 0x00 "CCGR77,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR77_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR77_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR77_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44E0++0x0F "Clock Gating 78" line.long 0x00 "CCGR78,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR78_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR78_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR78_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44F0++0x0F "Clock Gating 79" line.long 0x00 "CCGR79,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR79_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR79_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR79_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4500++0x0F "Clock Gating 80" line.long 0x00 "CCGR80,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR80_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR80_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR80_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4510++0x0F "Clock Gating 81" line.long 0x00 "CCGR81,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR81_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR81_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR81_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4520++0x0F "Clock Gating 82" line.long 0x00 "CCGR82,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR82_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR82_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR82_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4530++0x0F "Clock Gating 83" line.long 0x00 "CCGR83,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR83_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR83_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR83_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4540++0x0F "Clock Gating 84" line.long 0x00 "CCGR84,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR84_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR84_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR84_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4550++0x0F "Clock Gating 85" line.long 0x00 "CCGR85,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR85_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR85_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR85_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4560++0x0F "Clock Gating 86" line.long 0x00 "CCGR86,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR86_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR86_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR86_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4570++0x0F "Clock Gating 87" line.long 0x00 "CCGR87,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR87_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR87_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR87_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4580++0x0F "Clock Gating 88" line.long 0x00 "CCGR88,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR88_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR88_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR88_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4590++0x0F "Clock Gating 89" line.long 0x00 "CCGR89,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR89_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR89_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR89_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45A0++0x0F "Clock Gating 90" line.long 0x00 "CCGR90,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR90_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR90_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR90_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45B0++0x0F "Clock Gating 91" line.long 0x00 "CCGR91,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR91_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR91_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR91_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45C0++0x0F "Clock Gating 92" line.long 0x00 "CCGR92,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR92_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR92_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR92_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45D0++0x0F "Clock Gating 93" line.long 0x00 "CCGR93,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR93_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR93_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR93_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45E0++0x0F "Clock Gating 94" line.long 0x00 "CCGR94,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR94_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR94_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR94_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45F0++0x0F "Clock Gating 95" line.long 0x00 "CCGR95,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR95_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR95_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR95_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4600++0x0F "Clock Gating 96" line.long 0x00 "CCGR96,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR96_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR96_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR96_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4610++0x0F "Clock Gating 97" line.long 0x00 "CCGR97,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR97_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR97_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR97_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4620++0x0F "Clock Gating 98" line.long 0x00 "CCGR98,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR98_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR98_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR98_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4630++0x0F "Clock Gating 99" line.long 0x00 "CCGR99,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR99_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR99_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR99_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4640++0x0F "Clock Gating 100" line.long 0x00 "CCGR100,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR100_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR100_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR100_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4650++0x0F "Clock Gating 101" line.long 0x00 "CCGR101,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR101_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR101_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR101_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4660++0x0F "Clock Gating 102" line.long 0x00 "CCGR102,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR102_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR102_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR102_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4670++0x0F "Clock Gating 103" line.long 0x00 "CCGR103,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR103_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR103_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR103_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4680++0x0F "Clock Gating 104" line.long 0x00 "CCGR104,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR104_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR104_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR104_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4690++0x0F "Clock Gating 105" line.long 0x00 "CCGR105,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR105_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR105_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR105_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46A0++0x0F "Clock Gating 106" line.long 0x00 "CCGR106,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR106_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR106_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR106_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46B0++0x0F "Clock Gating 107" line.long 0x00 "CCGR107,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR107_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR107_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR107_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46C0++0x0F "Clock Gating 108" line.long 0x00 "CCGR108,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR108_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR108_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR108_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46D0++0x0F "Clock Gating 109" line.long 0x00 "CCGR109,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR109_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR109_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR109_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46E0++0x0F "Clock Gating 110" line.long 0x00 "CCGR110,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR110_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR110_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR110_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46F0++0x0F "Clock Gating 111" line.long 0x00 "CCGR111,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR111_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR111_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR111_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4700++0x0F "Clock Gating 112" line.long 0x00 "CCGR112,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR112_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR112_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR112_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4710++0x0F "Clock Gating 113" line.long 0x00 "CCGR113,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR113_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR113_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR113_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4720++0x0F "Clock Gating 114" line.long 0x00 "CCGR114,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR114_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR114_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR114_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4730++0x0F "Clock Gating 115" line.long 0x00 "CCGR115,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR115_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR115_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR115_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4740++0x0F "Clock Gating 116" line.long 0x00 "CCGR116,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR116_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR116_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR116_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4750++0x0F "Clock Gating 117" line.long 0x00 "CCGR117,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR117_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR117_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR117_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4760++0x0F "Clock Gating 118" line.long 0x00 "CCGR118,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR118_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR118_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR118_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4770++0x0F "Clock Gating 119" line.long 0x00 "CCGR119,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR119_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR119_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR119_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4780++0x0F "Clock Gating 120" line.long 0x00 "CCGR120,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR120_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR120_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR120_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4790++0x0F "Clock Gating 121" line.long 0x00 "CCGR121,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR121_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR121_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR121_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47A0++0x0F "Clock Gating 122" line.long 0x00 "CCGR122,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR122_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR122_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR122_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47B0++0x0F "Clock Gating 123" line.long 0x00 "CCGR123,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR123_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR123_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR123_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47C0++0x0F "Clock Gating 124" line.long 0x00 "CCGR124,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR124_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR124_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR124_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47D0++0x0F "Clock Gating 125" line.long 0x00 "CCGR125,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR125_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR125_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR125_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47E0++0x0F "Clock Gating 126" line.long 0x00 "CCGR126,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR126_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR126_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR126_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47F0++0x0F "Clock Gating 127" line.long 0x00 "CCGR127,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR127_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR127_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR127_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4800++0x0F "Clock Gating 128" line.long 0x00 "CCGR128,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR128_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR128_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR128_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4810++0x0F "Clock Gating 129" line.long 0x00 "CCGR129,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR129_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR129_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR129_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4820++0x0F "Clock Gating 130" line.long 0x00 "CCGR130,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR130_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR130_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR130_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4830++0x0F "Clock Gating 131" line.long 0x00 "CCGR131,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR131_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR131_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR131_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4840++0x0F "Clock Gating 132" line.long 0x00 "CCGR132,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR132_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR132_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR132_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4850++0x0F "Clock Gating 133" line.long 0x00 "CCGR133,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR133_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR133_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR133_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4860++0x0F "Clock Gating 134" line.long 0x00 "CCGR134,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR134_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR134_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR134_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4870++0x0F "Clock Gating 135" line.long 0x00 "CCGR135,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR135_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR135_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR135_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4880++0x0F "Clock Gating 136" line.long 0x00 "CCGR136,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR136_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR136_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR136_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4890++0x0F "Clock Gating 137" line.long 0x00 "CCGR137,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR137_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR137_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR137_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48A0++0x0F "Clock Gating 138" line.long 0x00 "CCGR138,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR138_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR138_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR138_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48B0++0x0F "Clock Gating 139" line.long 0x00 "CCGR139,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR139_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR139_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR139_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48C0++0x0F "Clock Gating 140" line.long 0x00 "CCGR140,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR140_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR140_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR140_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48D0++0x0F "Clock Gating 141" line.long 0x00 "CCGR141,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR141_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR141_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR141_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48E0++0x0F "Clock Gating 142" line.long 0x00 "CCGR142,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR142_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR142_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR142_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48F0++0x0F "Clock Gating 143" line.long 0x00 "CCGR143,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR143_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR143_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR143_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4900++0x0F "Clock Gating 144" line.long 0x00 "CCGR144,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR144_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR144_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR144_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4910++0x0F "Clock Gating 145" line.long 0x00 "CCGR145,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR145_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR145_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR145_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4920++0x0F "Clock Gating 146" line.long 0x00 "CCGR146,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR146_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR146_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR146_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4930++0x0F "Clock Gating 147" line.long 0x00 "CCGR147,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR147_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR147_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR147_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4940++0x0F "Clock Gating 148" line.long 0x00 "CCGR148,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR148_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR148_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR148_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4950++0x0F "Clock Gating 149" line.long 0x00 "CCGR149,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR149_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR149_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR149_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4960++0x0F "Clock Gating 150" line.long 0x00 "CCGR150,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR150_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR150_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR150_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4970++0x0F "Clock Gating 151" line.long 0x00 "CCGR151,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR151_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR151_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR151_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4980++0x0F "Clock Gating 152" line.long 0x00 "CCGR152,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR152_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR152_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR152_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4990++0x0F "Clock Gating 153" line.long 0x00 "CCGR153,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR153_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR153_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR153_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49A0++0x0F "Clock Gating 154" line.long 0x00 "CCGR154,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR154_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR154_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR154_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49B0++0x0F "Clock Gating 155" line.long 0x00 "CCGR155,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR155_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR155_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR155_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49C0++0x0F "Clock Gating 156" line.long 0x00 "CCGR156,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR156_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR156_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR156_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49D0++0x0F "Clock Gating 157" line.long 0x00 "CCGR157,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR157_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR157_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR157_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49E0++0x0F "Clock Gating 158" line.long 0x00 "CCGR158,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR158_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR158_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR158_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49F0++0x0F "Clock Gating 159" line.long 0x00 "CCGR159,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR159_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR159_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR159_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A00++0x0F "Clock Gating 160" line.long 0x00 "CCGR160,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR160_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR160_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR160_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A10++0x0F "Clock Gating 161" line.long 0x00 "CCGR161,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR161_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR161_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR161_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A20++0x0F "Clock Gating 162" line.long 0x00 "CCGR162,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR162_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR162_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR162_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A30++0x0F "Clock Gating 163" line.long 0x00 "CCGR163,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR163_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR163_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR163_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A40++0x0F "Clock Gating 164" line.long 0x00 "CCGR164,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR164_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR164_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR164_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A50++0x0F "Clock Gating 165" line.long 0x00 "CCGR165,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR165_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR165_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR165_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A60++0x0F "Clock Gating 166" line.long 0x00 "CCGR166,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR166_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR166_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR166_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A70++0x0F "Clock Gating 167" line.long 0x00 "CCGR167,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR167_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR167_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR167_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A80++0x0F "Clock Gating 168" line.long 0x00 "CCGR168,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR168_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR168_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR168_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A90++0x0F "Clock Gating 169" line.long 0x00 "CCGR169,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR169_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR169_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR169_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AA0++0x0F "Clock Gating 170" line.long 0x00 "CCGR170,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR170_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR170_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR170_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AB0++0x0F "Clock Gating 171" line.long 0x00 "CCGR171,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR171_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR171_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR171_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AC0++0x0F "Clock Gating 172" line.long 0x00 "CCGR172,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR172_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR172_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR172_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AD0++0x0F "Clock Gating 173" line.long 0x00 "CCGR173,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR173_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR173_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR173_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AE0++0x0F "Clock Gating 174" line.long 0x00 "CCGR174,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR174_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR174_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR174_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AF0++0x0F "Clock Gating 175" line.long 0x00 "CCGR175,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR175_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR175_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR175_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B00++0x0F "Clock Gating 176" line.long 0x00 "CCGR176,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR176_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR176_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR176_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B10++0x0F "Clock Gating 177" line.long 0x00 "CCGR177,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR177_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR177_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR177_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B20++0x0F "Clock Gating 178" line.long 0x00 "CCGR178,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR178_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR178_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR178_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B30++0x0F "Clock Gating 179" line.long 0x00 "CCGR179,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR179_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR179_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR179_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B40++0x0F "Clock Gating 180" line.long 0x00 "CCGR180,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR180_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR180_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR180_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B50++0x0F "Clock Gating 181" line.long 0x00 "CCGR181,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR181_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR181_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR181_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B60++0x0F "Clock Gating 182" line.long 0x00 "CCGR182,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR182_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR182_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR182_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B70++0x0F "Clock Gating 183" line.long 0x00 "CCGR183,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR183_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR183_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR183_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B80++0x0F "Clock Gating 184" line.long 0x00 "CCGR184,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR184_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR184_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR184_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B90++0x0F "Clock Gating 185" line.long 0x00 "CCGR185,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR185_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR185_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR185_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BA0++0x0F "Clock Gating 186" line.long 0x00 "CCGR186,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR186_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR186_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR186_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BB0++0x0F "Clock Gating 187" line.long 0x00 "CCGR187,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR187_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR187_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR187_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BC0++0x0F "Clock Gating 188" line.long 0x00 "CCGR188,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR188_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR188_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR188_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BD0++0x0F "Clock Gating 189" line.long 0x00 "CCGR189,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR189_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR189_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR189_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BE0++0x0F "Clock Gating 190" line.long 0x00 "CCGR190,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR190_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR190_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR190_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" tree.end width 25. tree "Clock Root Registers" tree "Clock Root 0" group.long 0x8000++0x0F line.long 0x00 "TARGET_ROOT0,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT0_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT0_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT0_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8000+0x10)++0x0F line.long 0x00 "MISC0,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT0_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT0_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT0_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8000+0x20)++0x0F line.long 0x00 "POST0,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT0_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT0_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT0_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8000+0x30)++0x0F line.long 0x00 "PRE0,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT0_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT0_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT0_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL0,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT0_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT0_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT0_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 1" group.long 0x8080++0x0F line.long 0x00 "TARGET_ROOT1,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT1_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT1_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT1_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8080+0x10)++0x0F line.long 0x00 "MISC1,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT1_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT1_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT1_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8080+0x20)++0x0F line.long 0x00 "POST1,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT1_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT1_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT1_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8080+0x30)++0x0F line.long 0x00 "PRE1,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT1_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT1_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT1_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL1,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT1_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT1_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT1_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 2" group.long 0x8100++0x0F line.long 0x00 "TARGET_ROOT2,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT2_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT2_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT2_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8100+0x10)++0x0F line.long 0x00 "MISC2,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT2_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT2_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT2_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8100+0x20)++0x0F line.long 0x00 "POST2,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT2_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT2_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT2_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8100+0x30)++0x0F line.long 0x00 "PRE2,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT2_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT2_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT2_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL2,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT2_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT2_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT2_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 3" group.long 0x8180++0x0F line.long 0x00 "TARGET_ROOT3,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT3_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT3_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT3_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8180+0x10)++0x0F line.long 0x00 "MISC3,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT3_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT3_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT3_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8180+0x20)++0x0F line.long 0x00 "POST3,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT3_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT3_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT3_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8180+0x30)++0x0F line.long 0x00 "PRE3,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT3_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT3_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT3_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL3,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT3_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT3_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT3_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 4" group.long 0x8200++0x0F line.long 0x00 "TARGET_ROOT4,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT4_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT4_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT4_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8200+0x10)++0x0F line.long 0x00 "MISC4,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT4_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT4_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT4_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8200+0x20)++0x0F line.long 0x00 "POST4,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT4_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT4_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT4_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8200+0x30)++0x0F line.long 0x00 "PRE4,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT4_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT4_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT4_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL4,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT4_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT4_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT4_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 5" group.long 0x8280++0x0F line.long 0x00 "TARGET_ROOT5,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT5_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT5_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT5_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8280+0x10)++0x0F line.long 0x00 "MISC5,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT5_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT5_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT5_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8280+0x20)++0x0F line.long 0x00 "POST5,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT5_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT5_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT5_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8280+0x30)++0x0F line.long 0x00 "PRE5,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT5_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT5_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT5_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL5,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT5_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT5_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT5_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 6" group.long 0x8300++0x0F line.long 0x00 "TARGET_ROOT6,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT6_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT6_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT6_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8300+0x10)++0x0F line.long 0x00 "MISC6,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT6_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT6_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT6_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8300+0x20)++0x0F line.long 0x00 "POST6,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT6_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT6_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT6_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8300+0x30)++0x0F line.long 0x00 "PRE6,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT6_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT6_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT6_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL6,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT6_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT6_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT6_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 7" group.long 0x8380++0x0F line.long 0x00 "TARGET_ROOT7,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT7_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT7_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT7_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8380+0x10)++0x0F line.long 0x00 "MISC7,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT7_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT7_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT7_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8380+0x20)++0x0F line.long 0x00 "POST7,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT7_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT7_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT7_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8380+0x30)++0x0F line.long 0x00 "PRE7,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT7_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT7_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT7_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL7,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT7_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT7_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT7_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 8" group.long 0x8400++0x0F line.long 0x00 "TARGET_ROOT8,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT8_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT8_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT8_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8400+0x10)++0x0F line.long 0x00 "MISC8,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT8_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT8_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT8_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8400+0x20)++0x0F line.long 0x00 "POST8,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT8_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT8_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT8_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8400+0x30)++0x0F line.long 0x00 "PRE8,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT8_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT8_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT8_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL8,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT8_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT8_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT8_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 9" group.long 0x8480++0x0F line.long 0x00 "TARGET_ROOT9,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT9_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT9_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT9_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8480+0x10)++0x0F line.long 0x00 "MISC9,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT9_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT9_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT9_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8480+0x20)++0x0F line.long 0x00 "POST9,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT9_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT9_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT9_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8480+0x30)++0x0F line.long 0x00 "PRE9,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT9_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT9_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT9_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL9,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT9_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT9_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT9_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 10" group.long 0x8500++0x0F line.long 0x00 "TARGET_ROOT10,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT10_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT10_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT10_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8500+0x10)++0x0F line.long 0x00 "MISC10,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT10_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT10_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT10_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8500+0x20)++0x0F line.long 0x00 "POST10,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT10_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT10_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT10_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8500+0x30)++0x0F line.long 0x00 "PRE10,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT10_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT10_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT10_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL10,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT10_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT10_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT10_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 11" group.long 0x8580++0x0F line.long 0x00 "TARGET_ROOT11,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT11_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT11_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT11_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8580+0x10)++0x0F line.long 0x00 "MISC11,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT11_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT11_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT11_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8580+0x20)++0x0F line.long 0x00 "POST11,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT11_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT11_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT11_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8580+0x30)++0x0F line.long 0x00 "PRE11,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT11_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT11_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT11_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL11,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT11_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT11_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT11_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 12" group.long 0x8600++0x0F line.long 0x00 "TARGET_ROOT12,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT12_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT12_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT12_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8600+0x10)++0x0F line.long 0x00 "MISC12,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT12_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT12_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT12_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8600+0x20)++0x0F line.long 0x00 "POST12,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT12_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT12_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT12_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8600+0x30)++0x0F line.long 0x00 "PRE12,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT12_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT12_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT12_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL12,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT12_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT12_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT12_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 13" group.long 0x8680++0x0F line.long 0x00 "TARGET_ROOT13,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT13_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT13_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT13_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8680+0x10)++0x0F line.long 0x00 "MISC13,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT13_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT13_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT13_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8680+0x20)++0x0F line.long 0x00 "POST13,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT13_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT13_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT13_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8680+0x30)++0x0F line.long 0x00 "PRE13,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT13_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT13_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT13_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL13,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT13_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT13_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT13_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 14" group.long 0x8700++0x0F line.long 0x00 "TARGET_ROOT14,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT14_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT14_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT14_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8700+0x10)++0x0F line.long 0x00 "MISC14,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT14_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT14_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT14_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8700+0x20)++0x0F line.long 0x00 "POST14,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT14_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT14_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT14_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8700+0x30)++0x0F line.long 0x00 "PRE14,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT14_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT14_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT14_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL14,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT14_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT14_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT14_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 15" group.long 0x8780++0x0F line.long 0x00 "TARGET_ROOT15,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT15_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT15_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT15_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8780+0x10)++0x0F line.long 0x00 "MISC15,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT15_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT15_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT15_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8780+0x20)++0x0F line.long 0x00 "POST15,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT15_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT15_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT15_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8780+0x30)++0x0F line.long 0x00 "PRE15,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT15_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT15_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT15_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL15,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT15_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT15_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT15_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 16" group.long 0x8800++0x0F line.long 0x00 "TARGET_ROOT16,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT16_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT16_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT16_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8800+0x10)++0x0F line.long 0x00 "MISC16,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT16_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT16_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT16_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8800+0x20)++0x0F line.long 0x00 "POST16,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT16_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT16_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT16_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8800+0x30)++0x0F line.long 0x00 "PRE16,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT16_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT16_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT16_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL16,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT16_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT16_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT16_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 17" group.long 0x8880++0x0F line.long 0x00 "TARGET_ROOT17,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT17_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT17_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT17_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8880+0x10)++0x0F line.long 0x00 "MISC17,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT17_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT17_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT17_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8880+0x20)++0x0F line.long 0x00 "POST17,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT17_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT17_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT17_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8880+0x30)++0x0F line.long 0x00 "PRE17,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT17_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT17_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT17_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL17,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT17_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT17_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT17_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 18" group.long 0x8900++0x0F line.long 0x00 "TARGET_ROOT18,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT18_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT18_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT18_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8900+0x10)++0x0F line.long 0x00 "MISC18,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT18_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT18_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT18_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8900+0x20)++0x0F line.long 0x00 "POST18,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT18_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT18_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT18_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8900+0x30)++0x0F line.long 0x00 "PRE18,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT18_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT18_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT18_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL18,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT18_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT18_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT18_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 19" group.long 0x8980++0x0F line.long 0x00 "TARGET_ROOT19,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT19_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT19_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT19_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8980+0x10)++0x0F line.long 0x00 "MISC19,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT19_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT19_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT19_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8980+0x20)++0x0F line.long 0x00 "POST19,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT19_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT19_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT19_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8980+0x30)++0x0F line.long 0x00 "PRE19,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT19_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT19_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT19_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL19,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT19_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT19_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT19_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 20" group.long 0x8A00++0x0F line.long 0x00 "TARGET_ROOT20,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT20_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT20_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT20_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A00+0x10)++0x0F line.long 0x00 "MISC20,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT20_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT20_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT20_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8A00+0x20)++0x0F line.long 0x00 "POST20,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT20_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT20_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT20_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A00+0x30)++0x0F line.long 0x00 "PRE20,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT20_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT20_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT20_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8A00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL20,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT20_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT20_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT20_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 21" group.long 0x8A80++0x0F line.long 0x00 "TARGET_ROOT21,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT21_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT21_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT21_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A80+0x10)++0x0F line.long 0x00 "MISC21,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT21_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT21_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT21_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8A80+0x20)++0x0F line.long 0x00 "POST21,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT21_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT21_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT21_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A80+0x30)++0x0F line.long 0x00 "PRE21,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT21_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT21_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT21_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8A80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL21,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT21_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT21_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT21_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 22" group.long 0x8B00++0x0F line.long 0x00 "TARGET_ROOT22,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT22_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT22_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT22_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B00+0x10)++0x0F line.long 0x00 "MISC22,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT22_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT22_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT22_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8B00+0x20)++0x0F line.long 0x00 "POST22,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT22_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT22_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT22_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B00+0x30)++0x0F line.long 0x00 "PRE22,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT22_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT22_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT22_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8B00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL22,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT22_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT22_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT22_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 23" group.long 0x8B80++0x0F line.long 0x00 "TARGET_ROOT23,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT23_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT23_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT23_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B80+0x10)++0x0F line.long 0x00 "MISC23,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT23_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT23_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT23_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8B80+0x20)++0x0F line.long 0x00 "POST23,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT23_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT23_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT23_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B80+0x30)++0x0F line.long 0x00 "PRE23,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT23_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT23_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT23_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8B80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL23,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT23_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT23_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT23_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 24" group.long 0x8C00++0x0F line.long 0x00 "TARGET_ROOT24,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT24_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT24_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT24_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C00+0x10)++0x0F line.long 0x00 "MISC24,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT24_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT24_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT24_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8C00+0x20)++0x0F line.long 0x00 "POST24,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT24_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT24_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT24_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C00+0x30)++0x0F line.long 0x00 "PRE24,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT24_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT24_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT24_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8C00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL24,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT24_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT24_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT24_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 25" group.long 0x8C80++0x0F line.long 0x00 "TARGET_ROOT25,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT25_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT25_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT25_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C80+0x10)++0x0F line.long 0x00 "MISC25,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT25_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT25_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT25_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8C80+0x20)++0x0F line.long 0x00 "POST25,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT25_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT25_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT25_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C80+0x30)++0x0F line.long 0x00 "PRE25,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT25_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT25_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT25_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8C80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL25,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT25_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT25_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT25_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 26" group.long 0x8D00++0x0F line.long 0x00 "TARGET_ROOT26,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT26_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT26_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT26_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D00+0x10)++0x0F line.long 0x00 "MISC26,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT26_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT26_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT26_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8D00+0x20)++0x0F line.long 0x00 "POST26,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT26_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT26_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT26_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D00+0x30)++0x0F line.long 0x00 "PRE26,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT26_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT26_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT26_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8D00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL26,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT26_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT26_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT26_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 27" group.long 0x8D80++0x0F line.long 0x00 "TARGET_ROOT27,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT27_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT27_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT27_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D80+0x10)++0x0F line.long 0x00 "MISC27,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT27_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT27_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT27_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8D80+0x20)++0x0F line.long 0x00 "POST27,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT27_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT27_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT27_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D80+0x30)++0x0F line.long 0x00 "PRE27,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT27_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT27_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT27_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8D80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL27,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT27_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT27_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT27_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 28" group.long 0x8E00++0x0F line.long 0x00 "TARGET_ROOT28,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT28_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT28_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT28_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E00+0x10)++0x0F line.long 0x00 "MISC28,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT28_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT28_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT28_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8E00+0x20)++0x0F line.long 0x00 "POST28,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT28_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT28_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT28_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E00+0x30)++0x0F line.long 0x00 "PRE28,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT28_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT28_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT28_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8E00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL28,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT28_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT28_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT28_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 29" group.long 0x8E80++0x0F line.long 0x00 "TARGET_ROOT29,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT29_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT29_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT29_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E80+0x10)++0x0F line.long 0x00 "MISC29,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT29_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT29_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT29_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8E80+0x20)++0x0F line.long 0x00 "POST29,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT29_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT29_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT29_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E80+0x30)++0x0F line.long 0x00 "PRE29,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT29_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT29_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT29_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8E80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL29,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT29_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT29_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT29_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 30" group.long 0x8F00++0x0F line.long 0x00 "TARGET_ROOT30,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT30_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT30_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT30_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F00+0x10)++0x0F line.long 0x00 "MISC30,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT30_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT30_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT30_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8F00+0x20)++0x0F line.long 0x00 "POST30,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT30_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT30_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT30_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F00+0x30)++0x0F line.long 0x00 "PRE30,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT30_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT30_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT30_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8F00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL30,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT30_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT30_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT30_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 31" group.long 0x8F80++0x0F line.long 0x00 "TARGET_ROOT31,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT31_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT31_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT31_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F80+0x10)++0x0F line.long 0x00 "MISC31,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT31_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT31_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT31_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8F80+0x20)++0x0F line.long 0x00 "POST31,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT31_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT31_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT31_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F80+0x30)++0x0F line.long 0x00 "PRE31,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT31_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT31_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT31_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8F80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL31,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT31_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT31_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT31_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 32" group.long 0x9000++0x0F line.long 0x00 "TARGET_ROOT32,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT32_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT32_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT32_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9000+0x10)++0x0F line.long 0x00 "MISC32,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT32_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT32_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT32_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9000+0x20)++0x0F line.long 0x00 "POST32,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT32_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT32_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT32_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9000+0x30)++0x0F line.long 0x00 "PRE32,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT32_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT32_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT32_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL32,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT32_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT32_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT32_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 33" group.long 0x9080++0x0F line.long 0x00 "TARGET_ROOT33,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT33_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT33_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT33_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9080+0x10)++0x0F line.long 0x00 "MISC33,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT33_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT33_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT33_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9080+0x20)++0x0F line.long 0x00 "POST33,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT33_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT33_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT33_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9080+0x30)++0x0F line.long 0x00 "PRE33,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT33_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT33_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT33_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL33,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT33_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT33_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT33_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 34" group.long 0x9100++0x0F line.long 0x00 "TARGET_ROOT34,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT34_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT34_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT34_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9100+0x10)++0x0F line.long 0x00 "MISC34,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT34_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT34_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT34_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9100+0x20)++0x0F line.long 0x00 "POST34,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT34_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT34_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT34_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9100+0x30)++0x0F line.long 0x00 "PRE34,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT34_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT34_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT34_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL34,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT34_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT34_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT34_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 35" group.long 0x9180++0x0F line.long 0x00 "TARGET_ROOT35,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT35_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT35_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT35_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9180+0x10)++0x0F line.long 0x00 "MISC35,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT35_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT35_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT35_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9180+0x20)++0x0F line.long 0x00 "POST35,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT35_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT35_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT35_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9180+0x30)++0x0F line.long 0x00 "PRE35,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT35_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT35_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT35_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL35,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT35_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT35_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT35_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 36" group.long 0x9200++0x0F line.long 0x00 "TARGET_ROOT36,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT36_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT36_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT36_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9200+0x10)++0x0F line.long 0x00 "MISC36,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT36_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT36_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT36_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9200+0x20)++0x0F line.long 0x00 "POST36,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT36_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT36_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT36_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9200+0x30)++0x0F line.long 0x00 "PRE36,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT36_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT36_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT36_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL36,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT36_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT36_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT36_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 37" group.long 0x9280++0x0F line.long 0x00 "TARGET_ROOT37,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT37_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT37_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT37_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9280+0x10)++0x0F line.long 0x00 "MISC37,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT37_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT37_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT37_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9280+0x20)++0x0F line.long 0x00 "POST37,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT37_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT37_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT37_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9280+0x30)++0x0F line.long 0x00 "PRE37,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT37_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT37_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT37_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL37,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT37_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT37_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT37_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 38" group.long 0x9300++0x0F line.long 0x00 "TARGET_ROOT38,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT38_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT38_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT38_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9300+0x10)++0x0F line.long 0x00 "MISC38,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT38_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT38_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT38_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9300+0x20)++0x0F line.long 0x00 "POST38,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT38_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT38_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT38_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9300+0x30)++0x0F line.long 0x00 "PRE38,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT38_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT38_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT38_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL38,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT38_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT38_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT38_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 39" group.long 0x9380++0x0F line.long 0x00 "TARGET_ROOT39,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT39_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT39_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT39_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9380+0x10)++0x0F line.long 0x00 "MISC39,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT39_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT39_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT39_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9380+0x20)++0x0F line.long 0x00 "POST39,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT39_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT39_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT39_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9380+0x30)++0x0F line.long 0x00 "PRE39,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT39_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT39_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT39_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL39,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT39_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT39_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT39_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 40" group.long 0x9400++0x0F line.long 0x00 "TARGET_ROOT40,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT40_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT40_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT40_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9400+0x10)++0x0F line.long 0x00 "MISC40,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT40_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT40_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT40_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9400+0x20)++0x0F line.long 0x00 "POST40,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT40_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT40_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT40_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9400+0x30)++0x0F line.long 0x00 "PRE40,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT40_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT40_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT40_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL40,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT40_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT40_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT40_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 41" group.long 0x9480++0x0F line.long 0x00 "TARGET_ROOT41,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT41_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT41_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT41_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9480+0x10)++0x0F line.long 0x00 "MISC41,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT41_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT41_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT41_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9480+0x20)++0x0F line.long 0x00 "POST41,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT41_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT41_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT41_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9480+0x30)++0x0F line.long 0x00 "PRE41,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT41_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT41_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT41_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL41,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT41_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT41_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT41_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 42" group.long 0x9500++0x0F line.long 0x00 "TARGET_ROOT42,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT42_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT42_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT42_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9500+0x10)++0x0F line.long 0x00 "MISC42,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT42_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT42_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT42_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9500+0x20)++0x0F line.long 0x00 "POST42,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT42_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT42_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT42_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9500+0x30)++0x0F line.long 0x00 "PRE42,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT42_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT42_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT42_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL42,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT42_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT42_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT42_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 43" group.long 0x9580++0x0F line.long 0x00 "TARGET_ROOT43,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT43_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT43_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT43_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9580+0x10)++0x0F line.long 0x00 "MISC43,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT43_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT43_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT43_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9580+0x20)++0x0F line.long 0x00 "POST43,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT43_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT43_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT43_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9580+0x30)++0x0F line.long 0x00 "PRE43,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT43_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT43_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT43_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL43,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT43_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT43_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT43_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 44" group.long 0x9600++0x0F line.long 0x00 "TARGET_ROOT44,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT44_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT44_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT44_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9600+0x10)++0x0F line.long 0x00 "MISC44,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT44_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT44_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT44_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9600+0x20)++0x0F line.long 0x00 "POST44,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT44_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT44_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT44_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9600+0x30)++0x0F line.long 0x00 "PRE44,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT44_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT44_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT44_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL44,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT44_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT44_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT44_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 45" group.long 0x9680++0x0F line.long 0x00 "TARGET_ROOT45,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT45_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT45_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT45_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9680+0x10)++0x0F line.long 0x00 "MISC45,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT45_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT45_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT45_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9680+0x20)++0x0F line.long 0x00 "POST45,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT45_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT45_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT45_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9680+0x30)++0x0F line.long 0x00 "PRE45,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT45_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT45_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT45_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL45,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT45_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT45_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT45_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 46" group.long 0x9700++0x0F line.long 0x00 "TARGET_ROOT46,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT46_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT46_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT46_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9700+0x10)++0x0F line.long 0x00 "MISC46,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT46_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT46_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT46_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9700+0x20)++0x0F line.long 0x00 "POST46,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT46_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT46_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT46_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9700+0x30)++0x0F line.long 0x00 "PRE46,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT46_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT46_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT46_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL46,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT46_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT46_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT46_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 47" group.long 0x9780++0x0F line.long 0x00 "TARGET_ROOT47,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT47_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT47_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT47_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9780+0x10)++0x0F line.long 0x00 "MISC47,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT47_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT47_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT47_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9780+0x20)++0x0F line.long 0x00 "POST47,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT47_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT47_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT47_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9780+0x30)++0x0F line.long 0x00 "PRE47,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT47_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT47_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT47_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL47,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT47_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT47_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT47_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 48" group.long 0x9800++0x0F line.long 0x00 "TARGET_ROOT48,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT48_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT48_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT48_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9800+0x10)++0x0F line.long 0x00 "MISC48,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT48_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT48_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT48_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9800+0x20)++0x0F line.long 0x00 "POST48,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT48_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT48_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT48_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9800+0x30)++0x0F line.long 0x00 "PRE48,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT48_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT48_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT48_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL48,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT48_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT48_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT48_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 49" group.long 0x9880++0x0F line.long 0x00 "TARGET_ROOT49,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT49_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT49_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT49_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9880+0x10)++0x0F line.long 0x00 "MISC49,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT49_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT49_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT49_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9880+0x20)++0x0F line.long 0x00 "POST49,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT49_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT49_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT49_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9880+0x30)++0x0F line.long 0x00 "PRE49,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT49_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT49_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT49_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL49,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT49_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT49_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT49_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 50" group.long 0x9900++0x0F line.long 0x00 "TARGET_ROOT50,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT50_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT50_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT50_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9900+0x10)++0x0F line.long 0x00 "MISC50,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT50_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT50_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT50_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9900+0x20)++0x0F line.long 0x00 "POST50,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT50_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT50_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT50_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9900+0x30)++0x0F line.long 0x00 "PRE50,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT50_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT50_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT50_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL50,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT50_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT50_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT50_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 51" group.long 0x9980++0x0F line.long 0x00 "TARGET_ROOT51,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT51_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT51_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT51_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9980+0x10)++0x0F line.long 0x00 "MISC51,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT51_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT51_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT51_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9980+0x20)++0x0F line.long 0x00 "POST51,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT51_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT51_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT51_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9980+0x30)++0x0F line.long 0x00 "PRE51,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT51_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT51_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT51_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL51,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT51_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT51_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT51_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 52" group.long 0x9A00++0x0F line.long 0x00 "TARGET_ROOT52,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT52_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT52_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT52_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A00+0x10)++0x0F line.long 0x00 "MISC52,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT52_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT52_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT52_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9A00+0x20)++0x0F line.long 0x00 "POST52,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT52_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT52_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT52_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A00+0x30)++0x0F line.long 0x00 "PRE52,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT52_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT52_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT52_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9A00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL52,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT52_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT52_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT52_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 53" group.long 0x9A80++0x0F line.long 0x00 "TARGET_ROOT53,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT53_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT53_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT53_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A80+0x10)++0x0F line.long 0x00 "MISC53,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT53_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT53_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT53_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9A80+0x20)++0x0F line.long 0x00 "POST53,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT53_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT53_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT53_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A80+0x30)++0x0F line.long 0x00 "PRE53,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT53_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT53_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT53_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9A80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL53,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT53_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT53_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT53_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 54" group.long 0x9B00++0x0F line.long 0x00 "TARGET_ROOT54,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT54_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT54_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT54_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B00+0x10)++0x0F line.long 0x00 "MISC54,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT54_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT54_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT54_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9B00+0x20)++0x0F line.long 0x00 "POST54,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT54_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT54_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT54_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B00+0x30)++0x0F line.long 0x00 "PRE54,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT54_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT54_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT54_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9B00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL54,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT54_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT54_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT54_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 55" group.long 0x9B80++0x0F line.long 0x00 "TARGET_ROOT55,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT55_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT55_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT55_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B80+0x10)++0x0F line.long 0x00 "MISC55,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT55_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT55_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT55_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9B80+0x20)++0x0F line.long 0x00 "POST55,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT55_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT55_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT55_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B80+0x30)++0x0F line.long 0x00 "PRE55,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT55_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT55_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT55_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9B80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL55,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT55_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT55_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT55_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 56" group.long 0x9C00++0x0F line.long 0x00 "TARGET_ROOT56,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT56_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT56_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT56_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C00+0x10)++0x0F line.long 0x00 "MISC56,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT56_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT56_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT56_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9C00+0x20)++0x0F line.long 0x00 "POST56,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT56_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT56_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT56_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C00+0x30)++0x0F line.long 0x00 "PRE56,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT56_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT56_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT56_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9C00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL56,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT56_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT56_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT56_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 57" group.long 0x9C80++0x0F line.long 0x00 "TARGET_ROOT57,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT57_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT57_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT57_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C80+0x10)++0x0F line.long 0x00 "MISC57,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT57_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT57_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT57_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9C80+0x20)++0x0F line.long 0x00 "POST57,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT57_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT57_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT57_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C80+0x30)++0x0F line.long 0x00 "PRE57,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT57_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT57_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT57_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9C80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL57,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT57_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT57_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT57_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 58" group.long 0x9D00++0x0F line.long 0x00 "TARGET_ROOT58,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT58_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT58_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT58_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D00+0x10)++0x0F line.long 0x00 "MISC58,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT58_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT58_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT58_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9D00+0x20)++0x0F line.long 0x00 "POST58,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT58_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT58_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT58_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D00+0x30)++0x0F line.long 0x00 "PRE58,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT58_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT58_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT58_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9D00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL58,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT58_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT58_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT58_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 59" group.long 0x9D80++0x0F line.long 0x00 "TARGET_ROOT59,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT59_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT59_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT59_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D80+0x10)++0x0F line.long 0x00 "MISC59,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT59_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT59_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT59_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9D80+0x20)++0x0F line.long 0x00 "POST59,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT59_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT59_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT59_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D80+0x30)++0x0F line.long 0x00 "PRE59,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT59_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT59_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT59_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9D80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL59,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT59_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT59_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT59_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 60" group.long 0x9E00++0x0F line.long 0x00 "TARGET_ROOT60,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT60_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT60_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT60_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E00+0x10)++0x0F line.long 0x00 "MISC60,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT60_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT60_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT60_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9E00+0x20)++0x0F line.long 0x00 "POST60,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT60_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT60_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT60_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E00+0x30)++0x0F line.long 0x00 "PRE60,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT60_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT60_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT60_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9E00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL60,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT60_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT60_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT60_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 61" group.long 0x9E80++0x0F line.long 0x00 "TARGET_ROOT61,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT61_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT61_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT61_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E80+0x10)++0x0F line.long 0x00 "MISC61,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT61_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT61_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT61_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9E80+0x20)++0x0F line.long 0x00 "POST61,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT61_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT61_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT61_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E80+0x30)++0x0F line.long 0x00 "PRE61,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT61_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT61_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT61_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9E80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL61,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT61_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT61_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT61_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 62" group.long 0x9F00++0x0F line.long 0x00 "TARGET_ROOT62,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT62_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT62_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT62_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F00+0x10)++0x0F line.long 0x00 "MISC62,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT62_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT62_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT62_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9F00+0x20)++0x0F line.long 0x00 "POST62,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT62_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT62_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT62_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F00+0x30)++0x0F line.long 0x00 "PRE62,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT62_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT62_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT62_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9F00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL62,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT62_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT62_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT62_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 63" group.long 0x9F80++0x0F line.long 0x00 "TARGET_ROOT63,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT63_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT63_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT63_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F80+0x10)++0x0F line.long 0x00 "MISC63,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT63_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT63_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT63_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9F80+0x20)++0x0F line.long 0x00 "POST63,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT63_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT63_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT63_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F80+0x30)++0x0F line.long 0x00 "PRE63,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT63_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT63_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT63_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9F80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL63,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT63_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT63_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT63_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 64" group.long 0xA000++0x0F line.long 0x00 "TARGET_ROOT64,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT64_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT64_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT64_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA000+0x10)++0x0F line.long 0x00 "MISC64,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT64_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT64_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT64_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA000+0x20)++0x0F line.long 0x00 "POST64,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT64_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT64_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT64_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA000+0x30)++0x0F line.long 0x00 "PRE64,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT64_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT64_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT64_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL64,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT64_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT64_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT64_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 65" group.long 0xA080++0x0F line.long 0x00 "TARGET_ROOT65,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT65_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT65_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT65_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA080+0x10)++0x0F line.long 0x00 "MISC65,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT65_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT65_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT65_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA080+0x20)++0x0F line.long 0x00 "POST65,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT65_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT65_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT65_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA080+0x30)++0x0F line.long 0x00 "PRE65,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT65_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT65_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT65_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL65,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT65_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT65_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT65_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 66" group.long 0xA100++0x0F line.long 0x00 "TARGET_ROOT66,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT66_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT66_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT66_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA100+0x10)++0x0F line.long 0x00 "MISC66,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT66_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT66_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT66_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA100+0x20)++0x0F line.long 0x00 "POST66,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT66_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT66_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT66_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA100+0x30)++0x0F line.long 0x00 "PRE66,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT66_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT66_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT66_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL66,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT66_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT66_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT66_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 67" group.long 0xA180++0x0F line.long 0x00 "TARGET_ROOT67,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT67_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT67_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT67_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA180+0x10)++0x0F line.long 0x00 "MISC67,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT67_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT67_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT67_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA180+0x20)++0x0F line.long 0x00 "POST67,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT67_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT67_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT67_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA180+0x30)++0x0F line.long 0x00 "PRE67,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT67_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT67_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT67_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL67,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT67_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT67_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT67_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 68" group.long 0xA200++0x0F line.long 0x00 "TARGET_ROOT68,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT68_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT68_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT68_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA200+0x10)++0x0F line.long 0x00 "MISC68,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT68_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT68_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT68_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA200+0x20)++0x0F line.long 0x00 "POST68,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT68_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT68_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT68_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA200+0x30)++0x0F line.long 0x00 "PRE68,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT68_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT68_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT68_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL68,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT68_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT68_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT68_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 69" group.long 0xA280++0x0F line.long 0x00 "TARGET_ROOT69,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT69_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT69_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT69_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA280+0x10)++0x0F line.long 0x00 "MISC69,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT69_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT69_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT69_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA280+0x20)++0x0F line.long 0x00 "POST69,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT69_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT69_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT69_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA280+0x30)++0x0F line.long 0x00 "PRE69,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT69_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT69_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT69_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL69,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT69_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT69_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT69_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 70" group.long 0xA300++0x0F line.long 0x00 "TARGET_ROOT70,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT70_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT70_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT70_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA300+0x10)++0x0F line.long 0x00 "MISC70,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT70_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT70_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT70_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA300+0x20)++0x0F line.long 0x00 "POST70,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT70_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT70_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT70_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA300+0x30)++0x0F line.long 0x00 "PRE70,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT70_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT70_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT70_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL70,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT70_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT70_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT70_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 71" group.long 0xA380++0x0F line.long 0x00 "TARGET_ROOT71,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT71_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT71_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT71_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA380+0x10)++0x0F line.long 0x00 "MISC71,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT71_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT71_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT71_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA380+0x20)++0x0F line.long 0x00 "POST71,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT71_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT71_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT71_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA380+0x30)++0x0F line.long 0x00 "PRE71,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT71_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT71_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT71_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL71,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT71_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT71_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT71_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 72" group.long 0xA400++0x0F line.long 0x00 "TARGET_ROOT72,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT72_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT72_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT72_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA400+0x10)++0x0F line.long 0x00 "MISC72,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT72_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT72_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT72_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA400+0x20)++0x0F line.long 0x00 "POST72,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT72_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT72_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT72_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA400+0x30)++0x0F line.long 0x00 "PRE72,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT72_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT72_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT72_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL72,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT72_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT72_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT72_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 73" group.long 0xA480++0x0F line.long 0x00 "TARGET_ROOT73,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT73_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT73_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT73_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA480+0x10)++0x0F line.long 0x00 "MISC73,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT73_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT73_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT73_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA480+0x20)++0x0F line.long 0x00 "POST73,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT73_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT73_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT73_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA480+0x30)++0x0F line.long 0x00 "PRE73,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT73_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT73_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT73_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL73,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT73_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT73_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT73_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 74" group.long 0xA500++0x0F line.long 0x00 "TARGET_ROOT74,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT74_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT74_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT74_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA500+0x10)++0x0F line.long 0x00 "MISC74,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT74_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT74_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT74_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA500+0x20)++0x0F line.long 0x00 "POST74,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT74_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT74_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT74_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA500+0x30)++0x0F line.long 0x00 "PRE74,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT74_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT74_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT74_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL74,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT74_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT74_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT74_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 75" group.long 0xA580++0x0F line.long 0x00 "TARGET_ROOT75,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT75_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT75_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT75_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA580+0x10)++0x0F line.long 0x00 "MISC75,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT75_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT75_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT75_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA580+0x20)++0x0F line.long 0x00 "POST75,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT75_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT75_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT75_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA580+0x30)++0x0F line.long 0x00 "PRE75,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT75_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT75_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT75_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL75,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT75_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT75_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT75_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 76" group.long 0xA600++0x0F line.long 0x00 "TARGET_ROOT76,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT76_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT76_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT76_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA600+0x10)++0x0F line.long 0x00 "MISC76,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT76_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT76_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT76_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA600+0x20)++0x0F line.long 0x00 "POST76,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT76_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT76_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT76_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA600+0x30)++0x0F line.long 0x00 "PRE76,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT76_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT76_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT76_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL76,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT76_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT76_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT76_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 77" group.long 0xA680++0x0F line.long 0x00 "TARGET_ROOT77,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT77_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT77_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT77_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA680+0x10)++0x0F line.long 0x00 "MISC77,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT77_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT77_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT77_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA680+0x20)++0x0F line.long 0x00 "POST77,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT77_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT77_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT77_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA680+0x30)++0x0F line.long 0x00 "PRE77,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT77_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT77_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT77_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL77,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT77_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT77_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT77_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 78" group.long 0xA700++0x0F line.long 0x00 "TARGET_ROOT78,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT78_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT78_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT78_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA700+0x10)++0x0F line.long 0x00 "MISC78,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT78_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT78_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT78_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA700+0x20)++0x0F line.long 0x00 "POST78,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT78_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT78_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT78_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA700+0x30)++0x0F line.long 0x00 "PRE78,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT78_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT78_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT78_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL78,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT78_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT78_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT78_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 79" group.long 0xA780++0x0F line.long 0x00 "TARGET_ROOT79,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT79_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT79_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT79_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA780+0x10)++0x0F line.long 0x00 "MISC79,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT79_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT79_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT79_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA780+0x20)++0x0F line.long 0x00 "POST79,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT79_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT79_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT79_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA780+0x30)++0x0F line.long 0x00 "PRE79,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT79_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT79_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT79_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL79,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT79_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT79_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT79_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 80" group.long 0xA800++0x0F line.long 0x00 "TARGET_ROOT80,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT80_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT80_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT80_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA800+0x10)++0x0F line.long 0x00 "MISC80,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT80_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT80_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT80_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA800+0x20)++0x0F line.long 0x00 "POST80,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT80_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT80_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT80_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA800+0x30)++0x0F line.long 0x00 "PRE80,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT80_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT80_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT80_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL80,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT80_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT80_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT80_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 81" group.long 0xA880++0x0F line.long 0x00 "TARGET_ROOT81,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT81_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT81_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT81_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA880+0x10)++0x0F line.long 0x00 "MISC81,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT81_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT81_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT81_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA880+0x20)++0x0F line.long 0x00 "POST81,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT81_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT81_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT81_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA880+0x30)++0x0F line.long 0x00 "PRE81,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT81_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT81_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT81_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL81,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT81_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT81_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT81_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 82" group.long 0xA900++0x0F line.long 0x00 "TARGET_ROOT82,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT82_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT82_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT82_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA900+0x10)++0x0F line.long 0x00 "MISC82,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT82_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT82_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT82_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA900+0x20)++0x0F line.long 0x00 "POST82,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT82_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT82_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT82_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA900+0x30)++0x0F line.long 0x00 "PRE82,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT82_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT82_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT82_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL82,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT82_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT82_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT82_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 83" group.long 0xA980++0x0F line.long 0x00 "TARGET_ROOT83,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT83_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT83_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT83_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA980+0x10)++0x0F line.long 0x00 "MISC83,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT83_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT83_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT83_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA980+0x20)++0x0F line.long 0x00 "POST83,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT83_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT83_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT83_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA980+0x30)++0x0F line.long 0x00 "PRE83,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT83_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT83_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT83_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL83,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT83_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT83_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT83_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 84" group.long 0xAA00++0x0F line.long 0x00 "TARGET_ROOT84,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT84_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT84_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT84_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA00+0x10)++0x0F line.long 0x00 "MISC84,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT84_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT84_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT84_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAA00+0x20)++0x0F line.long 0x00 "POST84,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT84_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT84_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT84_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA00+0x30)++0x0F line.long 0x00 "PRE84,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT84_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT84_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT84_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAA00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL84,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT84_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT84_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT84_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 85" group.long 0xAA80++0x0F line.long 0x00 "TARGET_ROOT85,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT85_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT85_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT85_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA80+0x10)++0x0F line.long 0x00 "MISC85,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT85_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT85_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT85_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAA80+0x20)++0x0F line.long 0x00 "POST85,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT85_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT85_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT85_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA80+0x30)++0x0F line.long 0x00 "PRE85,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT85_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT85_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT85_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAA80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL85,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT85_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT85_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT85_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 86" group.long 0xAB00++0x0F line.long 0x00 "TARGET_ROOT86,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT86_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT86_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT86_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB00+0x10)++0x0F line.long 0x00 "MISC86,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT86_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT86_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT86_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAB00+0x20)++0x0F line.long 0x00 "POST86,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT86_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT86_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT86_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB00+0x30)++0x0F line.long 0x00 "PRE86,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT86_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT86_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT86_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAB00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL86,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT86_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT86_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT86_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 87" group.long 0xAB80++0x0F line.long 0x00 "TARGET_ROOT87,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT87_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT87_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT87_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB80+0x10)++0x0F line.long 0x00 "MISC87,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT87_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT87_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT87_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAB80+0x20)++0x0F line.long 0x00 "POST87,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT87_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT87_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT87_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB80+0x30)++0x0F line.long 0x00 "PRE87,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT87_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT87_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT87_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAB80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL87,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT87_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT87_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT87_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 88" group.long 0xAC00++0x0F line.long 0x00 "TARGET_ROOT88,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT88_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT88_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT88_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC00+0x10)++0x0F line.long 0x00 "MISC88,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT88_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT88_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT88_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAC00+0x20)++0x0F line.long 0x00 "POST88,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT88_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT88_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT88_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC00+0x30)++0x0F line.long 0x00 "PRE88,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT88_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT88_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT88_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAC00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL88,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT88_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT88_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT88_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 89" group.long 0xAC80++0x0F line.long 0x00 "TARGET_ROOT89,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT89_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT89_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT89_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC80+0x10)++0x0F line.long 0x00 "MISC89,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT89_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT89_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT89_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAC80+0x20)++0x0F line.long 0x00 "POST89,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT89_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT89_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT89_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC80+0x30)++0x0F line.long 0x00 "PRE89,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT89_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT89_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT89_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAC80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL89,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT89_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT89_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT89_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 90" group.long 0xAD00++0x0F line.long 0x00 "TARGET_ROOT90,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT90_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT90_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT90_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD00+0x10)++0x0F line.long 0x00 "MISC90,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT90_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT90_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT90_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAD00+0x20)++0x0F line.long 0x00 "POST90,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT90_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT90_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT90_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD00+0x30)++0x0F line.long 0x00 "PRE90,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT90_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT90_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT90_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAD00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL90,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT90_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT90_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT90_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 91" group.long 0xAD80++0x0F line.long 0x00 "TARGET_ROOT91,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT91_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT91_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT91_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD80+0x10)++0x0F line.long 0x00 "MISC91,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT91_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT91_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT91_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAD80+0x20)++0x0F line.long 0x00 "POST91,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT91_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT91_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT91_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD80+0x30)++0x0F line.long 0x00 "PRE91,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT91_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT91_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT91_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAD80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL91,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT91_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT91_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT91_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 92" group.long 0xAE00++0x0F line.long 0x00 "TARGET_ROOT92,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT92_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT92_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT92_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE00+0x10)++0x0F line.long 0x00 "MISC92,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT92_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT92_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT92_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAE00+0x20)++0x0F line.long 0x00 "POST92,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT92_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT92_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT92_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE00+0x30)++0x0F line.long 0x00 "PRE92,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT92_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT92_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT92_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAE00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL92,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT92_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT92_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT92_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 93" group.long 0xAE80++0x0F line.long 0x00 "TARGET_ROOT93,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT93_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT93_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT93_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE80+0x10)++0x0F line.long 0x00 "MISC93,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT93_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT93_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT93_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAE80+0x20)++0x0F line.long 0x00 "POST93,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT93_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT93_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT93_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE80+0x30)++0x0F line.long 0x00 "PRE93,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT93_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT93_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT93_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAE80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL93,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT93_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT93_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT93_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 94" group.long 0xAF00++0x0F line.long 0x00 "TARGET_ROOT94,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT94_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT94_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT94_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF00+0x10)++0x0F line.long 0x00 "MISC94,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT94_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT94_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT94_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAF00+0x20)++0x0F line.long 0x00 "POST94,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT94_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT94_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT94_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF00+0x30)++0x0F line.long 0x00 "PRE94,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT94_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT94_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT94_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAF00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL94,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT94_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT94_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT94_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 95" group.long 0xAF80++0x0F line.long 0x00 "TARGET_ROOT95,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT95_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT95_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT95_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF80+0x10)++0x0F line.long 0x00 "MISC95,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT95_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT95_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT95_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAF80+0x20)++0x0F line.long 0x00 "POST95,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT95_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT95_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT95_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF80+0x30)++0x0F line.long 0x00 "PRE95,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT95_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT95_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT95_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAF80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL95,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT95_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT95_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT95_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 96" group.long 0xB000++0x0F line.long 0x00 "TARGET_ROOT96,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT96_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT96_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT96_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB000+0x10)++0x0F line.long 0x00 "MISC96,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT96_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT96_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT96_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB000+0x20)++0x0F line.long 0x00 "POST96,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT96_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT96_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT96_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB000+0x30)++0x0F line.long 0x00 "PRE96,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT96_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT96_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT96_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL96,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT96_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT96_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT96_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 97" group.long 0xB080++0x0F line.long 0x00 "TARGET_ROOT97,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT97_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT97_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT97_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB080+0x10)++0x0F line.long 0x00 "MISC97,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT97_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT97_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT97_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB080+0x20)++0x0F line.long 0x00 "POST97,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT97_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT97_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT97_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB080+0x30)++0x0F line.long 0x00 "PRE97,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT97_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT97_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT97_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL97,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT97_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT97_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT97_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 98" group.long 0xB100++0x0F line.long 0x00 "TARGET_ROOT98,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT98_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT98_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT98_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB100+0x10)++0x0F line.long 0x00 "MISC98,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT98_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT98_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT98_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB100+0x20)++0x0F line.long 0x00 "POST98,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT98_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT98_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT98_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB100+0x30)++0x0F line.long 0x00 "PRE98,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT98_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT98_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT98_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL98,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT98_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT98_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT98_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 99" group.long 0xB180++0x0F line.long 0x00 "TARGET_ROOT99,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT99_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT99_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT99_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB180+0x10)++0x0F line.long 0x00 "MISC99,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT99_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT99_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT99_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB180+0x20)++0x0F line.long 0x00 "POST99,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT99_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT99_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT99_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB180+0x30)++0x0F line.long 0x00 "PRE99,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT99_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT99_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT99_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL99,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT99_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT99_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT99_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 100" group.long 0xB200++0x0F line.long 0x00 "TARGET_ROOT100,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT100_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT100_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT100_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB200+0x10)++0x0F line.long 0x00 "MISC100,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT100_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT100_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT100_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB200+0x20)++0x0F line.long 0x00 "POST100,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT100_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT100_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT100_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB200+0x30)++0x0F line.long 0x00 "PRE100,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT100_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT100_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT100_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL100,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT100_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT100_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT100_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 101" group.long 0xB280++0x0F line.long 0x00 "TARGET_ROOT101,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT101_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT101_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT101_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB280+0x10)++0x0F line.long 0x00 "MISC101,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT101_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT101_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT101_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB280+0x20)++0x0F line.long 0x00 "POST101,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT101_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT101_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT101_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB280+0x30)++0x0F line.long 0x00 "PRE101,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT101_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT101_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT101_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL101,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT101_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT101_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT101_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 102" group.long 0xB300++0x0F line.long 0x00 "TARGET_ROOT102,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT102_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT102_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT102_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB300+0x10)++0x0F line.long 0x00 "MISC102,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT102_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT102_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT102_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB300+0x20)++0x0F line.long 0x00 "POST102,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT102_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT102_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT102_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB300+0x30)++0x0F line.long 0x00 "PRE102,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT102_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT102_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT102_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL102,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT102_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT102_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT102_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 103" group.long 0xB380++0x0F line.long 0x00 "TARGET_ROOT103,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT103_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT103_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT103_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB380+0x10)++0x0F line.long 0x00 "MISC103,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT103_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT103_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT103_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB380+0x20)++0x0F line.long 0x00 "POST103,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT103_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT103_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT103_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB380+0x30)++0x0F line.long 0x00 "PRE103,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT103_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT103_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT103_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL103,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT103_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT103_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT103_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 104" group.long 0xB400++0x0F line.long 0x00 "TARGET_ROOT104,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT104_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT104_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT104_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB400+0x10)++0x0F line.long 0x00 "MISC104,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT104_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT104_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT104_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB400+0x20)++0x0F line.long 0x00 "POST104,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT104_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT104_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT104_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB400+0x30)++0x0F line.long 0x00 "PRE104,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT104_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT104_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT104_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL104,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT104_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT104_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT104_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 105" group.long 0xB480++0x0F line.long 0x00 "TARGET_ROOT105,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT105_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT105_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT105_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB480+0x10)++0x0F line.long 0x00 "MISC105,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT105_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT105_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT105_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB480+0x20)++0x0F line.long 0x00 "POST105,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT105_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT105_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT105_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB480+0x30)++0x0F line.long 0x00 "PRE105,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT105_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT105_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT105_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL105,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT105_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT105_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT105_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 106" group.long 0xB500++0x0F line.long 0x00 "TARGET_ROOT106,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT106_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT106_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT106_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB500+0x10)++0x0F line.long 0x00 "MISC106,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT106_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT106_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT106_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB500+0x20)++0x0F line.long 0x00 "POST106,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT106_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT106_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT106_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB500+0x30)++0x0F line.long 0x00 "PRE106,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT106_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT106_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT106_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL106,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT106_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT106_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT106_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 107" group.long 0xB580++0x0F line.long 0x00 "TARGET_ROOT107,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT107_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT107_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT107_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB580+0x10)++0x0F line.long 0x00 "MISC107,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT107_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT107_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT107_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB580+0x20)++0x0F line.long 0x00 "POST107,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT107_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT107_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT107_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB580+0x30)++0x0F line.long 0x00 "PRE107,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT107_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT107_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT107_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL107,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT107_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT107_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT107_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 108" group.long 0xB600++0x0F line.long 0x00 "TARGET_ROOT108,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT108_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT108_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT108_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB600+0x10)++0x0F line.long 0x00 "MISC108,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT108_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT108_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT108_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB600+0x20)++0x0F line.long 0x00 "POST108,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT108_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT108_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT108_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB600+0x30)++0x0F line.long 0x00 "PRE108,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT108_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT108_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT108_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL108,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT108_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT108_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT108_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 109" group.long 0xB680++0x0F line.long 0x00 "TARGET_ROOT109,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT109_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT109_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT109_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB680+0x10)++0x0F line.long 0x00 "MISC109,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT109_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT109_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT109_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB680+0x20)++0x0F line.long 0x00 "POST109,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT109_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT109_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT109_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB680+0x30)++0x0F line.long 0x00 "PRE109,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT109_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT109_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT109_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL109,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT109_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT109_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT109_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 110" group.long 0xB700++0x0F line.long 0x00 "TARGET_ROOT110,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT110_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT110_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT110_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB700+0x10)++0x0F line.long 0x00 "MISC110,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT110_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT110_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT110_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB700+0x20)++0x0F line.long 0x00 "POST110,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT110_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT110_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT110_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB700+0x30)++0x0F line.long 0x00 "PRE110,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT110_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT110_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT110_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL110,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT110_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT110_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT110_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 111" group.long 0xB780++0x0F line.long 0x00 "TARGET_ROOT111,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT111_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT111_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT111_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB780+0x10)++0x0F line.long 0x00 "MISC111,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT111_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT111_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT111_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB780+0x20)++0x0F line.long 0x00 "POST111,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT111_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT111_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT111_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB780+0x30)++0x0F line.long 0x00 "PRE111,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT111_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT111_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT111_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL111,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT111_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT111_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT111_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 112" group.long 0xB800++0x0F line.long 0x00 "TARGET_ROOT112,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT112_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT112_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT112_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB800+0x10)++0x0F line.long 0x00 "MISC112,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT112_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT112_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT112_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB800+0x20)++0x0F line.long 0x00 "POST112,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT112_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT112_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT112_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB800+0x30)++0x0F line.long 0x00 "PRE112,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT112_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT112_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT112_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL112,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT112_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT112_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT112_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 113" group.long 0xB880++0x0F line.long 0x00 "TARGET_ROOT113,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT113_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT113_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT113_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB880+0x10)++0x0F line.long 0x00 "MISC113,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT113_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT113_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT113_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB880+0x20)++0x0F line.long 0x00 "POST113,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT113_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT113_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT113_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB880+0x30)++0x0F line.long 0x00 "PRE113,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT113_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT113_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT113_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL113,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT113_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT113_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT113_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 114" group.long 0xB900++0x0F line.long 0x00 "TARGET_ROOT114,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT114_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT114_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT114_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB900+0x10)++0x0F line.long 0x00 "MISC114,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT114_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT114_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT114_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB900+0x20)++0x0F line.long 0x00 "POST114,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT114_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT114_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT114_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB900+0x30)++0x0F line.long 0x00 "PRE114,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT114_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT114_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT114_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL114,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT114_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT114_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT114_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 115" group.long 0xB980++0x0F line.long 0x00 "TARGET_ROOT115,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT115_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT115_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT115_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB980+0x10)++0x0F line.long 0x00 "MISC115,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT115_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT115_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT115_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB980+0x20)++0x0F line.long 0x00 "POST115,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT115_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT115_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT115_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB980+0x30)++0x0F line.long 0x00 "PRE115,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT115_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT115_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT115_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL115,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT115_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT115_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT115_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 116" group.long 0xBA00++0x0F line.long 0x00 "TARGET_ROOT116,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT116_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT116_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT116_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA00+0x10)++0x0F line.long 0x00 "MISC116,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT116_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT116_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT116_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBA00+0x20)++0x0F line.long 0x00 "POST116,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT116_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT116_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT116_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA00+0x30)++0x0F line.long 0x00 "PRE116,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT116_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT116_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT116_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBA00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL116,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT116_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT116_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT116_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 117" group.long 0xBA80++0x0F line.long 0x00 "TARGET_ROOT117,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT117_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT117_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT117_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA80+0x10)++0x0F line.long 0x00 "MISC117,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT117_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT117_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT117_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBA80+0x20)++0x0F line.long 0x00 "POST117,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT117_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT117_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT117_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA80+0x30)++0x0F line.long 0x00 "PRE117,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT117_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT117_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT117_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBA80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL117,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT117_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT117_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT117_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 118" group.long 0xBB00++0x0F line.long 0x00 "TARGET_ROOT118,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT118_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT118_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT118_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB00+0x10)++0x0F line.long 0x00 "MISC118,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT118_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT118_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT118_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBB00+0x20)++0x0F line.long 0x00 "POST118,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT118_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT118_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT118_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB00+0x30)++0x0F line.long 0x00 "PRE118,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT118_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT118_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT118_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBB00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL118,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT118_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT118_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT118_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 119" group.long 0xBB80++0x0F line.long 0x00 "TARGET_ROOT119,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT119_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT119_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT119_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB80+0x10)++0x0F line.long 0x00 "MISC119,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT119_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT119_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT119_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBB80+0x20)++0x0F line.long 0x00 "POST119,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT119_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT119_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT119_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB80+0x30)++0x0F line.long 0x00 "PRE119,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT119_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT119_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT119_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBB80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL119,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT119_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT119_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT119_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 120" group.long 0xBC00++0x0F line.long 0x00 "TARGET_ROOT120,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT120_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT120_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT120_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC00+0x10)++0x0F line.long 0x00 "MISC120,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT120_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT120_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT120_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBC00+0x20)++0x0F line.long 0x00 "POST120,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT120_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT120_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT120_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC00+0x30)++0x0F line.long 0x00 "PRE120,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT120_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT120_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT120_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBC00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL120,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT120_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT120_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT120_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 121" group.long 0xBC80++0x0F line.long 0x00 "TARGET_ROOT121,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT121_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT121_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT121_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC80+0x10)++0x0F line.long 0x00 "MISC121,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT121_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT121_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT121_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBC80+0x20)++0x0F line.long 0x00 "POST121,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT121_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT121_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT121_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC80+0x30)++0x0F line.long 0x00 "PRE121,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT121_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT121_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT121_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBC80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL121,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT121_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT121_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT121_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 122" group.long 0xBD00++0x0F line.long 0x00 "TARGET_ROOT122,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT122_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT122_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT122_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBD00+0x10)++0x0F line.long 0x00 "MISC122,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT122_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT122_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT122_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBD00+0x20)++0x0F line.long 0x00 "POST122,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT122_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT122_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT122_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBD00+0x30)++0x0F line.long 0x00 "PRE122,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT122_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT122_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT122_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBD00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL122,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT122_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT122_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT122_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 123" group.long 0xBD80++0x0F line.long 0x00 "TARGET_ROOT123,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT123_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT123_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT123_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBD80+0x10)++0x0F line.long 0x00 "MISC123,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT123_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT123_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT123_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBD80+0x20)++0x0F line.long 0x00 "POST123,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT123_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT123_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT123_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBD80+0x30)++0x0F line.long 0x00 "PRE123,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT123_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT123_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT123_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBD80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL123,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT123_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT123_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT123_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 124" group.long 0xBE00++0x0F line.long 0x00 "TARGET_ROOT124,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT124_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT124_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT124_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBE00+0x10)++0x0F line.long 0x00 "MISC124,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT124_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT124_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT124_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBE00+0x20)++0x0F line.long 0x00 "POST124,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT124_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT124_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT124_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBE00+0x30)++0x0F line.long 0x00 "PRE124,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT124_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT124_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT124_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBE00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL124,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT124_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT124_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT124_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end width 0x0B else width 10. group.long 0x00++0x0F line.long 0x00 "GPR0,General Purpose Register" line.long 0x04 "GPR0_SET,General Purpose Set Register" line.long 0x08 "GPR0_CLR,General Purpose Clear Register" line.long 0x0C "GPR0_TOG,General Purpose Toggle Register" width 16. tree "Input Clocks Registers" group.long 0x800++0x0F "PLL Control 0" line.long 0x00 "PLL_CTRL0,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL0_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL0_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL0_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x810++0x0F "PLL Control 1" line.long 0x00 "PLL_CTRL1,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL1_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL1_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL1_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x820++0x0F "PLL Control 2" line.long 0x00 "PLL_CTRL2,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL2_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL2_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL2_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x830++0x0F "PLL Control 3" line.long 0x00 "PLL_CTRL3,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL3_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL3_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL3_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x840++0x0F "PLL Control 4" line.long 0x00 "PLL_CTRL4,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL4_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL4_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL4_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x850++0x0F "PLL Control 5" line.long 0x00 "PLL_CTRL5,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL5_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL5_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL5_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x860++0x0F "PLL Control 6" line.long 0x00 "PLL_CTRL6,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL6_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL6_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL6_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x870++0x0F "PLL Control 7" line.long 0x00 "PLL_CTRL7,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL7_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL7_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL7_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x880++0x0F "PLL Control 8" line.long 0x00 "PLL_CTRL8,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL8_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL8_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL8_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x890++0x0F "PLL Control 9" line.long 0x00 "PLL_CTRL9,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL9_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL9_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL9_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8A0++0x0F "PLL Control 10" line.long 0x00 "PLL_CTRL10,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL10_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL10_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL10_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8B0++0x0F "PLL Control 11" line.long 0x00 "PLL_CTRL11,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL11_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL11_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL11_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8C0++0x0F "PLL Control 12" line.long 0x00 "PLL_CTRL12,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL12_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL12_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL12_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8D0++0x0F "PLL Control 13" line.long 0x00 "PLL_CTRL13,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL13_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL13_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL13_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8E0++0x0F "PLL Control 14" line.long 0x00 "PLL_CTRL14,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL14_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL14_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL14_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x8F0++0x0F "PLL Control 15" line.long 0x00 "PLL_CTRL15,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL15_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL15_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL15_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x900++0x0F "PLL Control 16" line.long 0x00 "PLL_CTRL16,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL16_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL16_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL16_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x910++0x0F "PLL Control 17" line.long 0x00 "PLL_CTRL17,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL17_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL17_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL17_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x920++0x0F "PLL Control 18" line.long 0x00 "PLL_CTRL18,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL18_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL18_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL18_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x930++0x0F "PLL Control 19" line.long 0x00 "PLL_CTRL19,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL19_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL19_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL19_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x940++0x0F "PLL Control 20" line.long 0x00 "PLL_CTRL20,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL20_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL20_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL20_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x950++0x0F "PLL Control 21" line.long 0x00 "PLL_CTRL21,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL21_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL21_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL21_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x960++0x0F "PLL Control 22" line.long 0x00 "PLL_CTRL22,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL22_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL22_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL22_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x970++0x0F "PLL Control 23" line.long 0x00 "PLL_CTRL23,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL23_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL23_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL23_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x980++0x0F "PLL Control 24" line.long 0x00 "PLL_CTRL24,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL24_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL24_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL24_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x990++0x0F "PLL Control 25" line.long 0x00 "PLL_CTRL25,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL25_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL25_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL25_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9A0++0x0F "PLL Control 26" line.long 0x00 "PLL_CTRL26,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL26_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL26_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL26_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9B0++0x0F "PLL Control 27" line.long 0x00 "PLL_CTRL27,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL27_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL27_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL27_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9C0++0x0F "PLL Control 28" line.long 0x00 "PLL_CTRL28,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL28_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL28_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL28_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9D0++0x0F "PLL Control 29" line.long 0x00 "PLL_CTRL29,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL29_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL29_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL29_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9E0++0x0F "PLL Control 30" line.long 0x00 "PLL_CTRL30,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL30_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL30_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL30_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x9F0++0x0F "PLL Control 31" line.long 0x00 "PLL_CTRL31,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL31_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL31_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL31_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0xA00++0x0F "PLL Control 32" line.long 0x00 "PLL_CTRL32,CCM PLL Control Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "PLL_CTRL32_SET,CCM PLL Control Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "PLL_CTRL32_CLR,CCM PLL Control Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "PLL_CTRL32_TOG,CCM PLL Control Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" tree.end width 13. tree "Clock Gating Interface Registers" group.long 0x4000++0x0F "Clock Gating 0" line.long 0x00 "CCGR0,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR0_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR0_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR0_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4010++0x0F "Clock Gating 1" line.long 0x00 "CCGR1,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR1_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR1_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR1_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4020++0x0F "Clock Gating 2" line.long 0x00 "CCGR2,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR2_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR2_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR2_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4030++0x0F "Clock Gating 3" line.long 0x00 "CCGR3,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR3_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR3_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR3_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4040++0x0F "Clock Gating 4" line.long 0x00 "CCGR4,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR4_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR4_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR4_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4050++0x0F "Clock Gating 5" line.long 0x00 "CCGR5,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR5_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR5_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR5_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4060++0x0F "Clock Gating 6" line.long 0x00 "CCGR6,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR6_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR6_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR6_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4070++0x0F "Clock Gating 7" line.long 0x00 "CCGR7,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR7_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR7_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR7_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4080++0x0F "Clock Gating 8" line.long 0x00 "CCGR8,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR8_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR8_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR8_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4090++0x0F "Clock Gating 9" line.long 0x00 "CCGR9,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR9_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR9_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR9_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40A0++0x0F "Clock Gating 10" line.long 0x00 "CCGR10,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR10_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR10_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR10_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40B0++0x0F "Clock Gating 11" line.long 0x00 "CCGR11,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR11_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR11_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR11_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40C0++0x0F "Clock Gating 12" line.long 0x00 "CCGR12,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR12_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR12_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR12_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40D0++0x0F "Clock Gating 13" line.long 0x00 "CCGR13,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR13_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR13_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR13_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40E0++0x0F "Clock Gating 14" line.long 0x00 "CCGR14,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR14_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR14_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR14_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x40F0++0x0F "Clock Gating 15" line.long 0x00 "CCGR15,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR15_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR15_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR15_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4100++0x0F "Clock Gating 16" line.long 0x00 "CCGR16,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR16_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR16_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR16_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4110++0x0F "Clock Gating 17" line.long 0x00 "CCGR17,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR17_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR17_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR17_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4120++0x0F "Clock Gating 18" line.long 0x00 "CCGR18,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR18_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR18_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR18_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4130++0x0F "Clock Gating 19" line.long 0x00 "CCGR19,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR19_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR19_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR19_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4140++0x0F "Clock Gating 20" line.long 0x00 "CCGR20,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR20_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR20_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR20_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4150++0x0F "Clock Gating 21" line.long 0x00 "CCGR21,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR21_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR21_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR21_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4160++0x0F "Clock Gating 22" line.long 0x00 "CCGR22,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR22_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR22_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR22_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4170++0x0F "Clock Gating 23" line.long 0x00 "CCGR23,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR23_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR23_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR23_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4180++0x0F "Clock Gating 24" line.long 0x00 "CCGR24,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR24_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR24_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR24_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4190++0x0F "Clock Gating 25" line.long 0x00 "CCGR25,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR25_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR25_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR25_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41A0++0x0F "Clock Gating 26" line.long 0x00 "CCGR26,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR26_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR26_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR26_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41B0++0x0F "Clock Gating 27" line.long 0x00 "CCGR27,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR27_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR27_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR27_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41C0++0x0F "Clock Gating 28" line.long 0x00 "CCGR28,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR28_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR28_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR28_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41D0++0x0F "Clock Gating 29" line.long 0x00 "CCGR29,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR29_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR29_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR29_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41E0++0x0F "Clock Gating 30" line.long 0x00 "CCGR30,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR30_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR30_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR30_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x41F0++0x0F "Clock Gating 31" line.long 0x00 "CCGR31,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR31_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR31_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR31_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4200++0x0F "Clock Gating 32" line.long 0x00 "CCGR32,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR32_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR32_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR32_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4210++0x0F "Clock Gating 33" line.long 0x00 "CCGR33,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR33_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR33_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR33_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4220++0x0F "Clock Gating 34" line.long 0x00 "CCGR34,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR34_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR34_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR34_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4230++0x0F "Clock Gating 35" line.long 0x00 "CCGR35,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR35_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR35_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR35_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4240++0x0F "Clock Gating 36" line.long 0x00 "CCGR36,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR36_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR36_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR36_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4250++0x0F "Clock Gating 37" line.long 0x00 "CCGR37,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR37_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR37_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR37_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4260++0x0F "Clock Gating 38" line.long 0x00 "CCGR38,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR38_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR38_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR38_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4270++0x0F "Clock Gating 39" line.long 0x00 "CCGR39,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR39_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR39_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR39_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4280++0x0F "Clock Gating 40" line.long 0x00 "CCGR40,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR40_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR40_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR40_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4290++0x0F "Clock Gating 41" line.long 0x00 "CCGR41,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR41_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR41_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR41_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42A0++0x0F "Clock Gating 42" line.long 0x00 "CCGR42,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR42_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR42_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR42_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42B0++0x0F "Clock Gating 43" line.long 0x00 "CCGR43,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR43_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR43_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR43_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42C0++0x0F "Clock Gating 44" line.long 0x00 "CCGR44,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR44_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR44_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR44_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42D0++0x0F "Clock Gating 45" line.long 0x00 "CCGR45,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR45_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR45_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR45_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42E0++0x0F "Clock Gating 46" line.long 0x00 "CCGR46,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR46_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR46_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR46_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x42F0++0x0F "Clock Gating 47" line.long 0x00 "CCGR47,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR47_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR47_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR47_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4300++0x0F "Clock Gating 48" line.long 0x00 "CCGR48,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR48_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR48_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR48_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4310++0x0F "Clock Gating 49" line.long 0x00 "CCGR49,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR49_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR49_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR49_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4320++0x0F "Clock Gating 50" line.long 0x00 "CCGR50,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR50_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR50_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR50_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4330++0x0F "Clock Gating 51" line.long 0x00 "CCGR51,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR51_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR51_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR51_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4340++0x0F "Clock Gating 52" line.long 0x00 "CCGR52,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR52_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR52_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR52_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4350++0x0F "Clock Gating 53" line.long 0x00 "CCGR53,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR53_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR53_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR53_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4360++0x0F "Clock Gating 54" line.long 0x00 "CCGR54,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR54_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR54_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR54_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4370++0x0F "Clock Gating 55" line.long 0x00 "CCGR55,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR55_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR55_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR55_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4380++0x0F "Clock Gating 56" line.long 0x00 "CCGR56,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR56_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR56_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR56_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4390++0x0F "Clock Gating 57" line.long 0x00 "CCGR57,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR57_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR57_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR57_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43A0++0x0F "Clock Gating 58" line.long 0x00 "CCGR58,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR58_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR58_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR58_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43B0++0x0F "Clock Gating 59" line.long 0x00 "CCGR59,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR59_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR59_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR59_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43C0++0x0F "Clock Gating 60" line.long 0x00 "CCGR60,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR60_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR60_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR60_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43D0++0x0F "Clock Gating 61" line.long 0x00 "CCGR61,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR61_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR61_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR61_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43E0++0x0F "Clock Gating 62" line.long 0x00 "CCGR62,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR62_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR62_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR62_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x43F0++0x0F "Clock Gating 63" line.long 0x00 "CCGR63,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR63_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR63_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR63_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4400++0x0F "Clock Gating 64" line.long 0x00 "CCGR64,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR64_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR64_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR64_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4410++0x0F "Clock Gating 65" line.long 0x00 "CCGR65,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR65_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR65_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR65_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4420++0x0F "Clock Gating 66" line.long 0x00 "CCGR66,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR66_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR66_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR66_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4430++0x0F "Clock Gating 67" line.long 0x00 "CCGR67,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR67_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR67_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR67_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4440++0x0F "Clock Gating 68" line.long 0x00 "CCGR68,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR68_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR68_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR68_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4450++0x0F "Clock Gating 69" line.long 0x00 "CCGR69,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR69_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR69_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR69_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4460++0x0F "Clock Gating 70" line.long 0x00 "CCGR70,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR70_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR70_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR70_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4470++0x0F "Clock Gating 71" line.long 0x00 "CCGR71,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR71_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR71_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR71_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4480++0x0F "Clock Gating 72" line.long 0x00 "CCGR72,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR72_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR72_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR72_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4490++0x0F "Clock Gating 73" line.long 0x00 "CCGR73,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR73_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR73_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR73_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44A0++0x0F "Clock Gating 74" line.long 0x00 "CCGR74,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR74_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR74_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR74_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44B0++0x0F "Clock Gating 75" line.long 0x00 "CCGR75,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR75_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR75_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR75_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44C0++0x0F "Clock Gating 76" line.long 0x00 "CCGR76,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR76_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR76_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR76_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44D0++0x0F "Clock Gating 77" line.long 0x00 "CCGR77,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR77_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR77_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR77_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44E0++0x0F "Clock Gating 78" line.long 0x00 "CCGR78,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR78_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR78_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR78_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x44F0++0x0F "Clock Gating 79" line.long 0x00 "CCGR79,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR79_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR79_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR79_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4500++0x0F "Clock Gating 80" line.long 0x00 "CCGR80,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR80_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR80_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR80_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4510++0x0F "Clock Gating 81" line.long 0x00 "CCGR81,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR81_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR81_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR81_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4520++0x0F "Clock Gating 82" line.long 0x00 "CCGR82,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR82_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR82_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR82_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4530++0x0F "Clock Gating 83" line.long 0x00 "CCGR83,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR83_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR83_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR83_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4540++0x0F "Clock Gating 84" line.long 0x00 "CCGR84,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR84_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR84_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR84_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4550++0x0F "Clock Gating 85" line.long 0x00 "CCGR85,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR85_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR85_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR85_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4560++0x0F "Clock Gating 86" line.long 0x00 "CCGR86,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR86_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR86_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR86_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4570++0x0F "Clock Gating 87" line.long 0x00 "CCGR87,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR87_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR87_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR87_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4580++0x0F "Clock Gating 88" line.long 0x00 "CCGR88,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR88_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR88_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR88_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4590++0x0F "Clock Gating 89" line.long 0x00 "CCGR89,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR89_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR89_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR89_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45A0++0x0F "Clock Gating 90" line.long 0x00 "CCGR90,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR90_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR90_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR90_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45B0++0x0F "Clock Gating 91" line.long 0x00 "CCGR91,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR91_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR91_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR91_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45C0++0x0F "Clock Gating 92" line.long 0x00 "CCGR92,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR92_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR92_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR92_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45D0++0x0F "Clock Gating 93" line.long 0x00 "CCGR93,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR93_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR93_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR93_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45E0++0x0F "Clock Gating 94" line.long 0x00 "CCGR94,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR94_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR94_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR94_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x45F0++0x0F "Clock Gating 95" line.long 0x00 "CCGR95,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR95_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR95_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR95_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4600++0x0F "Clock Gating 96" line.long 0x00 "CCGR96,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR96_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR96_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR96_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4610++0x0F "Clock Gating 97" line.long 0x00 "CCGR97,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR97_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR97_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR97_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4620++0x0F "Clock Gating 98" line.long 0x00 "CCGR98,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR98_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR98_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR98_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4630++0x0F "Clock Gating 99" line.long 0x00 "CCGR99,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR99_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR99_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR99_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4640++0x0F "Clock Gating 100" line.long 0x00 "CCGR100,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR100_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR100_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR100_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4650++0x0F "Clock Gating 101" line.long 0x00 "CCGR101,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR101_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR101_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR101_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4660++0x0F "Clock Gating 102" line.long 0x00 "CCGR102,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR102_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR102_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR102_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4670++0x0F "Clock Gating 103" line.long 0x00 "CCGR103,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR103_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR103_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR103_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4680++0x0F "Clock Gating 104" line.long 0x00 "CCGR104,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR104_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR104_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR104_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4690++0x0F "Clock Gating 105" line.long 0x00 "CCGR105,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR105_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR105_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR105_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46A0++0x0F "Clock Gating 106" line.long 0x00 "CCGR106,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR106_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR106_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR106_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46B0++0x0F "Clock Gating 107" line.long 0x00 "CCGR107,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR107_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR107_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR107_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46C0++0x0F "Clock Gating 108" line.long 0x00 "CCGR108,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR108_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR108_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR108_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46D0++0x0F "Clock Gating 109" line.long 0x00 "CCGR109,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR109_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR109_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR109_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46E0++0x0F "Clock Gating 110" line.long 0x00 "CCGR110,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR110_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR110_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR110_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x46F0++0x0F "Clock Gating 111" line.long 0x00 "CCGR111,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR111_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR111_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR111_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4700++0x0F "Clock Gating 112" line.long 0x00 "CCGR112,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR112_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR112_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR112_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4710++0x0F "Clock Gating 113" line.long 0x00 "CCGR113,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR113_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR113_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR113_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4720++0x0F "Clock Gating 114" line.long 0x00 "CCGR114,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR114_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR114_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR114_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4730++0x0F "Clock Gating 115" line.long 0x00 "CCGR115,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR115_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR115_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR115_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4740++0x0F "Clock Gating 116" line.long 0x00 "CCGR116,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR116_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR116_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR116_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4750++0x0F "Clock Gating 117" line.long 0x00 "CCGR117,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR117_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR117_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR117_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4760++0x0F "Clock Gating 118" line.long 0x00 "CCGR118,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR118_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR118_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR118_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4770++0x0F "Clock Gating 119" line.long 0x00 "CCGR119,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR119_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR119_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR119_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4780++0x0F "Clock Gating 120" line.long 0x00 "CCGR120,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR120_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR120_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR120_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4790++0x0F "Clock Gating 121" line.long 0x00 "CCGR121,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR121_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR121_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR121_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47A0++0x0F "Clock Gating 122" line.long 0x00 "CCGR122,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR122_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR122_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR122_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47B0++0x0F "Clock Gating 123" line.long 0x00 "CCGR123,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR123_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR123_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR123_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47C0++0x0F "Clock Gating 124" line.long 0x00 "CCGR124,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR124_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR124_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR124_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47D0++0x0F "Clock Gating 125" line.long 0x00 "CCGR125,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR125_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR125_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR125_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47E0++0x0F "Clock Gating 126" line.long 0x00 "CCGR126,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR126_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR126_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR126_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x47F0++0x0F "Clock Gating 127" line.long 0x00 "CCGR127,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR127_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR127_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR127_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4800++0x0F "Clock Gating 128" line.long 0x00 "CCGR128,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR128_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR128_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR128_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4810++0x0F "Clock Gating 129" line.long 0x00 "CCGR129,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR129_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR129_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR129_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4820++0x0F "Clock Gating 130" line.long 0x00 "CCGR130,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR130_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR130_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR130_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4830++0x0F "Clock Gating 131" line.long 0x00 "CCGR131,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR131_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR131_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR131_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4840++0x0F "Clock Gating 132" line.long 0x00 "CCGR132,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR132_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR132_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR132_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4850++0x0F "Clock Gating 133" line.long 0x00 "CCGR133,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR133_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR133_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR133_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4860++0x0F "Clock Gating 134" line.long 0x00 "CCGR134,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR134_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR134_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR134_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4870++0x0F "Clock Gating 135" line.long 0x00 "CCGR135,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR135_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR135_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR135_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4880++0x0F "Clock Gating 136" line.long 0x00 "CCGR136,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR136_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR136_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR136_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4890++0x0F "Clock Gating 137" line.long 0x00 "CCGR137,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR137_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR137_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR137_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48A0++0x0F "Clock Gating 138" line.long 0x00 "CCGR138,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR138_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR138_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR138_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48B0++0x0F "Clock Gating 139" line.long 0x00 "CCGR139,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR139_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR139_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR139_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48C0++0x0F "Clock Gating 140" line.long 0x00 "CCGR140,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR140_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR140_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR140_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48D0++0x0F "Clock Gating 141" line.long 0x00 "CCGR141,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR141_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR141_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR141_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48E0++0x0F "Clock Gating 142" line.long 0x00 "CCGR142,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR142_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR142_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR142_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x48F0++0x0F "Clock Gating 143" line.long 0x00 "CCGR143,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR143_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR143_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR143_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4900++0x0F "Clock Gating 144" line.long 0x00 "CCGR144,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR144_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR144_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR144_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4910++0x0F "Clock Gating 145" line.long 0x00 "CCGR145,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR145_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR145_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR145_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4920++0x0F "Clock Gating 146" line.long 0x00 "CCGR146,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR146_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR146_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR146_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4930++0x0F "Clock Gating 147" line.long 0x00 "CCGR147,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR147_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR147_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR147_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4940++0x0F "Clock Gating 148" line.long 0x00 "CCGR148,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR148_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR148_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR148_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4950++0x0F "Clock Gating 149" line.long 0x00 "CCGR149,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR149_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR149_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR149_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4960++0x0F "Clock Gating 150" line.long 0x00 "CCGR150,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR150_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR150_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR150_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4970++0x0F "Clock Gating 151" line.long 0x00 "CCGR151,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR151_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR151_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR151_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4980++0x0F "Clock Gating 152" line.long 0x00 "CCGR152,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR152_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR152_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR152_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4990++0x0F "Clock Gating 153" line.long 0x00 "CCGR153,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR153_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR153_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR153_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49A0++0x0F "Clock Gating 154" line.long 0x00 "CCGR154,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR154_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR154_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR154_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49B0++0x0F "Clock Gating 155" line.long 0x00 "CCGR155,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR155_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR155_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR155_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49C0++0x0F "Clock Gating 156" line.long 0x00 "CCGR156,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR156_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR156_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR156_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49D0++0x0F "Clock Gating 157" line.long 0x00 "CCGR157,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR157_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR157_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR157_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49E0++0x0F "Clock Gating 158" line.long 0x00 "CCGR158,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR158_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR158_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR158_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x49F0++0x0F "Clock Gating 159" line.long 0x00 "CCGR159,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR159_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR159_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR159_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A00++0x0F "Clock Gating 160" line.long 0x00 "CCGR160,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR160_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR160_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR160_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A10++0x0F "Clock Gating 161" line.long 0x00 "CCGR161,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR161_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR161_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR161_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A20++0x0F "Clock Gating 162" line.long 0x00 "CCGR162,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR162_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR162_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR162_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A30++0x0F "Clock Gating 163" line.long 0x00 "CCGR163,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR163_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR163_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR163_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A40++0x0F "Clock Gating 164" line.long 0x00 "CCGR164,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR164_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR164_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR164_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A50++0x0F "Clock Gating 165" line.long 0x00 "CCGR165,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR165_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR165_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR165_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A60++0x0F "Clock Gating 166" line.long 0x00 "CCGR166,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR166_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR166_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR166_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A70++0x0F "Clock Gating 167" line.long 0x00 "CCGR167,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR167_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR167_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR167_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A80++0x0F "Clock Gating 168" line.long 0x00 "CCGR168,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR168_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR168_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR168_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4A90++0x0F "Clock Gating 169" line.long 0x00 "CCGR169,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR169_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR169_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR169_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AA0++0x0F "Clock Gating 170" line.long 0x00 "CCGR170,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR170_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR170_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR170_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AB0++0x0F "Clock Gating 171" line.long 0x00 "CCGR171,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR171_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR171_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR171_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AC0++0x0F "Clock Gating 172" line.long 0x00 "CCGR172,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR172_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR172_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR172_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AD0++0x0F "Clock Gating 173" line.long 0x00 "CCGR173,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR173_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR173_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR173_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AE0++0x0F "Clock Gating 174" line.long 0x00 "CCGR174,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR174_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR174_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR174_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4AF0++0x0F "Clock Gating 175" line.long 0x00 "CCGR175,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR175_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR175_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR175_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B00++0x0F "Clock Gating 176" line.long 0x00 "CCGR176,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR176_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR176_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR176_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B10++0x0F "Clock Gating 177" line.long 0x00 "CCGR177,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR177_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR177_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR177_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B20++0x0F "Clock Gating 178" line.long 0x00 "CCGR178,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR178_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR178_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR178_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B30++0x0F "Clock Gating 179" line.long 0x00 "CCGR179,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR179_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR179_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR179_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B40++0x0F "Clock Gating 180" line.long 0x00 "CCGR180,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR180_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR180_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR180_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B50++0x0F "Clock Gating 181" line.long 0x00 "CCGR181,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR181_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR181_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR181_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B60++0x0F "Clock Gating 182" line.long 0x00 "CCGR182,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR182_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR182_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR182_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B70++0x0F "Clock Gating 183" line.long 0x00 "CCGR183,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR183_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR183_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR183_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B80++0x0F "Clock Gating 184" line.long 0x00 "CCGR184,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR184_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR184_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR184_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4B90++0x0F "Clock Gating 185" line.long 0x00 "CCGR185,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR185_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR185_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR185_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BA0++0x0F "Clock Gating 186" line.long 0x00 "CCGR186,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR186_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR186_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR186_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BB0++0x0F "Clock Gating 187" line.long 0x00 "CCGR187,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR187_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR187_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR187_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BC0++0x0F "Clock Gating 188" line.long 0x00 "CCGR188,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR188_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR188_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR188_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BD0++0x0F "Clock Gating 189" line.long 0x00 "CCGR189,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR189_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR189_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR189_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" group.long 0x4BE0++0x0F "Clock Gating 190" line.long 0x00 "CCGR190,CCM Clock Gating Register" bitfld.long 0x00 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x00 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x04 "CCGR190_SET,CCM Clock Gating Set Register" bitfld.long 0x04 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x04 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x08 "CCGR190_CLR,CCM Clock Gating Clear Register" bitfld.long 0x08 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x08 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" line.long 0x0C "CCGR190_TOG,CCM Clock Gating Toggle Register" bitfld.long 0x0C 12.--13. " SETTING3 ,Clock gate control setting for domain 3" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 8.--9. " SETTING2 ,Clock gate control setting for domain 2" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 4.--5. " SETTING1 ,Clock gate control setting for domain 1" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" bitfld.long 0x0C 0.--1. " SETTING0 ,Clock gate control setting for domain 0" "Not needed,Needed in RUN,Needed in RUN and WAIT,Needed all the time" tree.end width 25. tree "Clock Root Registers" tree "Clock Root 0" group.long 0x8000++0x0F line.long 0x00 "TARGET_ROOT0,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT0_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT0_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT0_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8000+0x10)++0x0F line.long 0x00 "MISC0,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT0_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT0_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT0_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8000+0x20)++0x0F line.long 0x00 "POST0,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT0_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT0_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT0_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8000+0x30)++0x0F line.long 0x00 "PRE0,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT0_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT0_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT0_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL0,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT0_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT0_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT0_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 1" group.long 0x8080++0x0F line.long 0x00 "TARGET_ROOT1,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT1_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT1_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT1_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8080+0x10)++0x0F line.long 0x00 "MISC1,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT1_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT1_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT1_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8080+0x20)++0x0F line.long 0x00 "POST1,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT1_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT1_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT1_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8080+0x30)++0x0F line.long 0x00 "PRE1,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT1_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT1_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT1_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL1,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT1_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT1_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT1_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 2" group.long 0x8100++0x0F line.long 0x00 "TARGET_ROOT2,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT2_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT2_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT2_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8100+0x10)++0x0F line.long 0x00 "MISC2,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT2_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT2_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT2_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8100+0x20)++0x0F line.long 0x00 "POST2,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT2_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT2_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT2_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8100+0x30)++0x0F line.long 0x00 "PRE2,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT2_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT2_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT2_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL2,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT2_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT2_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT2_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 3" group.long 0x8180++0x0F line.long 0x00 "TARGET_ROOT3,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT3_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT3_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT3_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8180+0x10)++0x0F line.long 0x00 "MISC3,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT3_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT3_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT3_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8180+0x20)++0x0F line.long 0x00 "POST3,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT3_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT3_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT3_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8180+0x30)++0x0F line.long 0x00 "PRE3,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT3_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT3_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT3_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL3,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT3_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT3_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT3_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 4" group.long 0x8200++0x0F line.long 0x00 "TARGET_ROOT4,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT4_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT4_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT4_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8200+0x10)++0x0F line.long 0x00 "MISC4,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT4_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT4_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT4_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8200+0x20)++0x0F line.long 0x00 "POST4,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT4_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT4_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT4_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8200+0x30)++0x0F line.long 0x00 "PRE4,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT4_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT4_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT4_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL4,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT4_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT4_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT4_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 5" group.long 0x8280++0x0F line.long 0x00 "TARGET_ROOT5,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT5_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT5_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT5_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8280+0x10)++0x0F line.long 0x00 "MISC5,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT5_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT5_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT5_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8280+0x20)++0x0F line.long 0x00 "POST5,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT5_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT5_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT5_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8280+0x30)++0x0F line.long 0x00 "PRE5,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT5_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT5_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT5_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL5,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT5_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT5_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT5_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 6" group.long 0x8300++0x0F line.long 0x00 "TARGET_ROOT6,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT6_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT6_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT6_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8300+0x10)++0x0F line.long 0x00 "MISC6,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT6_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT6_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT6_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8300+0x20)++0x0F line.long 0x00 "POST6,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT6_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT6_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT6_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8300+0x30)++0x0F line.long 0x00 "PRE6,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT6_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT6_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT6_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL6,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT6_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT6_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT6_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 7" group.long 0x8380++0x0F line.long 0x00 "TARGET_ROOT7,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT7_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT7_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT7_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8380+0x10)++0x0F line.long 0x00 "MISC7,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT7_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT7_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT7_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8380+0x20)++0x0F line.long 0x00 "POST7,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT7_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT7_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT7_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8380+0x30)++0x0F line.long 0x00 "PRE7,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT7_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT7_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT7_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL7,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT7_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT7_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT7_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 8" group.long 0x8400++0x0F line.long 0x00 "TARGET_ROOT8,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT8_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT8_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT8_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8400+0x10)++0x0F line.long 0x00 "MISC8,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT8_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT8_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT8_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8400+0x20)++0x0F line.long 0x00 "POST8,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT8_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT8_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT8_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8400+0x30)++0x0F line.long 0x00 "PRE8,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT8_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT8_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT8_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL8,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT8_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT8_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT8_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 9" group.long 0x8480++0x0F line.long 0x00 "TARGET_ROOT9,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT9_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT9_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT9_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8480+0x10)++0x0F line.long 0x00 "MISC9,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT9_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT9_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT9_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8480+0x20)++0x0F line.long 0x00 "POST9,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT9_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT9_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT9_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8480+0x30)++0x0F line.long 0x00 "PRE9,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT9_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT9_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT9_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL9,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT9_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT9_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT9_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 10" group.long 0x8500++0x0F line.long 0x00 "TARGET_ROOT10,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT10_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT10_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT10_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8500+0x10)++0x0F line.long 0x00 "MISC10,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT10_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT10_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT10_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8500+0x20)++0x0F line.long 0x00 "POST10,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT10_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT10_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT10_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8500+0x30)++0x0F line.long 0x00 "PRE10,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT10_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT10_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT10_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL10,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT10_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT10_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT10_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 11" group.long 0x8580++0x0F line.long 0x00 "TARGET_ROOT11,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT11_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT11_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT11_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8580+0x10)++0x0F line.long 0x00 "MISC11,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT11_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT11_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT11_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8580+0x20)++0x0F line.long 0x00 "POST11,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT11_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT11_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT11_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8580+0x30)++0x0F line.long 0x00 "PRE11,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT11_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT11_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT11_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL11,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT11_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT11_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT11_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 12" group.long 0x8600++0x0F line.long 0x00 "TARGET_ROOT12,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT12_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT12_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT12_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8600+0x10)++0x0F line.long 0x00 "MISC12,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT12_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT12_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT12_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8600+0x20)++0x0F line.long 0x00 "POST12,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT12_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT12_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT12_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8600+0x30)++0x0F line.long 0x00 "PRE12,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT12_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT12_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT12_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL12,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT12_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT12_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT12_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 13" group.long 0x8680++0x0F line.long 0x00 "TARGET_ROOT13,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT13_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT13_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT13_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8680+0x10)++0x0F line.long 0x00 "MISC13,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT13_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT13_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT13_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8680+0x20)++0x0F line.long 0x00 "POST13,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT13_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT13_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT13_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8680+0x30)++0x0F line.long 0x00 "PRE13,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT13_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT13_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT13_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL13,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT13_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT13_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT13_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 14" group.long 0x8700++0x0F line.long 0x00 "TARGET_ROOT14,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT14_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT14_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT14_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8700+0x10)++0x0F line.long 0x00 "MISC14,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT14_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT14_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT14_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8700+0x20)++0x0F line.long 0x00 "POST14,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT14_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT14_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT14_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8700+0x30)++0x0F line.long 0x00 "PRE14,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT14_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT14_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT14_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL14,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT14_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT14_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT14_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 15" group.long 0x8780++0x0F line.long 0x00 "TARGET_ROOT15,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT15_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT15_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT15_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8780+0x10)++0x0F line.long 0x00 "MISC15,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT15_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT15_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT15_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8780+0x20)++0x0F line.long 0x00 "POST15,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT15_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT15_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT15_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8780+0x30)++0x0F line.long 0x00 "PRE15,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT15_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT15_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT15_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL15,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT15_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT15_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT15_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 16" group.long 0x8800++0x0F line.long 0x00 "TARGET_ROOT16,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT16_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT16_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT16_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8800+0x10)++0x0F line.long 0x00 "MISC16,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT16_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT16_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT16_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8800+0x20)++0x0F line.long 0x00 "POST16,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT16_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT16_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT16_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8800+0x30)++0x0F line.long 0x00 "PRE16,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT16_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT16_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT16_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL16,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT16_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT16_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT16_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 17" group.long 0x8880++0x0F line.long 0x00 "TARGET_ROOT17,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT17_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT17_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT17_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8880+0x10)++0x0F line.long 0x00 "MISC17,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT17_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT17_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT17_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8880+0x20)++0x0F line.long 0x00 "POST17,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT17_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT17_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT17_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8880+0x30)++0x0F line.long 0x00 "PRE17,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT17_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT17_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT17_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL17,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT17_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT17_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT17_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 18" group.long 0x8900++0x0F line.long 0x00 "TARGET_ROOT18,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT18_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT18_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT18_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8900+0x10)++0x0F line.long 0x00 "MISC18,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT18_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT18_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT18_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8900+0x20)++0x0F line.long 0x00 "POST18,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT18_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT18_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT18_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8900+0x30)++0x0F line.long 0x00 "PRE18,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT18_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT18_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT18_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL18,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT18_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT18_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT18_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 19" group.long 0x8980++0x0F line.long 0x00 "TARGET_ROOT19,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT19_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT19_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT19_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8980+0x10)++0x0F line.long 0x00 "MISC19,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT19_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT19_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT19_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8980+0x20)++0x0F line.long 0x00 "POST19,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT19_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT19_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT19_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8980+0x30)++0x0F line.long 0x00 "PRE19,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT19_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT19_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT19_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL19,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT19_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT19_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT19_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 20" group.long 0x8A00++0x0F line.long 0x00 "TARGET_ROOT20,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT20_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT20_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT20_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A00+0x10)++0x0F line.long 0x00 "MISC20,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT20_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT20_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT20_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8A00+0x20)++0x0F line.long 0x00 "POST20,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT20_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT20_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT20_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A00+0x30)++0x0F line.long 0x00 "PRE20,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT20_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT20_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT20_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8A00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL20,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT20_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT20_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT20_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 21" group.long 0x8A80++0x0F line.long 0x00 "TARGET_ROOT21,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT21_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT21_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT21_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A80+0x10)++0x0F line.long 0x00 "MISC21,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT21_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT21_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT21_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8A80+0x20)++0x0F line.long 0x00 "POST21,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT21_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT21_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT21_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8A80+0x30)++0x0F line.long 0x00 "PRE21,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT21_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT21_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT21_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8A80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL21,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT21_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT21_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT21_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 22" group.long 0x8B00++0x0F line.long 0x00 "TARGET_ROOT22,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT22_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT22_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT22_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B00+0x10)++0x0F line.long 0x00 "MISC22,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT22_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT22_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT22_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8B00+0x20)++0x0F line.long 0x00 "POST22,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT22_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT22_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT22_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B00+0x30)++0x0F line.long 0x00 "PRE22,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT22_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT22_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT22_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8B00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL22,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT22_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT22_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT22_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 23" group.long 0x8B80++0x0F line.long 0x00 "TARGET_ROOT23,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT23_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT23_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT23_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B80+0x10)++0x0F line.long 0x00 "MISC23,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT23_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT23_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT23_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8B80+0x20)++0x0F line.long 0x00 "POST23,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT23_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT23_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT23_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8B80+0x30)++0x0F line.long 0x00 "PRE23,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT23_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT23_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT23_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8B80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL23,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT23_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT23_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT23_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 24" group.long 0x8C00++0x0F line.long 0x00 "TARGET_ROOT24,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT24_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT24_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT24_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C00+0x10)++0x0F line.long 0x00 "MISC24,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT24_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT24_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT24_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8C00+0x20)++0x0F line.long 0x00 "POST24,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT24_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT24_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT24_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C00+0x30)++0x0F line.long 0x00 "PRE24,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT24_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT24_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT24_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8C00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL24,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT24_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT24_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT24_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 25" group.long 0x8C80++0x0F line.long 0x00 "TARGET_ROOT25,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT25_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT25_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT25_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C80+0x10)++0x0F line.long 0x00 "MISC25,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT25_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT25_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT25_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8C80+0x20)++0x0F line.long 0x00 "POST25,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT25_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT25_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT25_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8C80+0x30)++0x0F line.long 0x00 "PRE25,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT25_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT25_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT25_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8C80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL25,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT25_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT25_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT25_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 26" group.long 0x8D00++0x0F line.long 0x00 "TARGET_ROOT26,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT26_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT26_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT26_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D00+0x10)++0x0F line.long 0x00 "MISC26,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT26_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT26_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT26_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8D00+0x20)++0x0F line.long 0x00 "POST26,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT26_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT26_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT26_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D00+0x30)++0x0F line.long 0x00 "PRE26,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT26_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT26_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT26_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8D00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL26,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT26_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT26_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT26_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 27" group.long 0x8D80++0x0F line.long 0x00 "TARGET_ROOT27,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT27_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT27_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT27_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D80+0x10)++0x0F line.long 0x00 "MISC27,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT27_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT27_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT27_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8D80+0x20)++0x0F line.long 0x00 "POST27,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT27_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT27_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT27_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8D80+0x30)++0x0F line.long 0x00 "PRE27,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT27_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT27_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT27_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8D80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL27,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT27_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT27_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT27_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 28" group.long 0x8E00++0x0F line.long 0x00 "TARGET_ROOT28,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT28_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT28_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT28_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E00+0x10)++0x0F line.long 0x00 "MISC28,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT28_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT28_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT28_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8E00+0x20)++0x0F line.long 0x00 "POST28,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT28_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT28_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT28_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E00+0x30)++0x0F line.long 0x00 "PRE28,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT28_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT28_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT28_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8E00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL28,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT28_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT28_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT28_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 29" group.long 0x8E80++0x0F line.long 0x00 "TARGET_ROOT29,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT29_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT29_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT29_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E80+0x10)++0x0F line.long 0x00 "MISC29,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT29_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT29_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT29_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8E80+0x20)++0x0F line.long 0x00 "POST29,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT29_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT29_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT29_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8E80+0x30)++0x0F line.long 0x00 "PRE29,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT29_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT29_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT29_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8E80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL29,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT29_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT29_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT29_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 30" group.long 0x8F00++0x0F line.long 0x00 "TARGET_ROOT30,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT30_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT30_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT30_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F00+0x10)++0x0F line.long 0x00 "MISC30,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT30_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT30_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT30_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8F00+0x20)++0x0F line.long 0x00 "POST30,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT30_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT30_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT30_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F00+0x30)++0x0F line.long 0x00 "PRE30,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT30_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT30_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT30_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8F00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL30,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT30_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT30_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT30_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 31" group.long 0x8F80++0x0F line.long 0x00 "TARGET_ROOT31,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT31_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT31_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT31_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F80+0x10)++0x0F line.long 0x00 "MISC31,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT31_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT31_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT31_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x8F80+0x20)++0x0F line.long 0x00 "POST31,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT31_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT31_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT31_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x8F80+0x30)++0x0F line.long 0x00 "PRE31,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT31_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT31_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT31_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x8F80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL31,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT31_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT31_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT31_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 32" group.long 0x9000++0x0F line.long 0x00 "TARGET_ROOT32,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT32_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT32_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT32_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9000+0x10)++0x0F line.long 0x00 "MISC32,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT32_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT32_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT32_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9000+0x20)++0x0F line.long 0x00 "POST32,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT32_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT32_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT32_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9000+0x30)++0x0F line.long 0x00 "PRE32,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT32_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT32_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT32_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL32,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT32_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT32_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT32_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 33" group.long 0x9080++0x0F line.long 0x00 "TARGET_ROOT33,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT33_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT33_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT33_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9080+0x10)++0x0F line.long 0x00 "MISC33,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT33_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT33_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT33_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9080+0x20)++0x0F line.long 0x00 "POST33,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT33_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT33_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT33_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9080+0x30)++0x0F line.long 0x00 "PRE33,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT33_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT33_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT33_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL33,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT33_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT33_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT33_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 34" group.long 0x9100++0x0F line.long 0x00 "TARGET_ROOT34,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT34_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT34_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT34_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9100+0x10)++0x0F line.long 0x00 "MISC34,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT34_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT34_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT34_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9100+0x20)++0x0F line.long 0x00 "POST34,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT34_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT34_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT34_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9100+0x30)++0x0F line.long 0x00 "PRE34,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT34_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT34_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT34_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL34,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT34_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT34_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT34_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 35" group.long 0x9180++0x0F line.long 0x00 "TARGET_ROOT35,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT35_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT35_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT35_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9180+0x10)++0x0F line.long 0x00 "MISC35,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT35_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT35_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT35_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9180+0x20)++0x0F line.long 0x00 "POST35,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT35_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT35_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT35_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9180+0x30)++0x0F line.long 0x00 "PRE35,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT35_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT35_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT35_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL35,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT35_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT35_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT35_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 36" group.long 0x9200++0x0F line.long 0x00 "TARGET_ROOT36,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT36_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT36_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT36_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9200+0x10)++0x0F line.long 0x00 "MISC36,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT36_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT36_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT36_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9200+0x20)++0x0F line.long 0x00 "POST36,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT36_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT36_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT36_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9200+0x30)++0x0F line.long 0x00 "PRE36,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT36_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT36_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT36_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL36,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT36_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT36_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT36_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 37" group.long 0x9280++0x0F line.long 0x00 "TARGET_ROOT37,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT37_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT37_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT37_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9280+0x10)++0x0F line.long 0x00 "MISC37,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT37_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT37_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT37_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9280+0x20)++0x0F line.long 0x00 "POST37,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT37_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT37_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT37_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9280+0x30)++0x0F line.long 0x00 "PRE37,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT37_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT37_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT37_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL37,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT37_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT37_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT37_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 38" group.long 0x9300++0x0F line.long 0x00 "TARGET_ROOT38,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT38_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT38_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT38_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9300+0x10)++0x0F line.long 0x00 "MISC38,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT38_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT38_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT38_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9300+0x20)++0x0F line.long 0x00 "POST38,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT38_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT38_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT38_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9300+0x30)++0x0F line.long 0x00 "PRE38,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT38_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT38_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT38_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL38,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT38_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT38_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT38_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 39" group.long 0x9380++0x0F line.long 0x00 "TARGET_ROOT39,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT39_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT39_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT39_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9380+0x10)++0x0F line.long 0x00 "MISC39,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT39_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT39_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT39_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9380+0x20)++0x0F line.long 0x00 "POST39,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT39_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT39_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT39_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9380+0x30)++0x0F line.long 0x00 "PRE39,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT39_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT39_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT39_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL39,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT39_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT39_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT39_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 40" group.long 0x9400++0x0F line.long 0x00 "TARGET_ROOT40,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT40_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT40_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT40_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9400+0x10)++0x0F line.long 0x00 "MISC40,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT40_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT40_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT40_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9400+0x20)++0x0F line.long 0x00 "POST40,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT40_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT40_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT40_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9400+0x30)++0x0F line.long 0x00 "PRE40,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT40_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT40_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT40_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL40,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT40_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT40_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT40_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 41" group.long 0x9480++0x0F line.long 0x00 "TARGET_ROOT41,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT41_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT41_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT41_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9480+0x10)++0x0F line.long 0x00 "MISC41,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT41_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT41_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT41_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9480+0x20)++0x0F line.long 0x00 "POST41,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT41_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT41_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT41_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9480+0x30)++0x0F line.long 0x00 "PRE41,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT41_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT41_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT41_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL41,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT41_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT41_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT41_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 42" group.long 0x9500++0x0F line.long 0x00 "TARGET_ROOT42,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT42_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT42_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT42_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9500+0x10)++0x0F line.long 0x00 "MISC42,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT42_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT42_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT42_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9500+0x20)++0x0F line.long 0x00 "POST42,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT42_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT42_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT42_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9500+0x30)++0x0F line.long 0x00 "PRE42,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT42_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT42_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT42_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL42,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT42_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT42_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT42_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 43" group.long 0x9580++0x0F line.long 0x00 "TARGET_ROOT43,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT43_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT43_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT43_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9580+0x10)++0x0F line.long 0x00 "MISC43,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT43_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT43_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT43_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9580+0x20)++0x0F line.long 0x00 "POST43,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT43_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT43_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT43_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9580+0x30)++0x0F line.long 0x00 "PRE43,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT43_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT43_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT43_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL43,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT43_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT43_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT43_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 44" group.long 0x9600++0x0F line.long 0x00 "TARGET_ROOT44,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT44_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT44_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT44_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9600+0x10)++0x0F line.long 0x00 "MISC44,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT44_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT44_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT44_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9600+0x20)++0x0F line.long 0x00 "POST44,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT44_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT44_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT44_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9600+0x30)++0x0F line.long 0x00 "PRE44,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT44_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT44_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT44_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL44,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT44_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT44_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT44_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 45" group.long 0x9680++0x0F line.long 0x00 "TARGET_ROOT45,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT45_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT45_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT45_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9680+0x10)++0x0F line.long 0x00 "MISC45,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT45_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT45_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT45_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9680+0x20)++0x0F line.long 0x00 "POST45,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT45_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT45_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT45_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9680+0x30)++0x0F line.long 0x00 "PRE45,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT45_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT45_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT45_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL45,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT45_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT45_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT45_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 46" group.long 0x9700++0x0F line.long 0x00 "TARGET_ROOT46,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT46_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT46_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT46_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9700+0x10)++0x0F line.long 0x00 "MISC46,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT46_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT46_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT46_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9700+0x20)++0x0F line.long 0x00 "POST46,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT46_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT46_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT46_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9700+0x30)++0x0F line.long 0x00 "PRE46,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT46_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT46_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT46_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL46,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT46_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT46_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT46_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 47" group.long 0x9780++0x0F line.long 0x00 "TARGET_ROOT47,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT47_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT47_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT47_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9780+0x10)++0x0F line.long 0x00 "MISC47,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT47_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT47_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT47_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9780+0x20)++0x0F line.long 0x00 "POST47,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT47_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT47_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT47_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9780+0x30)++0x0F line.long 0x00 "PRE47,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT47_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT47_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT47_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL47,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT47_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT47_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT47_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 48" group.long 0x9800++0x0F line.long 0x00 "TARGET_ROOT48,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT48_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT48_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT48_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9800+0x10)++0x0F line.long 0x00 "MISC48,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT48_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT48_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT48_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9800+0x20)++0x0F line.long 0x00 "POST48,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT48_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT48_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT48_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9800+0x30)++0x0F line.long 0x00 "PRE48,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT48_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT48_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT48_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL48,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT48_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT48_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT48_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 49" group.long 0x9880++0x0F line.long 0x00 "TARGET_ROOT49,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT49_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT49_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT49_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9880+0x10)++0x0F line.long 0x00 "MISC49,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT49_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT49_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT49_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9880+0x20)++0x0F line.long 0x00 "POST49,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT49_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT49_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT49_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9880+0x30)++0x0F line.long 0x00 "PRE49,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT49_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT49_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT49_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL49,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT49_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT49_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT49_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 50" group.long 0x9900++0x0F line.long 0x00 "TARGET_ROOT50,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT50_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT50_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT50_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9900+0x10)++0x0F line.long 0x00 "MISC50,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT50_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT50_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT50_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9900+0x20)++0x0F line.long 0x00 "POST50,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT50_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT50_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT50_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9900+0x30)++0x0F line.long 0x00 "PRE50,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT50_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT50_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT50_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL50,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT50_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT50_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT50_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 51" group.long 0x9980++0x0F line.long 0x00 "TARGET_ROOT51,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT51_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT51_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT51_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9980+0x10)++0x0F line.long 0x00 "MISC51,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT51_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT51_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT51_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9980+0x20)++0x0F line.long 0x00 "POST51,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT51_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT51_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT51_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9980+0x30)++0x0F line.long 0x00 "PRE51,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT51_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT51_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT51_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL51,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT51_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT51_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT51_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 52" group.long 0x9A00++0x0F line.long 0x00 "TARGET_ROOT52,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT52_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT52_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT52_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A00+0x10)++0x0F line.long 0x00 "MISC52,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT52_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT52_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT52_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9A00+0x20)++0x0F line.long 0x00 "POST52,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT52_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT52_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT52_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A00+0x30)++0x0F line.long 0x00 "PRE52,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT52_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT52_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT52_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9A00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL52,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT52_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT52_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT52_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 53" group.long 0x9A80++0x0F line.long 0x00 "TARGET_ROOT53,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT53_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT53_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT53_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A80+0x10)++0x0F line.long 0x00 "MISC53,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT53_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT53_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT53_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9A80+0x20)++0x0F line.long 0x00 "POST53,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT53_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT53_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT53_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9A80+0x30)++0x0F line.long 0x00 "PRE53,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT53_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT53_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT53_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9A80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL53,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT53_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT53_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT53_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 54" group.long 0x9B00++0x0F line.long 0x00 "TARGET_ROOT54,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT54_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT54_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT54_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B00+0x10)++0x0F line.long 0x00 "MISC54,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT54_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT54_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT54_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9B00+0x20)++0x0F line.long 0x00 "POST54,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT54_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT54_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT54_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B00+0x30)++0x0F line.long 0x00 "PRE54,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT54_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT54_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT54_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9B00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL54,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT54_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT54_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT54_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 55" group.long 0x9B80++0x0F line.long 0x00 "TARGET_ROOT55,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT55_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT55_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT55_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B80+0x10)++0x0F line.long 0x00 "MISC55,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT55_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT55_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT55_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9B80+0x20)++0x0F line.long 0x00 "POST55,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT55_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT55_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT55_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9B80+0x30)++0x0F line.long 0x00 "PRE55,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT55_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT55_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT55_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9B80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL55,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT55_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT55_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT55_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 56" group.long 0x9C00++0x0F line.long 0x00 "TARGET_ROOT56,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT56_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT56_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT56_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C00+0x10)++0x0F line.long 0x00 "MISC56,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT56_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT56_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT56_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9C00+0x20)++0x0F line.long 0x00 "POST56,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT56_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT56_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT56_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C00+0x30)++0x0F line.long 0x00 "PRE56,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT56_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT56_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT56_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9C00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL56,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT56_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT56_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT56_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 57" group.long 0x9C80++0x0F line.long 0x00 "TARGET_ROOT57,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT57_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT57_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT57_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C80+0x10)++0x0F line.long 0x00 "MISC57,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT57_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT57_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT57_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9C80+0x20)++0x0F line.long 0x00 "POST57,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT57_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT57_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT57_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9C80+0x30)++0x0F line.long 0x00 "PRE57,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT57_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT57_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT57_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9C80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL57,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT57_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT57_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT57_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 58" group.long 0x9D00++0x0F line.long 0x00 "TARGET_ROOT58,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT58_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT58_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT58_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D00+0x10)++0x0F line.long 0x00 "MISC58,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT58_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT58_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT58_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9D00+0x20)++0x0F line.long 0x00 "POST58,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT58_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT58_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT58_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D00+0x30)++0x0F line.long 0x00 "PRE58,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT58_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT58_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT58_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9D00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL58,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT58_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT58_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT58_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 59" group.long 0x9D80++0x0F line.long 0x00 "TARGET_ROOT59,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT59_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT59_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT59_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D80+0x10)++0x0F line.long 0x00 "MISC59,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT59_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT59_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT59_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9D80+0x20)++0x0F line.long 0x00 "POST59,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT59_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT59_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT59_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9D80+0x30)++0x0F line.long 0x00 "PRE59,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT59_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT59_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT59_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9D80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL59,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT59_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT59_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT59_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 60" group.long 0x9E00++0x0F line.long 0x00 "TARGET_ROOT60,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT60_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT60_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT60_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E00+0x10)++0x0F line.long 0x00 "MISC60,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT60_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT60_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT60_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9E00+0x20)++0x0F line.long 0x00 "POST60,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT60_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT60_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT60_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E00+0x30)++0x0F line.long 0x00 "PRE60,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT60_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT60_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT60_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9E00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL60,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT60_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT60_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT60_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 61" group.long 0x9E80++0x0F line.long 0x00 "TARGET_ROOT61,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT61_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT61_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT61_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E80+0x10)++0x0F line.long 0x00 "MISC61,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT61_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT61_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT61_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9E80+0x20)++0x0F line.long 0x00 "POST61,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT61_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT61_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT61_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9E80+0x30)++0x0F line.long 0x00 "PRE61,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT61_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT61_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT61_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9E80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL61,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT61_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT61_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT61_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 62" group.long 0x9F00++0x0F line.long 0x00 "TARGET_ROOT62,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT62_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT62_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT62_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F00+0x10)++0x0F line.long 0x00 "MISC62,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT62_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT62_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT62_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9F00+0x20)++0x0F line.long 0x00 "POST62,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT62_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT62_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT62_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F00+0x30)++0x0F line.long 0x00 "PRE62,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT62_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT62_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT62_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9F00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL62,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT62_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT62_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT62_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 63" group.long 0x9F80++0x0F line.long 0x00 "TARGET_ROOT63,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT63_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT63_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT63_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F80+0x10)++0x0F line.long 0x00 "MISC63,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT63_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT63_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT63_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0x9F80+0x20)++0x0F line.long 0x00 "POST63,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT63_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT63_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT63_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0x9F80+0x30)++0x0F line.long 0x00 "PRE63,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT63_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT63_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT63_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0x9F80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL63,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT63_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT63_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT63_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 64" group.long 0xA000++0x0F line.long 0x00 "TARGET_ROOT64,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT64_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT64_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT64_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA000+0x10)++0x0F line.long 0x00 "MISC64,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT64_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT64_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT64_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA000+0x20)++0x0F line.long 0x00 "POST64,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT64_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT64_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT64_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA000+0x30)++0x0F line.long 0x00 "PRE64,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT64_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT64_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT64_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL64,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT64_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT64_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT64_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 65" group.long 0xA080++0x0F line.long 0x00 "TARGET_ROOT65,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT65_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT65_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT65_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA080+0x10)++0x0F line.long 0x00 "MISC65,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT65_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT65_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT65_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA080+0x20)++0x0F line.long 0x00 "POST65,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT65_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT65_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT65_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA080+0x30)++0x0F line.long 0x00 "PRE65,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT65_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT65_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT65_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL65,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT65_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT65_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT65_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 66" group.long 0xA100++0x0F line.long 0x00 "TARGET_ROOT66,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT66_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT66_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT66_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA100+0x10)++0x0F line.long 0x00 "MISC66,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT66_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT66_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT66_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA100+0x20)++0x0F line.long 0x00 "POST66,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT66_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT66_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT66_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA100+0x30)++0x0F line.long 0x00 "PRE66,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT66_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT66_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT66_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL66,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT66_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT66_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT66_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 67" group.long 0xA180++0x0F line.long 0x00 "TARGET_ROOT67,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT67_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT67_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT67_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA180+0x10)++0x0F line.long 0x00 "MISC67,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT67_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT67_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT67_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA180+0x20)++0x0F line.long 0x00 "POST67,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT67_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT67_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT67_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA180+0x30)++0x0F line.long 0x00 "PRE67,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT67_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT67_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT67_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL67,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT67_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT67_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT67_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 68" group.long 0xA200++0x0F line.long 0x00 "TARGET_ROOT68,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT68_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT68_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT68_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA200+0x10)++0x0F line.long 0x00 "MISC68,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT68_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT68_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT68_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA200+0x20)++0x0F line.long 0x00 "POST68,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT68_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT68_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT68_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA200+0x30)++0x0F line.long 0x00 "PRE68,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT68_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT68_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT68_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL68,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT68_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT68_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT68_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 69" group.long 0xA280++0x0F line.long 0x00 "TARGET_ROOT69,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT69_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT69_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT69_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA280+0x10)++0x0F line.long 0x00 "MISC69,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT69_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT69_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT69_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA280+0x20)++0x0F line.long 0x00 "POST69,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT69_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT69_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT69_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA280+0x30)++0x0F line.long 0x00 "PRE69,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT69_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT69_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT69_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL69,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT69_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT69_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT69_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 70" group.long 0xA300++0x0F line.long 0x00 "TARGET_ROOT70,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT70_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT70_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT70_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA300+0x10)++0x0F line.long 0x00 "MISC70,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT70_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT70_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT70_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA300+0x20)++0x0F line.long 0x00 "POST70,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT70_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT70_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT70_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA300+0x30)++0x0F line.long 0x00 "PRE70,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT70_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT70_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT70_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL70,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT70_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT70_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT70_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 71" group.long 0xA380++0x0F line.long 0x00 "TARGET_ROOT71,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT71_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT71_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT71_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA380+0x10)++0x0F line.long 0x00 "MISC71,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT71_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT71_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT71_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA380+0x20)++0x0F line.long 0x00 "POST71,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT71_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT71_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT71_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA380+0x30)++0x0F line.long 0x00 "PRE71,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT71_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT71_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT71_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL71,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT71_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT71_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT71_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 72" group.long 0xA400++0x0F line.long 0x00 "TARGET_ROOT72,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT72_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT72_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT72_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA400+0x10)++0x0F line.long 0x00 "MISC72,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT72_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT72_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT72_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA400+0x20)++0x0F line.long 0x00 "POST72,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT72_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT72_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT72_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA400+0x30)++0x0F line.long 0x00 "PRE72,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT72_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT72_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT72_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL72,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT72_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT72_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT72_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 73" group.long 0xA480++0x0F line.long 0x00 "TARGET_ROOT73,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT73_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT73_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT73_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA480+0x10)++0x0F line.long 0x00 "MISC73,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT73_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT73_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT73_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA480+0x20)++0x0F line.long 0x00 "POST73,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT73_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT73_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT73_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA480+0x30)++0x0F line.long 0x00 "PRE73,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT73_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT73_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT73_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL73,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT73_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT73_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT73_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 74" group.long 0xA500++0x0F line.long 0x00 "TARGET_ROOT74,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT74_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT74_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT74_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA500+0x10)++0x0F line.long 0x00 "MISC74,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT74_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT74_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT74_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA500+0x20)++0x0F line.long 0x00 "POST74,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT74_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT74_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT74_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA500+0x30)++0x0F line.long 0x00 "PRE74,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT74_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT74_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT74_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL74,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT74_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT74_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT74_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 75" group.long 0xA580++0x0F line.long 0x00 "TARGET_ROOT75,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT75_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT75_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT75_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA580+0x10)++0x0F line.long 0x00 "MISC75,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT75_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT75_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT75_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA580+0x20)++0x0F line.long 0x00 "POST75,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT75_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT75_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT75_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA580+0x30)++0x0F line.long 0x00 "PRE75,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT75_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT75_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT75_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL75,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT75_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT75_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT75_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 76" group.long 0xA600++0x0F line.long 0x00 "TARGET_ROOT76,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT76_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT76_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT76_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA600+0x10)++0x0F line.long 0x00 "MISC76,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT76_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT76_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT76_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA600+0x20)++0x0F line.long 0x00 "POST76,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT76_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT76_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT76_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA600+0x30)++0x0F line.long 0x00 "PRE76,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT76_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT76_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT76_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL76,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT76_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT76_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT76_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 77" group.long 0xA680++0x0F line.long 0x00 "TARGET_ROOT77,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT77_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT77_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT77_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA680+0x10)++0x0F line.long 0x00 "MISC77,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT77_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT77_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT77_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA680+0x20)++0x0F line.long 0x00 "POST77,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT77_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT77_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT77_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA680+0x30)++0x0F line.long 0x00 "PRE77,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT77_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT77_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT77_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL77,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT77_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT77_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT77_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 78" group.long 0xA700++0x0F line.long 0x00 "TARGET_ROOT78,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT78_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT78_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT78_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA700+0x10)++0x0F line.long 0x00 "MISC78,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT78_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT78_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT78_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA700+0x20)++0x0F line.long 0x00 "POST78,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT78_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT78_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT78_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA700+0x30)++0x0F line.long 0x00 "PRE78,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT78_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT78_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT78_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL78,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT78_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT78_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT78_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 79" group.long 0xA780++0x0F line.long 0x00 "TARGET_ROOT79,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT79_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT79_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT79_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA780+0x10)++0x0F line.long 0x00 "MISC79,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT79_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT79_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT79_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA780+0x20)++0x0F line.long 0x00 "POST79,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT79_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT79_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT79_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA780+0x30)++0x0F line.long 0x00 "PRE79,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT79_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT79_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT79_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL79,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT79_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT79_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT79_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 80" group.long 0xA800++0x0F line.long 0x00 "TARGET_ROOT80,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT80_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT80_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT80_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA800+0x10)++0x0F line.long 0x00 "MISC80,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT80_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT80_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT80_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA800+0x20)++0x0F line.long 0x00 "POST80,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT80_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT80_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT80_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA800+0x30)++0x0F line.long 0x00 "PRE80,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT80_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT80_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT80_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL80,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT80_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT80_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT80_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 81" group.long 0xA880++0x0F line.long 0x00 "TARGET_ROOT81,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT81_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT81_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT81_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA880+0x10)++0x0F line.long 0x00 "MISC81,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT81_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT81_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT81_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA880+0x20)++0x0F line.long 0x00 "POST81,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT81_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT81_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT81_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA880+0x30)++0x0F line.long 0x00 "PRE81,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT81_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT81_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT81_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL81,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT81_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT81_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT81_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 82" group.long 0xA900++0x0F line.long 0x00 "TARGET_ROOT82,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT82_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT82_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT82_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA900+0x10)++0x0F line.long 0x00 "MISC82,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT82_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT82_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT82_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA900+0x20)++0x0F line.long 0x00 "POST82,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT82_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT82_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT82_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA900+0x30)++0x0F line.long 0x00 "PRE82,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT82_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT82_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT82_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL82,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT82_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT82_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT82_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 83" group.long 0xA980++0x0F line.long 0x00 "TARGET_ROOT83,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT83_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT83_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT83_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA980+0x10)++0x0F line.long 0x00 "MISC83,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT83_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT83_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT83_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xA980+0x20)++0x0F line.long 0x00 "POST83,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT83_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT83_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT83_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xA980+0x30)++0x0F line.long 0x00 "PRE83,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT83_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT83_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT83_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xA980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL83,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT83_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT83_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT83_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 84" group.long 0xAA00++0x0F line.long 0x00 "TARGET_ROOT84,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT84_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT84_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT84_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA00+0x10)++0x0F line.long 0x00 "MISC84,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT84_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT84_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT84_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAA00+0x20)++0x0F line.long 0x00 "POST84,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT84_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT84_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT84_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA00+0x30)++0x0F line.long 0x00 "PRE84,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT84_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT84_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT84_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAA00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL84,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT84_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT84_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT84_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 85" group.long 0xAA80++0x0F line.long 0x00 "TARGET_ROOT85,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT85_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT85_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT85_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA80+0x10)++0x0F line.long 0x00 "MISC85,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT85_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT85_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT85_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAA80+0x20)++0x0F line.long 0x00 "POST85,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT85_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT85_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT85_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAA80+0x30)++0x0F line.long 0x00 "PRE85,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT85_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT85_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT85_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAA80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL85,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT85_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT85_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT85_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 86" group.long 0xAB00++0x0F line.long 0x00 "TARGET_ROOT86,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT86_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT86_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT86_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB00+0x10)++0x0F line.long 0x00 "MISC86,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT86_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT86_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT86_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAB00+0x20)++0x0F line.long 0x00 "POST86,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT86_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT86_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT86_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB00+0x30)++0x0F line.long 0x00 "PRE86,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT86_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT86_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT86_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAB00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL86,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT86_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT86_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT86_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 87" group.long 0xAB80++0x0F line.long 0x00 "TARGET_ROOT87,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT87_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT87_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT87_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB80+0x10)++0x0F line.long 0x00 "MISC87,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT87_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT87_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT87_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAB80+0x20)++0x0F line.long 0x00 "POST87,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT87_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT87_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT87_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAB80+0x30)++0x0F line.long 0x00 "PRE87,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT87_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT87_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT87_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAB80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL87,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT87_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT87_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT87_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 88" group.long 0xAC00++0x0F line.long 0x00 "TARGET_ROOT88,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT88_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT88_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT88_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC00+0x10)++0x0F line.long 0x00 "MISC88,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT88_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT88_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT88_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAC00+0x20)++0x0F line.long 0x00 "POST88,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT88_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT88_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT88_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC00+0x30)++0x0F line.long 0x00 "PRE88,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT88_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT88_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT88_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAC00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL88,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT88_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT88_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT88_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 89" group.long 0xAC80++0x0F line.long 0x00 "TARGET_ROOT89,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT89_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT89_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT89_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC80+0x10)++0x0F line.long 0x00 "MISC89,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT89_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT89_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT89_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAC80+0x20)++0x0F line.long 0x00 "POST89,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT89_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT89_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT89_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAC80+0x30)++0x0F line.long 0x00 "PRE89,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT89_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT89_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT89_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAC80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL89,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT89_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT89_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT89_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 90" group.long 0xAD00++0x0F line.long 0x00 "TARGET_ROOT90,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT90_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT90_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT90_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD00+0x10)++0x0F line.long 0x00 "MISC90,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT90_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT90_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT90_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAD00+0x20)++0x0F line.long 0x00 "POST90,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT90_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT90_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT90_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD00+0x30)++0x0F line.long 0x00 "PRE90,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT90_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT90_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT90_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAD00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL90,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT90_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT90_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT90_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 91" group.long 0xAD80++0x0F line.long 0x00 "TARGET_ROOT91,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT91_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT91_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT91_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD80+0x10)++0x0F line.long 0x00 "MISC91,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT91_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT91_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT91_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAD80+0x20)++0x0F line.long 0x00 "POST91,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT91_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT91_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT91_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAD80+0x30)++0x0F line.long 0x00 "PRE91,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT91_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT91_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT91_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAD80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL91,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT91_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT91_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT91_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 92" group.long 0xAE00++0x0F line.long 0x00 "TARGET_ROOT92,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT92_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT92_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT92_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE00+0x10)++0x0F line.long 0x00 "MISC92,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT92_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT92_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT92_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAE00+0x20)++0x0F line.long 0x00 "POST92,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT92_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT92_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT92_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE00+0x30)++0x0F line.long 0x00 "PRE92,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT92_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT92_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT92_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAE00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL92,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT92_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT92_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT92_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 93" group.long 0xAE80++0x0F line.long 0x00 "TARGET_ROOT93,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT93_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT93_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT93_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE80+0x10)++0x0F line.long 0x00 "MISC93,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT93_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT93_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT93_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAE80+0x20)++0x0F line.long 0x00 "POST93,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT93_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT93_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT93_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAE80+0x30)++0x0F line.long 0x00 "PRE93,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT93_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT93_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT93_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAE80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL93,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT93_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT93_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT93_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 94" group.long 0xAF00++0x0F line.long 0x00 "TARGET_ROOT94,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT94_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT94_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT94_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF00+0x10)++0x0F line.long 0x00 "MISC94,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT94_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT94_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT94_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAF00+0x20)++0x0F line.long 0x00 "POST94,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT94_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT94_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT94_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF00+0x30)++0x0F line.long 0x00 "PRE94,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT94_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT94_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT94_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAF00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL94,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT94_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT94_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT94_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 95" group.long 0xAF80++0x0F line.long 0x00 "TARGET_ROOT95,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT95_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT95_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT95_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF80+0x10)++0x0F line.long 0x00 "MISC95,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT95_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT95_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT95_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xAF80+0x20)++0x0F line.long 0x00 "POST95,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT95_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT95_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT95_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xAF80+0x30)++0x0F line.long 0x00 "PRE95,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT95_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT95_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT95_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xAF80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL95,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT95_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT95_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT95_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 96" group.long 0xB000++0x0F line.long 0x00 "TARGET_ROOT96,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT96_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT96_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT96_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB000+0x10)++0x0F line.long 0x00 "MISC96,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT96_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT96_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT96_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB000+0x20)++0x0F line.long 0x00 "POST96,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT96_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT96_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT96_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB000+0x30)++0x0F line.long 0x00 "PRE96,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT96_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT96_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT96_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB000+0x70)++0x0F line.long 0x00 "ACCESS_CTRL96,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT96_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT96_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT96_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 97" group.long 0xB080++0x0F line.long 0x00 "TARGET_ROOT97,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT97_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT97_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT97_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB080+0x10)++0x0F line.long 0x00 "MISC97,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT97_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT97_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT97_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB080+0x20)++0x0F line.long 0x00 "POST97,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT97_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT97_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT97_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB080+0x30)++0x0F line.long 0x00 "PRE97,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT97_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT97_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT97_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB080+0x70)++0x0F line.long 0x00 "ACCESS_CTRL97,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT97_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT97_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT97_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 98" group.long 0xB100++0x0F line.long 0x00 "TARGET_ROOT98,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT98_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT98_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT98_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB100+0x10)++0x0F line.long 0x00 "MISC98,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT98_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT98_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT98_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB100+0x20)++0x0F line.long 0x00 "POST98,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT98_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT98_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT98_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB100+0x30)++0x0F line.long 0x00 "PRE98,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT98_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT98_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT98_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB100+0x70)++0x0F line.long 0x00 "ACCESS_CTRL98,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT98_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT98_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT98_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 99" group.long 0xB180++0x0F line.long 0x00 "TARGET_ROOT99,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT99_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT99_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT99_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB180+0x10)++0x0F line.long 0x00 "MISC99,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT99_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT99_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT99_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB180+0x20)++0x0F line.long 0x00 "POST99,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT99_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT99_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT99_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB180+0x30)++0x0F line.long 0x00 "PRE99,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT99_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT99_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT99_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB180+0x70)++0x0F line.long 0x00 "ACCESS_CTRL99,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT99_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT99_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT99_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 100" group.long 0xB200++0x0F line.long 0x00 "TARGET_ROOT100,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT100_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT100_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT100_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB200+0x10)++0x0F line.long 0x00 "MISC100,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT100_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT100_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT100_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB200+0x20)++0x0F line.long 0x00 "POST100,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT100_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT100_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT100_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB200+0x30)++0x0F line.long 0x00 "PRE100,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT100_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT100_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT100_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB200+0x70)++0x0F line.long 0x00 "ACCESS_CTRL100,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT100_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT100_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT100_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 101" group.long 0xB280++0x0F line.long 0x00 "TARGET_ROOT101,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT101_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT101_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT101_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB280+0x10)++0x0F line.long 0x00 "MISC101,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT101_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT101_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT101_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB280+0x20)++0x0F line.long 0x00 "POST101,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT101_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT101_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT101_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB280+0x30)++0x0F line.long 0x00 "PRE101,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT101_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT101_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT101_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB280+0x70)++0x0F line.long 0x00 "ACCESS_CTRL101,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT101_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT101_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT101_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 102" group.long 0xB300++0x0F line.long 0x00 "TARGET_ROOT102,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT102_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT102_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT102_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB300+0x10)++0x0F line.long 0x00 "MISC102,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT102_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT102_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT102_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB300+0x20)++0x0F line.long 0x00 "POST102,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT102_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT102_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT102_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB300+0x30)++0x0F line.long 0x00 "PRE102,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT102_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT102_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT102_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB300+0x70)++0x0F line.long 0x00 "ACCESS_CTRL102,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT102_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT102_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT102_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 103" group.long 0xB380++0x0F line.long 0x00 "TARGET_ROOT103,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT103_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT103_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT103_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB380+0x10)++0x0F line.long 0x00 "MISC103,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT103_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT103_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT103_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB380+0x20)++0x0F line.long 0x00 "POST103,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT103_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT103_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT103_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB380+0x30)++0x0F line.long 0x00 "PRE103,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT103_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT103_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT103_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB380+0x70)++0x0F line.long 0x00 "ACCESS_CTRL103,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT103_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT103_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT103_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 104" group.long 0xB400++0x0F line.long 0x00 "TARGET_ROOT104,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT104_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT104_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT104_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB400+0x10)++0x0F line.long 0x00 "MISC104,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT104_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT104_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT104_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB400+0x20)++0x0F line.long 0x00 "POST104,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT104_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT104_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT104_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB400+0x30)++0x0F line.long 0x00 "PRE104,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT104_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT104_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT104_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB400+0x70)++0x0F line.long 0x00 "ACCESS_CTRL104,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT104_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT104_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT104_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 105" group.long 0xB480++0x0F line.long 0x00 "TARGET_ROOT105,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT105_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT105_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT105_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB480+0x10)++0x0F line.long 0x00 "MISC105,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT105_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT105_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT105_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB480+0x20)++0x0F line.long 0x00 "POST105,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT105_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT105_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT105_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB480+0x30)++0x0F line.long 0x00 "PRE105,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT105_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT105_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT105_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB480+0x70)++0x0F line.long 0x00 "ACCESS_CTRL105,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT105_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT105_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT105_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 106" group.long 0xB500++0x0F line.long 0x00 "TARGET_ROOT106,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT106_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT106_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT106_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB500+0x10)++0x0F line.long 0x00 "MISC106,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT106_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT106_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT106_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB500+0x20)++0x0F line.long 0x00 "POST106,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT106_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT106_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT106_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB500+0x30)++0x0F line.long 0x00 "PRE106,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT106_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT106_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT106_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB500+0x70)++0x0F line.long 0x00 "ACCESS_CTRL106,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT106_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT106_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT106_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 107" group.long 0xB580++0x0F line.long 0x00 "TARGET_ROOT107,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT107_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT107_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT107_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB580+0x10)++0x0F line.long 0x00 "MISC107,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT107_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT107_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT107_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB580+0x20)++0x0F line.long 0x00 "POST107,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT107_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT107_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT107_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB580+0x30)++0x0F line.long 0x00 "PRE107,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT107_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT107_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT107_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB580+0x70)++0x0F line.long 0x00 "ACCESS_CTRL107,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT107_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT107_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT107_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 108" group.long 0xB600++0x0F line.long 0x00 "TARGET_ROOT108,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT108_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT108_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT108_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB600+0x10)++0x0F line.long 0x00 "MISC108,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT108_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT108_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT108_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB600+0x20)++0x0F line.long 0x00 "POST108,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT108_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT108_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT108_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB600+0x30)++0x0F line.long 0x00 "PRE108,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT108_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT108_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT108_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB600+0x70)++0x0F line.long 0x00 "ACCESS_CTRL108,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT108_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT108_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT108_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 109" group.long 0xB680++0x0F line.long 0x00 "TARGET_ROOT109,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT109_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT109_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT109_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB680+0x10)++0x0F line.long 0x00 "MISC109,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT109_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT109_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT109_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB680+0x20)++0x0F line.long 0x00 "POST109,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT109_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT109_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT109_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB680+0x30)++0x0F line.long 0x00 "PRE109,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT109_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT109_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT109_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB680+0x70)++0x0F line.long 0x00 "ACCESS_CTRL109,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT109_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT109_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT109_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 110" group.long 0xB700++0x0F line.long 0x00 "TARGET_ROOT110,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT110_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT110_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT110_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB700+0x10)++0x0F line.long 0x00 "MISC110,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT110_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT110_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT110_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB700+0x20)++0x0F line.long 0x00 "POST110,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT110_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT110_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT110_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB700+0x30)++0x0F line.long 0x00 "PRE110,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT110_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT110_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT110_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB700+0x70)++0x0F line.long 0x00 "ACCESS_CTRL110,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT110_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT110_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT110_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 111" group.long 0xB780++0x0F line.long 0x00 "TARGET_ROOT111,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT111_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT111_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT111_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB780+0x10)++0x0F line.long 0x00 "MISC111,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT111_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT111_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT111_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB780+0x20)++0x0F line.long 0x00 "POST111,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT111_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT111_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT111_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB780+0x30)++0x0F line.long 0x00 "PRE111,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT111_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT111_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT111_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB780+0x70)++0x0F line.long 0x00 "ACCESS_CTRL111,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT111_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT111_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT111_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 112" group.long 0xB800++0x0F line.long 0x00 "TARGET_ROOT112,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT112_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT112_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT112_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB800+0x10)++0x0F line.long 0x00 "MISC112,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT112_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT112_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT112_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB800+0x20)++0x0F line.long 0x00 "POST112,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT112_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT112_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT112_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB800+0x30)++0x0F line.long 0x00 "PRE112,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT112_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT112_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT112_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB800+0x70)++0x0F line.long 0x00 "ACCESS_CTRL112,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT112_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT112_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT112_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 113" group.long 0xB880++0x0F line.long 0x00 "TARGET_ROOT113,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT113_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT113_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT113_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB880+0x10)++0x0F line.long 0x00 "MISC113,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT113_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT113_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT113_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB880+0x20)++0x0F line.long 0x00 "POST113,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT113_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT113_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT113_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB880+0x30)++0x0F line.long 0x00 "PRE113,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT113_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT113_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT113_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB880+0x70)++0x0F line.long 0x00 "ACCESS_CTRL113,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT113_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT113_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT113_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 114" group.long 0xB900++0x0F line.long 0x00 "TARGET_ROOT114,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT114_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT114_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT114_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB900+0x10)++0x0F line.long 0x00 "MISC114,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT114_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT114_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT114_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB900+0x20)++0x0F line.long 0x00 "POST114,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT114_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT114_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT114_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB900+0x30)++0x0F line.long 0x00 "PRE114,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT114_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT114_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT114_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB900+0x70)++0x0F line.long 0x00 "ACCESS_CTRL114,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT114_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT114_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT114_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 115" group.long 0xB980++0x0F line.long 0x00 "TARGET_ROOT115,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT115_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT115_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT115_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB980+0x10)++0x0F line.long 0x00 "MISC115,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT115_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT115_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT115_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xB980+0x20)++0x0F line.long 0x00 "POST115,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT115_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT115_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT115_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xB980+0x30)++0x0F line.long 0x00 "PRE115,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT115_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT115_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT115_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xB980+0x70)++0x0F line.long 0x00 "ACCESS_CTRL115,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT115_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT115_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT115_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 116" group.long 0xBA00++0x0F line.long 0x00 "TARGET_ROOT116,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT116_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT116_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT116_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA00+0x10)++0x0F line.long 0x00 "MISC116,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT116_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT116_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT116_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBA00+0x20)++0x0F line.long 0x00 "POST116,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT116_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT116_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT116_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA00+0x30)++0x0F line.long 0x00 "PRE116,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT116_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT116_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT116_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBA00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL116,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT116_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT116_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT116_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 117" group.long 0xBA80++0x0F line.long 0x00 "TARGET_ROOT117,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT117_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT117_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT117_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA80+0x10)++0x0F line.long 0x00 "MISC117,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT117_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT117_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT117_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBA80+0x20)++0x0F line.long 0x00 "POST117,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT117_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT117_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT117_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBA80+0x30)++0x0F line.long 0x00 "PRE117,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT117_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT117_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT117_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBA80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL117,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT117_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT117_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT117_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 118" group.long 0xBB00++0x0F line.long 0x00 "TARGET_ROOT118,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT118_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT118_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT118_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB00+0x10)++0x0F line.long 0x00 "MISC118,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT118_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT118_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT118_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBB00+0x20)++0x0F line.long 0x00 "POST118,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT118_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT118_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT118_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB00+0x30)++0x0F line.long 0x00 "PRE118,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT118_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT118_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT118_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBB00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL118,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT118_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT118_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT118_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 119" group.long 0xBB80++0x0F line.long 0x00 "TARGET_ROOT119,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT119_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT119_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT119_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB80+0x10)++0x0F line.long 0x00 "MISC119,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT119_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT119_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT119_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBB80+0x20)++0x0F line.long 0x00 "POST119,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT119_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT119_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT119_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBB80+0x30)++0x0F line.long 0x00 "PRE119,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT119_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT119_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT119_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBB80+0x70)++0x0F line.long 0x00 "ACCESS_CTRL119,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT119_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT119_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT119_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Clock Root 120" group.long 0xBC00++0x0F line.long 0x00 "TARGET_ROOT120,Target Register" bitfld.long 0x00 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x00 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "TARGET_ROOT120_SET,Target Set Register" bitfld.long 0x04 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x04 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "TARGET_ROOT120_CLR,Target Clear Register" bitfld.long 0x08 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x08 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "TARGET_ROOT120_TOG,Target Toggle Register" bitfld.long 0x0C 28. " ENABLE ,Enable this clock" "Off,On" bitfld.long 0x0C 24.--26. " MUX ,Selection of clock sources" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " PRE_PODF ,Pre divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC00+0x10)++0x0F line.long 0x00 "MISC120,Miscellaneous Register" bitfld.long 0x00 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x00 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x00 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x04 "MISC_ROOT120_SET,Miscellaneous Set Register" bitfld.long 0x04 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x04 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x04 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x08 "MISC_ROOT120_CLR,Miscellaneous Clear Register" bitfld.long 0x08 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x08 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x08 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" line.long 0x0C "MISC_ROOT120_TOG,Miscellaneous Toggle Register" bitfld.long 0x0C 8. " VIOLATE ,Access violation in normal interface of this clock" "No violation,Violation" bitfld.long 0x0C 4. " TIMEOUT ,Time out happened during accessing this clock" "No timeout,Timeout" bitfld.long 0x0C 0. " AUTHEN_FAIL ,Access restricted by access control of this clock" "No,Yes" group.long (0xBC00+0x20)++0x0F line.long 0x00 "POST120,Post Divider Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x00 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x00 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x00 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x00 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x04 "POST_ROOT120_SET,Post Divider Set Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x04 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x04 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x04 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x04 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x08 "POST_ROOT120_CLR,Post Divider Clear Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x08 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x08 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x08 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x08 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0C "POST_ROOT120_TOG,Post Divider Toggle Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rbitfld.long 0x0C 31. " BUSY2 ,Clock switching multiplexer is applying new setting" "Not applied,Applied" else rbitfld.long 0x0C 31. " BUSY2 ,Safe multiplexer is applying new setting" "Not applied,Applied" endif bitfld.long 0x0C 28. " SELECT ,Selection of pre clock branches" "Branch A,Branch B" rbitfld.long 0x0C 7. " BUSY1 ,Post divider is applying new set value" "Not applied,Applied" bitfld.long 0x0C 0.--5. " POST_PODF ,Post divider divide the number" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" group.long (0xBC00+0x30)++0x0F line.long 0x00 "PRE120,Pre Divider Register" rbitfld.long 0x00 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x00 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x00 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x00 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x00 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x00 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x00 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x04 "PRE_ROOT120_SET,Pre Divider Set Register" rbitfld.long 0x04 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x04 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x04 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x04 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x04 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x04 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x04 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x04 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "PRE_ROOT120_CLR,Pre Divider Clear Register" rbitfld.long 0x08 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x08 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x08 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x08 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x08 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x08 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x08 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x08 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "PRE_ROOT120_TOG,Pre Divider Toggle Register" rbitfld.long 0x0C 31. " BUSY4 ,EN_A field is applied to field" "Not applied,Applied" bitfld.long 0x0C 28. " EN_A ,Branch A clock gate control" "Shutdown,On" bitfld.long 0x0C 24.--26. " MUX_A ,Selection control of multiplexer of branch A" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 19. " BUSY3 ,Pre divider value for branch A is applied" "Not applied,Applied" newline bitfld.long 0x0C 16.--18. " PRE_PODF_A ,Pre divider divide number for branch A" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x0C 15. " BUSY1 ,EN_B is applied to field" "Not applied,Applied" bitfld.long 0x0C 12. " EN_B ,Branch B clock gate control" "Shutdown,On" bitfld.long 0x0C 8.--10. " MUX_B ,Selection control of multiplexer of branch B" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. " BUSY0 ,Pre divider value for branch a is applying" "Not applied,Applied" bitfld.long 0x0C 0.--2. " PRE_PODF_B ,Pre divider divide number for branch B" "/1,/2,/3,/4,/5,/6,/7,/8" newline group.long (0xBC00+0x70)++0x0F line.long 0x00 "ACCESS_CTRL120,Access Control Register" bitfld.long 0x00 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x00 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x00 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x00 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x00 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x00 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x00 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ACCESS_CTRL_ROOT120_SET,Access Control Set Register" bitfld.long 0x04 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x04 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x04 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x04 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x04 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x04 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x04 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ACCESS_CTRL_ROOT120_CLR,Access Control Clear Register" bitfld.long 0x08 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x08 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x08 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x08 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x08 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x08 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x08 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ACCESS_CTRL_ROOT120_TOG,Access Control Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock this clock root to use access control" "Inactive,Active" bitfld.long 0x0C 28. " SEMA_EN ,Enable internal semaphore" "Disabled,Enabled" bitfld.long 0x0C 27. " DOMAIN3_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 26. " DOMAIN2_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 25. " DOMAIN1_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" bitfld.long 0x0C 24. " DOMAIN0_WHITELIST ,White list of domains that can change setting of this clock root" "Change not possible,Change possible" newline bitfld.long 0x0C 20. " MUTEX ,Semaphore to control access" "Free,Taken" rbitfld.long 0x0C 16.--17. " OWNER_ID ,Current domain that owns semaphore" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.long 0x0C 12.--15. " DOMAIN3_INFO ,Information from domain 3 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " DOMAIN2_INFO ,Information from domain 2 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DOMAIN1_INFO ,Information from domain 1 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " DOMAIN0_INFO ,Information from domain 0 to pass to others" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end width 0x0B endif tree.end tree "CCM_ANALOG (CCM Analog)" base ad:0x30360060 width 19. group.long 0x60++0x0F line.long 0x00 "PLL_ARM,Analog ARM PLL Control Register" rbitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 20. " PLL_ARM_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 19. " PLL_SEL ,PLL_SEL" "0,1" bitfld.long 0x00 18. " LVDS_24MHZ_SEL ,LVDS_24MHZ_SEL" "0,1" textline " " bitfld.long 0x00 17. " LVDS_SEL ,LVDS_SEL" "0,1" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x00 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x00 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x00 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x00 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "PLL_ARM_SET,Analog ARM PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x04 20. " PLL_ARM_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 19. " PLL_SEL ,PLL_SEL" "0,1" bitfld.long 0x04 18. " LVDS_24MHZ_SEL ,LVDS_24MHZ_SEL" "0,1" textline " " bitfld.long 0x04 17. " LVDS_SEL ,LVDS_SEL" "0,1" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x04 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x04 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x04 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x04 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "PLL_ARM_CLR,Analog ARM PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x08 20. " PLL_ARM_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 19. " PLL_SEL ,PLL_SEL" "0,1" bitfld.long 0x08 18. " LVDS_24MHZ_SEL ,LVDS_24MHZ_SEL" "0,1" textline " " bitfld.long 0x08 17. " LVDS_SEL ,LVDS_SEL" "0,1" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x08 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x08 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x08 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x08 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "PLL_ARM_TOG,Analog ARM PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x0C 20. " PLL_ARM_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 19. " PLL_SEL ,PLL_SEL" "0,1" bitfld.long 0x0C 18. " LVDS_24MHZ_SEL ,LVDS_24MHZ_SEL" "0,1" textline " " bitfld.long 0x0C 17. " LVDS_SEL ,LVDS_SEL" "0,1" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x0C 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x0C 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x0C 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x0C 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x70++0x0F line.long 0x00 "PLL_DDR,Analog DDR PLL Control Register" rbitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 21.--22. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" bitfld.long 0x00 20. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 19. " PLL_DDR_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x00 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x00 12. " DIV2_ENABLE_CLK ,DIV2_ENABLE_CLK" "Disabled,Enabled" bitfld.long 0x00 11. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x00 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x00 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x00 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "PLL_DDR_SET,Analog DDR PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x04 21.--22. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" bitfld.long 0x04 20. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 19. " PLL_DDR_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x04 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x04 12. " DIV2_ENABLE_CLK ,DIV2_ENABLE_CLK" "Disabled,Enabled" bitfld.long 0x04 11. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x04 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x04 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x04 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "PLL_DDR_CLR,Analog DDR PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x08 21.--22. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" bitfld.long 0x08 20. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 19. " PLL_DDR_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x08 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x08 12. " DIV2_ENABLE_CLK ,DIV2_ENABLE_CLK" "Disabled,Enabled" bitfld.long 0x08 11. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x08 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x08 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x08 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "PLL_DDR_TOG,Analog DDR PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x0C 21.--22. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" bitfld.long 0x0C 20. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 19. " PLL_DDR_OVERRIDE ,The OVERRIDE bit allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x0C 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " DIV2_ENABLE_CLK ,DIV2_ENABLE_CLK" "Disabled,Enabled" bitfld.long 0x0C 11. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x0C 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x0C 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x0C 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x80++0x03 line.long 0x00 "PLL_DDR_SS,DDR PLL Spread Spectrum Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Frequency change = step/b*24mhz" bitfld.long 0x00 15. " ENABLE ,This bit enables the spread spectrum modulation" "Disabled,Enabled" hexmask.long.word 0x00 0.--14. 1. " STEP ,The max frequency change = stop/b*24mhz" group.long 0x90++0x03 line.long 0x00 "PLL_DDR_NUM,Numerator Of DDR PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator (A) of fractional loop divider (Signed integer)" group.long 0xA0++0x03 line.long 0x00 "PLL_DDR_DENOM,Denominator Of DDR PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit denominator (B) of fractional loop divider (Signed integer)" textline " " group.long 0xB0++0x0F line.long 0x00 "PLL_480,Analog 480mhz PLL Control Register" rbitfld.long 0x00 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x00 28. " PFD2_DIV2_CLKGATE ,Pll_sys_pfd2_135m_clk is off" "No,Yes" bitfld.long 0x00 27. " PFD1_DIV2_CLKGATE ,Pll_sys_pfd1_166m_clk is off" "No,Yes" bitfld.long 0x00 26. " PFD0_DIV2_CLKGATE ,Pll_sys_pfd0_196m_clk is off" "No,Yes" textline " " bitfld.long 0x00 25. " PFD7_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 24. " PFD6_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 23. " PFD5_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 22. " PFD4_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x00 21. " PFD3_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 20. " PFD2_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 19. " PFD1_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 18. " PFD0_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x00 17. " PLL_480_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x00 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x00 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x00 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x00 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" bitfld.long 0x00 6. " MAIN_DIV4_CLKGATE ,Pll_sys_main_120m_clk is off" "No,Yes" bitfld.long 0x00 5. " MAIN_DIV2_CLKGATE ,Pll_sys_main_240m_clk is off" "No,Yes" textline " " bitfld.long 0x00 4. " MAIN_DIV1_CLKGATE ,Pll_sys_main_480m_clk is off" "No,Yes" bitfld.long 0x00 0. " DIV_SELECT ,Controls the PLL loop divider" "Fout=480mhz,Fout=528mhz" line.long 0x04 "PLL_480_SET,Analog 480mhz PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x04 28. " PFD2_DIV2_CLKGATE ,Pll_sys_pfd2_135m_clk is off" "No,Yes" bitfld.long 0x04 27. " PFD1_DIV2_CLKGATE ,Pll_sys_pfd1_166m_clk is off" "No,Yes" bitfld.long 0x04 26. " PFD0_DIV2_CLKGATE ,Pll_sys_pfd0_196m_clk is off" "No,Yes" textline " " bitfld.long 0x04 25. " PFD7_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 24. " PFD6_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 23. " PFD5_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 22. " PFD4_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x04 21. " PFD3_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 20. " PFD2_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 19. " PFD1_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 18. " PFD0_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x04 17. " PLL_480_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x04 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x04 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x04 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x04 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" bitfld.long 0x04 6. " MAIN_DIV4_CLKGATE ,Pll_sys_main_120m_clk is off" "No,Yes" bitfld.long 0x04 5. " MAIN_DIV2_CLKGATE ,Pll_sys_main_240m_clk is off" "No,Yes" textline " " bitfld.long 0x04 4. " MAIN_DIV1_CLKGATE ,Pll_sys_main_480m_clk is off" "No,Yes" bitfld.long 0x04 0. " DIV_SELECT ,Controls the PLL loop divider" "Fout=480mhz,Fout=528mhz" line.long 0x08 "PLL_480_CLR,Analog 480mhz PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x08 28. " PFD2_DIV2_CLKGATE ,Pll_sys_pfd2_135m_clk is off" "No,Yes" bitfld.long 0x08 27. " PFD1_DIV2_CLKGATE ,Pll_sys_pfd1_166m_clk is off" "No,Yes" bitfld.long 0x08 26. " PFD0_DIV2_CLKGATE ,Pll_sys_pfd0_196m_clk is off" "No,Yes" textline " " bitfld.long 0x08 25. " PFD7_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 24. " PFD6_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 23. " PFD5_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 22. " PFD4_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x08 21. " PFD3_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 20. " PFD2_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 19. " PFD1_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 18. " PFD0_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x08 17. " PLL_480_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x08 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x08 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x08 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x08 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" bitfld.long 0x08 6. " MAIN_DIV4_CLKGATE ,Pll_sys_main_120m_clk is off" "No,Yes" bitfld.long 0x08 5. " MAIN_DIV2_CLKGATE ,Pll_sys_main_240m_clk is off" "No,Yes" textline " " bitfld.long 0x08 4. " MAIN_DIV1_CLKGATE ,Pll_sys_main_480m_clk is off" "No,Yes" bitfld.long 0x08 0. " DIV_SELECT ,Controls the PLL loop divider" "Fout=480mhz,Fout=528mhz" line.long 0x0C "PLL_480_TOG,Analog 480mhz PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x0C 28. " PFD2_DIV2_CLKGATE ,Pll_sys_pfd2_135m_clk is off" "No,Yes" bitfld.long 0x0C 27. " PFD1_DIV2_CLKGATE ,Pll_sys_pfd1_166m_clk is off" "No,Yes" bitfld.long 0x0C 26. " PFD0_DIV2_CLKGATE ,Pll_sys_pfd0_196m_clk is off" "No,Yes" textline " " bitfld.long 0x0C 25. " PFD7_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 24. " PFD6_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 23. " PFD5_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 22. " PFD4_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x0C 21. " PFD3_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 20. " PFD2_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 19. " PFD1_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 18. " PFD0_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" textline " " bitfld.long 0x0C 17. " PLL_480_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x0C 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x0C 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" bitfld.long 0x0C 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" textline " " bitfld.long 0x0C 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" bitfld.long 0x0C 6. " MAIN_DIV4_CLKGATE ,Pll_sys_main_120m_clk is off" "No,Yes" bitfld.long 0x0C 5. " MAIN_DIV2_CLKGATE ,Pll_sys_main_240m_clk is off" "No,Yes" textline " " bitfld.long 0x0C 4. " MAIN_DIV1_CLKGATE ,Pll_sys_main_480m_clk is off" "No,Yes" bitfld.long 0x0C 0. " DIV_SELECT ,Controls the PLL loop divider" "Fout=480mhz,Fout=528mhz" textline " " group.long 0xC0++0x0F line.long 0x00 "PFD_480A,480mhz Clock Phase Fractional Divider Control Register A" bitfld.long 0x00 31. " PFD3_DIV1_CLKGATE ,IO clock gate. The PFD3 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 30. " PFD3_STABLE ,PFD3_STABLE" "Not stable,Stable" bitfld.long 0x00 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 23. " PFD2_DIV1_CLKGATE ,IO clock gate. The PFD2 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 22. " PFD2_STABLE ,PFD2_STABLE" "Not stable,Stable" bitfld.long 0x00 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 15. " PFD1_DIV1_CLKGATE ,IO clock gate. The PFD1 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 14. " PFD1_STABLE ,PFD1_STABLE" "Not stable,Stable" bitfld.long 0x00 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 7. " PFD0_DIV1_CLKGATE ,IO clock gate. The PFD0 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 6. " PFD0_STABLE ,PFD0_STABLE" "Not stable,Stable" bitfld.long 0x00 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x04 "PFD_480A_SET,480mhz Clock Phase Fractional Divider Control Set Register A" bitfld.long 0x04 31. " PFD3_DIV1_CLKGATE ,IO clock gate. The PFD3 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 30. " PFD3_STABLE ,PFD3_STABLE" "Not stable,Stable" bitfld.long 0x04 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 23. " PFD2_DIV1_CLKGATE ,IO clock gate. The PFD2 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 22. " PFD2_STABLE ,PFD2_STABLE" "Not stable,Stable" bitfld.long 0x04 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 15. " PFD1_DIV1_CLKGATE ,IO clock gate. The PFD1 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 14. " PFD1_STABLE ,PFD1_STABLE" "Not stable,Stable" bitfld.long 0x04 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 7. " PFD0_DIV1_CLKGATE ,IO clock gate. The PFD0 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 6. " PFD0_STABLE ,PFD0_STABLE" "Not stable,Stable" bitfld.long 0x04 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x08 "PFD_480A_CLR,480mhz Clock Phase Fractional Divider Control Clear Register A" bitfld.long 0x08 31. " PFD3_DIV1_CLKGATE ,IO clock gate. The PFD3 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 30. " PFD3_STABLE ,PFD3_STABLE" "Not stable,Stable" bitfld.long 0x08 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 23. " PFD2_DIV1_CLKGATE ,IO clock gate. The PFD2 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 22. " PFD2_STABLE ,PFD2_STABLE" "Not stable,Stable" bitfld.long 0x08 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 15. " PFD1_DIV1_CLKGATE ,IO clock gate. The PFD1 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 14. " PFD1_STABLE ,PFD1_STABLE" "Not stable,Stable" bitfld.long 0x08 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 7. " PFD0_DIV1_CLKGATE ,IO clock gate. The PFD0 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 6. " PFD0_STABLE ,PFD0_STABLE" "Not stable,Stable" bitfld.long 0x08 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x0C "PFD_480A_TOG,480mhz Clock Phase Fractional Divider Control Toggle Register A" bitfld.long 0x0C 31. " PFD3_DIV1_CLKGATE ,IO clock gate. The PFD3 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 30. " PFD3_STABLE ,PFD3_STABLE" "Not stable,Stable" bitfld.long 0x0C 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 23. " PFD2_DIV1_CLKGATE ,IO clock gate. The PFD2 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 22. " PFD2_STABLE ,PFD2_STABLE" "Not stable,Stable" bitfld.long 0x0C 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 15. " PFD1_DIV1_CLKGATE ,IO clock gate. The PFD1 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 14. " PFD1_STABLE ,PFD1_STABLE" "Not stable,Stable" bitfld.long 0x0C 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 7. " PFD0_DIV1_CLKGATE ,IO clock gate. The PFD0 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 6. " PFD0_STABLE ,PFD0_STABLE" "Not stable,Stable" bitfld.long 0x0C 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" group.long 0xD0++0x0F line.long 0x00 "PFD_480B,480mhz Clock Phase Fractional Divider Control Register B" bitfld.long 0x00 31. " PFD7_DIV1_CLKGATE ,IO clock gate. The PFD7 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 30. " PFD7_STABLE ,PFD7_STABLE" "Not stable,Stable" bitfld.long 0x00 24.--29. " PFD7_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 23. " PFD6_DIV1_CLKGATE ,IO clock gate. The PFD6 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 22. " PFD6_STABLE ,PFD6_STABLE" "Not stable,Stable" bitfld.long 0x00 16.--21. " PFD6_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 15. " PFD5_DIV1_CLKGATE ,IO clock gate. The PFD5 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 14. " PFD5_STABLE ,PFD5_STABLE" "Not stable,Stable" bitfld.long 0x00 8.--13. " PFD5_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x00 7. " PFD4_DIV1_CLKGATE ,IO clock gate. The PFD4 fractional divider clock is off" "No,Yes" rbitfld.long 0x00 6. " PFD4_STABLE ,PFD4_STABLE" "Not stable,Stable" bitfld.long 0x00 0.--5. " PFD4_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x04 "PFD_480B_SET,480mhz Clock Phase Fractional Divider Control Set Register B" bitfld.long 0x04 31. " PFD7_DIV1_CLKGATE ,IO clock gate. The PFD7 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 30. " PFD7_STABLE ,PFD7_STABLE" "Not stable,Stable" bitfld.long 0x04 24.--29. " PFD7_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 23. " PFD6_DIV1_CLKGATE ,IO clock gate. The PFD6 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 22. " PFD6_STABLE ,PFD6_STABLE" "Not stable,Stable" bitfld.long 0x04 16.--21. " PFD6_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 15. " PFD5_DIV1_CLKGATE ,IO clock gate. The PFD5 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 14. " PFD5_STABLE ,PFD5_STABLE" "Not stable,Stable" bitfld.long 0x04 8.--13. " PFD5_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x04 7. " PFD4_DIV1_CLKGATE ,IO clock gate. The PFD4 fractional divider clock is off" "No,Yes" rbitfld.long 0x04 6. " PFD4_STABLE ,PFD4_STABLE" "Not stable,Stable" bitfld.long 0x04 0.--5. " PFD4_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x08 "PFD_480B_CLR,480mhz Clock Phase Fractional Divider Control Clear Register B" bitfld.long 0x08 31. " PFD7_DIV1_CLKGATE ,IO clock gate. The PFD7 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 30. " PFD7_STABLE ,PFD7_STABLE" "Not stable,Stable" bitfld.long 0x08 24.--29. " PFD7_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 23. " PFD6_DIV1_CLKGATE ,IO clock gate. The PFD6 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 22. " PFD6_STABLE ,PFD6_STABLE" "Not stable,Stable" bitfld.long 0x08 16.--21. " PFD6_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 15. " PFD5_DIV1_CLKGATE ,IO clock gate. The PFD5 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 14. " PFD5_STABLE ,PFD5_STABLE" "Not stable,Stable" bitfld.long 0x08 8.--13. " PFD5_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x08 7. " PFD4_DIV1_CLKGATE ,IO clock gate. The PFD4 fractional divider clock is off" "No,Yes" rbitfld.long 0x08 6. " PFD4_STABLE ,PFD4_STABLE" "Not stable,Stable" bitfld.long 0x08 0.--5. " PFD4_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" line.long 0x0C "PFD_480B_TOG,480mhz Clock Phase Fractional Divider Control Toggle Register B" bitfld.long 0x0C 31. " PFD7_DIV1_CLKGATE ,IO clock gate. The PFD7 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 30. " PFD7_STABLE ,PFD7_STABLE" "Not stable,Stable" bitfld.long 0x0C 24.--29. " PFD7_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 23. " PFD6_DIV1_CLKGATE ,IO clock gate. The PFD6 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 22. " PFD6_STABLE ,PFD6_STABLE" "Not stable,Stable" bitfld.long 0x0C 16.--21. " PFD6_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 15. " PFD5_DIV1_CLKGATE ,IO clock gate. The PFD5 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 14. " PFD5_STABLE ,PFD5_STABLE" "Not stable,Stable" bitfld.long 0x0C 8.--13. " PFD5_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" textline " " bitfld.long 0x0C 7. " PFD4_DIV1_CLKGATE ,IO clock gate. The PFD4 fractional divider clock is off" "No,Yes" rbitfld.long 0x0C 6. " PFD4_STABLE ,PFD4_STABLE" "Not stable,Stable" bitfld.long 0x0C 0.--5. " PFD4_FRAC ,This field controls the fractional divide value" "12.359375,12.71875,13.078125,13.4375,13.796875,14.15625,14.515625,14.875,15.234375,15.59375,15.953125,16.3125,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,275,28,29,30,31,32,33,34,35,25.296875,25.65625,26.015625,26.375,26.734375,27.09375,27.453125,27.8125,28.171875,28.53125,28.890625,29.25,29.609375,29.96875,30.328125,30.6875,31.046875,31.40625,31.765625,32.125,32.484375,32.84375,33.203125,33.5625,33.921875,34.28125,34.640625,35" group.long 0xE0++0x0F line.long 0x00 "PLL_ENET,Analog ENET PLL Control Register" rbitfld.long 0x00 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x00 13. " PLL_ENET_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 12. " ENABLE_CLK_500MHZ ,Enables the ethernet 500mhz clock output" "Disabled,Enabled" bitfld.long 0x00 11. " ENABLE_CLK_250MHZ ,Enables the ethernet 250mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ENABLE_CLK_125MHZ ,Enables the ethernet 125mhz clock output" "Disabled,Enabled" bitfld.long 0x00 9. " ENABLE_CLK_100MHZ ,Enables the ethernet 100mhz clock output" "Disabled,Enabled" bitfld.long 0x00 8. " ENABLE_CLK_50MHZ ,Enables the ethernet 50mhz clock output" "Disabled,Enabled" bitfld.long 0x00 7. " ENABLE_CLK_40MHZ ,Enables the ethernet 40mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " ENABLE_CLK_25MHZ ,Enables the ethernet 25mhz clock output" "Disabled,Enabled" bitfld.long 0x00 5. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 4. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x00 3. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x00 2. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x00 1. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 0. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" line.long 0x04 "PLL_ENET_SET,Analog ENET PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" textline " " bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x04 13. " PLL_ENET_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 12. " ENABLE_CLK_500MHZ ,Enables the ethernet 500mhz clock output" "Disabled,Enabled" bitfld.long 0x04 11. " ENABLE_CLK_250MHZ ,Enables the ethernet 250mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " ENABLE_CLK_125MHZ ,Enables the ethernet 125mhz clock output" "Disabled,Enabled" bitfld.long 0x04 9. " ENABLE_CLK_100MHZ ,Enables the ethernet 100mhz clock output" "Disabled,Enabled" bitfld.long 0x04 8. " ENABLE_CLK_50MHZ ,Enables the ethernet 50mhz clock output" "Disabled,Enabled" bitfld.long 0x04 7. " ENABLE_CLK_40MHZ ,Enables the ethernet 40mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " ENABLE_CLK_25MHZ ,Enables the ethernet 25mhz clock output" "Disabled,Enabled" bitfld.long 0x04 5. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 4. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x04 3. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x04 2. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x04 1. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 0. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" line.long 0x08 "PLL_ENET_CLR,Analog ENET PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" textline " " bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x08 13. " PLL_ENET_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 12. " ENABLE_CLK_500MHZ ,Enables the ethernet 500mhz clock output" "Disabled,Enabled" bitfld.long 0x08 11. " ENABLE_CLK_250MHZ ,Enables the ethernet 250mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x08 10. " ENABLE_CLK_125MHZ ,Enables the ethernet 125mhz clock output" "Disabled,Enabled" bitfld.long 0x08 9. " ENABLE_CLK_100MHZ ,Enables the ethernet 100mhz clock output" "Disabled,Enabled" bitfld.long 0x08 8. " ENABLE_CLK_50MHZ ,Enables the ethernet 50mhz clock output" "Disabled,Enabled" bitfld.long 0x08 7. " ENABLE_CLK_40MHZ ,Enables the ethernet 40mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " ENABLE_CLK_25MHZ ,Enables the ethernet 25mhz clock output" "Disabled,Enabled" bitfld.long 0x08 5. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 4. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x08 3. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x08 2. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x08 1. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 0. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" line.long 0x0C "PLL_ENET_TOG,Analog ENET PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" textline " " bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" bitfld.long 0x0C 13. " PLL_ENET_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 12. " ENABLE_CLK_500MHZ ,Enables the ethernet 500mhz clock output" "Disabled,Enabled" bitfld.long 0x0C 11. " ENABLE_CLK_250MHZ ,Enables the ethernet 250mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " ENABLE_CLK_125MHZ ,Enables the ethernet 125mhz clock output" "Disabled,Enabled" bitfld.long 0x0C 9. " ENABLE_CLK_100MHZ ,Enables the ethernet 100mhz clock output" "Disabled,Enabled" bitfld.long 0x0C 8. " ENABLE_CLK_50MHZ ,Enables the ethernet 50mhz clock output" "Disabled,Enabled" bitfld.long 0x0C 7. " ENABLE_CLK_40MHZ ,Enables the ethernet 40mhz clock output" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " ENABLE_CLK_25MHZ ,Enables the ethernet 25mhz clock output" "Disabled,Enabled" bitfld.long 0x0C 5. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 4. " HOLD_RING_OFF ,Status of ana_irq2 input from analog block" "Not held off,Held off" bitfld.long 0x0C 3. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x0C 2. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x0C 1. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 0. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" group.long 0xF0++0x0F line.long 0x00 "PLL_AUDIO,Analog Audio PLL Control Register" rbitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x00 24. " PLL_AUDIO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x00 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x00 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x00 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x00 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x00 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "PLL_AUDIO_SET,Analog Audio PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x04 24. " PLL_AUDIO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x04 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x04 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x04 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x04 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x04 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "PLL_AUDIO_CLR,Analog Audio PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x08 24. " PLL_AUDIO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x08 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x08 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x08 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x08 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x08 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "PLL_AUDIO_TOG,Analog Audio PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,Lock" "Unlocked,Locked" bitfld.long 0x0C 24. " PLL_AUDIO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x0C 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x0C 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x0C 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x0C 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x0C 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x100++0x03 line.long 0x00 "PLL_AUDIO_SS,Audio PLL Spread Spectrum Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Frequency change = step/b*24mhz" bitfld.long 0x00 15. " ENABLE ,Enables the spread spectrum modulation" "Disabled,Enabled" hexmask.long.word 0x00 0.--14. 1. " STEP ,The max frequency change = stop/b*24mhz" group.long 0x110++0x03 line.long 0x00 "PLL_AUDIO_NUM,Numerator Of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator of fractional loop divider" group.long 0x120++0x03 line.long 0x00 "PLL_AUDIO_DENOM,Denominator Of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit denominator of fractional loop divider" group.long 0x130++0x0F line.long 0x00 "PLL_VIDEO,Analog Video PLL Control Register" rbitfld.long 0x00 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x00 24. " PLL_VIDEO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x00 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x00 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x00 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x00 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x00 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x00 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x00 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x00 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "PLL_VIDEO_SET,Analog Video PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x04 24. " PLL_VIDEO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x04 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x04 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x04 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x04 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x04 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x04 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x04 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x04 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "PLL_VIDEO_CLR,Analog Video PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x08 24. " PLL_VIDEO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x08 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x08 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x08 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x08 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x08 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x08 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x08 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x08 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "PLL_VIDEO_TOG,Analog Video PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,LOCK" "Unlocked,Locked" bitfld.long 0x0C 24. " PLL_VIDEO_OVERRIDE ,Allows the clock control module to automatically override portions of the register" "Not allowed,Allowed" bitfld.long 0x0C 22.--23. " POST_DIV_SEL ,Post-divider for audio PLL:" "/1,/2,/1,/4" bitfld.long 0x0C 19.--20. " TEST_DIV_SELECT ,Control bits for the post divider for the PLL clk" "/4,/2,/1,/1" textline " " bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 17. " DITHER_ENABLE ,Enables dither in the fractional modulator calculation" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Not bypassed,Bypassed" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "0,1,2,3" textline " " bitfld.long 0x0C 13. " ENABLE_CLK ,Enable the clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Not powered down,Powered down" bitfld.long 0x0C 11. " HOLD_RING_OFF ,Analog debug bit" "Not held off,Held off" bitfld.long 0x0C 10. " DOUBLE_CP ,Increases the charge pump gain 2x" "Not doubled,Doubled" textline " " bitfld.long 0x0C 9. " HALF_CP ,Reduces the charge pump gain 2x" "Not reduced,Reduced" bitfld.long 0x0C 8. " DOUBLE_LF ,Increases the frequency of the loop filter 2x" "Not doubled,Doubled" bitfld.long 0x0C 7. " HALF_LF ,Reduces the frequency of the loop filter 2x" "Not reduced,Reduced" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x140++0x03 line.long 0x00 "PLL_VIDEO_SS,Video PLL Spread Spectrum Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Frequency change = step/b*24mhz" bitfld.long 0x00 15. " ENABLE ,Enables the spread spectrum modulation" "Disabled,Enabled" hexmask.long.word 0x00 0.--14. 1. " STEP ,The max frequency change = stop/b*24mhz" group.long 0x150++0x03 line.long 0x00 "PLL_VIDEO_NUM,Numerator Of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator of fractional loop divider" group.long 0x160++0x03 line.long 0x00 "PLL_VIDEO_DENOM,Denominator Of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit denominator of fractional loop divider" group.long 0x170++0x0F line.long 0x00 "CLK_MISC0,Miscellaneous0 Analog Clock Control And Status Register" bitfld.long 0x00 7. " ACLK2_PREDIV ,Predivider ACLK2 source/reference clock of the pll's" "/1,/2" bitfld.long 0x00 6. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x00 5. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x00 0.--4. " LVDS1_CLK_SEL ,Selects the clock to be routed to anaclk1/1b" "Arm PLL,480 PLL,Pfd0,Pfd1,Pfd2,Pfd3,Pfd4,Pfd5,Pfd6,Pfd7,Audio PLL,Video PLL,Pll_enet_div2 (500mhz),Pll_enet_div4 (250mhz),Pll_enet_div8 (125mhz),Pll_enet_div10 (100mhz),Pll_enet_div20 (50mhz),Pll_enet_div25 (40mhz),Pll_enet_div40 (25mhz),Pll_ddr,RC_OSC24,Clk24mhz,Anatest ring oscillators,Aclk2_loopback,?..." line.long 0x04 "CLK_MISC0_SET,Miscellaneous0 Analog Clock Control And Status Set Register" bitfld.long 0x04 7. " ACLK2_PREDIV ,Predivider ACLK2 source/reference clock of the pll's" "/1,/2" bitfld.long 0x04 6. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x04 5. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x04 0.--4. " LVDS1_CLK_SEL ,Selects the clock to be routed to anaclk1/1b" "Arm PLL,480 PLL,Pfd0,Pfd1,Pfd2,Pfd3,Pfd4,Pfd5,Pfd6,Pfd7,Audio PLL,Video PLL,Pll_enet_div2 (500mhz),Pll_enet_div4 (250mhz),Pll_enet_div8 (125mhz),Pll_enet_div10 (100mhz),Pll_enet_div20 (50mhz),Pll_enet_div25 (40mhz),Pll_enet_div40 (25mhz),Pll_ddr,RC_OSC24,Clk24mhz,Anatest ring oscillators,Aclk2_loopback,?..." line.long 0x08 "CLK_MISC0_CLR,Miscellaneous0 Analog Clock Control And Status Clear Register" bitfld.long 0x08 7. " ACLK2_PREDIV ,Predivider ACLK2 source/reference clock of the pll's" "/1,/2" bitfld.long 0x08 6. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x08 5. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x08 0.--4. " LVDS1_CLK_SEL ,Selects the clock to be routed to anaclk1/1b" "Arm PLL,480 PLL,Pfd0,Pfd1,Pfd2,Pfd3,Pfd4,Pfd5,Pfd6,Pfd7,Audio PLL,Video PLL,Pll_enet_div2 (500mhz),Pll_enet_div4 (250mhz),Pll_enet_div8 (125mhz),Pll_enet_div10 (100mhz),Pll_enet_div20 (50mhz),Pll_enet_div25 (40mhz),Pll_enet_div40 (25mhz),Pll_ddr,RC_OSC24,Clk24mhz,Anatest ring oscillators,Aclk2_loopback,?..." line.long 0x0C "CLK_MISC0_TOG,Miscellaneous0 Analog Clock Control And Status Toggle Register" bitfld.long 0x0C 7. " ACLK2_PREDIV ,Predivider ACLK2 source/reference clock of the pll's" "/1,/2" bitfld.long 0x0C 6. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x0C 5. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x0C 0.--4. " LVDS1_CLK_SEL ,Selects the clock to be routed to anaclk1/1b" "Arm PLL,480 PLL,Pfd0,Pfd1,Pfd2,Pfd3,Pfd4,Pfd5,Pfd6,Pfd7,Audio PLL,Video PLL,Pll_enet_div2 (500mhz),Pll_enet_div4 (250mhz),Pll_enet_div8 (125mhz),Pll_enet_div10 (100mhz),Pll_enet_div20 (50mhz),Pll_enet_div25 (40mhz),Pll_enet_div40 (25mhz),Pll_ddr,RC_OSC24,Clk24mhz,Anatest ring oscillators,Aclk2_loopback,?..." width 0x0B tree.end tree.end tree "XTALOSC (Crystal Oscillator)" base ad:0x30360000 width 21. group.long 0x00++0x3F line.long 0x00 "CTRL_24M,Anadig 24M Oscillator Control Register" hexmask.long.word 0x00 15.--30. 1. " XTAL_MISC ,Misc control bits for 24m XTAL osc" bitfld.long 0x00 13. " RC_OSC_EN ,RC oscillator enable control" "Disabled,Enabled" bitfld.long 0x00 12. " OSC_SEL ,Selects the source for the 24mhz clock" "XTAL oscillator,RC oscillator" rbitfld.long 0x00 11. " XTALOSC_PWRUP_STAT ,Status of the 24mhz XTAL oscillator" "Not stable,Stable" textline " " bitfld.long 0x00 9.--10. " XTALOSC_PWRUP_DELAY ,Specifies the time delay between when the 24mhz XTAL is powered up until it is stable and ready to use" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x00 8. " RCOSC_CG_OVERRIDE ,Clock gate override" "No override,Override" bitfld.long 0x00 5.--7. " CLKGATE_DELAY ,Delay between powering up the XTAL 24mhz clock and release the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x00 4. " CLKGATE_CTRL ,Disabling the clock gate for the XTAL 24mhz clock" "No,Yes" textline " " bitfld.long 0x00 3. " OSC_XTALOK_EN ,Enable the xtalok detection circuitry" "Disabled,Enabled" rbitfld.long 0x00 2. " OSC_XTALOK ,Status bit which signals that the output of the 24mhz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x00 1. " XTAL_24M_EN ,Controls the clock gate at the output of the oscillator" "Disabled,Enabled" bitfld.long 0x00 0. " XTAL_24M_PWD ,Powers down the 24M crystal oscillator" "Not powered-down,Powered-down" line.long 0x04 "CTRL_24M_SET,Anadig 24M Oscillator Control Set Register" hexmask.long.word 0x04 15.--30. 1. " XTAL_MISC ,Misc control bits for 24m XTAL osc" bitfld.long 0x04 13. " RC_OSC_EN ,RC oscillator enable control" "Disabled,Enabled" bitfld.long 0x04 12. " OSC_SEL ,Selects the source for the 24mhz clock" "XTAL oscillator,RC oscillator" rbitfld.long 0x04 11. " XTALOSC_PWRUP_STAT ,Status of the 24mhz XTAL oscillator" "Not stable,Stable" textline " " bitfld.long 0x04 9.--10. " XTALOSC_PWRUP_DELAY ,Specifies the time delay between when the 24mhz XTAL is powered up until it is stable and ready to use" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x04 8. " RCOSC_CG_OVERRIDE ,Clock gate override" "No override,Override" bitfld.long 0x04 5.--7. " CLKGATE_DELAY ,Delay between powering up the XTAL 24mhz clock and release the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x04 4. " CLKGATE_CTRL ,Disabling the clock gate for the XTAL 24mhz clock" "No,Yes" textline " " bitfld.long 0x04 3. " OSC_XTALOK_EN ,Enable the xtalok detection circuitry" "Disabled,Enabled" rbitfld.long 0x04 2. " OSC_XTALOK ,Status bit which signals that the output of the 24mhz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x04 1. " XTAL_24M_EN ,Controls the clock gate at the output of the oscillator" "Disabled,Enabled" bitfld.long 0x04 0. " XTAL_24M_PWD ,Powers down the 24M crystal oscillator" "Not powered-down,Powered-down" line.long 0x08 "CTRL_24M_CLR,Anadig 24M Oscillator Control Clear Register" hexmask.long.word 0x08 15.--30. 1. " XTAL_MISC ,Misc control bits for 24m XTAL osc" bitfld.long 0x08 13. " RC_OSC_EN ,RC oscillator enable control" "Disabled,Enabled" bitfld.long 0x08 12. " OSC_SEL ,Selects the source for the 24mhz clock" "XTAL oscillator,RC oscillator" rbitfld.long 0x08 11. " XTALOSC_PWRUP_STAT ,Status of the 24mhz XTAL oscillator" "Not stable,Stable" textline " " bitfld.long 0x08 9.--10. " XTALOSC_PWRUP_DELAY ,Specifies the time delay between when the 24mhz XTAL is powered up until it is stable and ready to use" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x08 8. " RCOSC_CG_OVERRIDE ,Clock gate override" "No override,Override" bitfld.long 0x08 5.--7. " CLKGATE_DELAY ,Delay between powering up the XTAL 24mhz clock and release the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x08 4. " CLKGATE_CTRL ,Disabling the clock gate for the XTAL 24mhz clock" "No,Yes" textline " " bitfld.long 0x08 3. " OSC_XTALOK_EN ,Enable the xtalok detection circuitry" "Disabled,Enabled" rbitfld.long 0x08 2. " OSC_XTALOK ,Status bit which signals that the output of the 24mhz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x08 1. " XTAL_24M_EN ,Controls the clock gate at the output of the oscillator" "Disabled,Enabled" bitfld.long 0x08 0. " XTAL_24M_PWD ,Powers down the 24M crystal oscillator" "Not powered-down,Powered-down" line.long 0x0C "CTRL_24M_TOG,Anadig 24M Oscillator Control Toggle Register" hexmask.long.word 0x0C 15.--30. 1. " XTAL_MISC ,Misc control bits for 24m XTAL osc" bitfld.long 0x0C 13. " RC_OSC_EN ,RC oscillator enable control" "Disabled,Enabled" bitfld.long 0x0C 12. " OSC_SEL ,Selects the source for the 24mhz clock" "XTAL oscillator,RC oscillator" rbitfld.long 0x0C 11. " XTALOSC_PWRUP_STAT ,Status of the 24mhz XTAL oscillator" "Not stable,Stable" textline " " bitfld.long 0x0C 9.--10. " XTALOSC_PWRUP_DELAY ,Specifies the time delay between when the 24mhz XTAL is powered up until it is stable and ready to use" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x0C 8. " RCOSC_CG_OVERRIDE ,Clock gate override" "No override,Override" bitfld.long 0x0C 5.--7. " CLKGATE_DELAY ,Delay between powering up the XTAL 24mhz clock and release the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x0C 4. " CLKGATE_CTRL ,Disabling the clock gate for the XTAL 24mhz clock" "No,Yes" textline " " bitfld.long 0x0C 3. " OSC_XTALOK_EN ,Enable the xtalok detection circuitry" "Disabled,Enabled" rbitfld.long 0x0C 2. " OSC_XTALOK ,Status bit which signals that the output of the 24mhz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x0C 1. " XTAL_24M_EN ,Controls the clock gate at the output of the oscillator" "Disabled,Enabled" bitfld.long 0x0C 0. " XTAL_24M_PWD ,Powers down the 24M crystal oscillator" "Not powered-down,Powered-down" line.long 0x10 "RCOSC_CONFIG0,Anadig 24mhz RC Oscillator Config0 Register" hexmask.long.byte 0x10 24.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x10 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x10 4.--11. 1. " RC_OSC_PROG ,RC oscillator tuning values" textline " " bitfld.long 0x10 3. " TUNE_INVERT ,Inverts the stepping of the calculated RC tuning value" "Not inverted,Inverted" bitfld.long 0x10 2. " TUNE_BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "Not bypassed,Bypassed" bitfld.long 0x10 1. " TUNE_ENABLE ,Enables the tuning logic to calculate new RC tuning values" "Disabled,Enabled" bitfld.long 0x10 0. " TUNE_START ,Starts/stops the RC tuning calculation logic" "Stopped,Started" line.long 0x14 "RCOSC_CONFIG0_SET,Anadig 24mhz RC Oscillator Config0 Set Register" hexmask.long.byte 0x14 24.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x14 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x14 4.--11. 1. " RC_OSC_PROG ,RC oscillator tuning values" textline " " bitfld.long 0x14 3. " TUNE_INVERT ,Inverts the stepping of the calculated RC tuning value" "Not inverted,Inverted" bitfld.long 0x14 2. " TUNE_BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "Not bypassed,Bypassed" bitfld.long 0x14 1. " TUNE_ENABLE ,Enables the tuning logic to calculate new RC tuning values" "Disabled,Enabled" bitfld.long 0x14 0. " TUNE_START ,Starts/stops the RC tuning calculation logic" "Stopped,Started" line.long 0x18 "RCOSC_CONFIG0_CLR,Anadig 24mhz RC Oscillator Config0 Clear Register" hexmask.long.byte 0x18 24.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x18 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x18 4.--11. 1. " RC_OSC_PROG ,RC oscillator tuning values" textline " " bitfld.long 0x18 3. " TUNE_INVERT ,Inverts the stepping of the calculated RC tuning value" "Not inverted,Inverted" bitfld.long 0x18 2. " TUNE_BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "Not bypassed,Bypassed" bitfld.long 0x18 1. " TUNE_ENABLE ,Enables the tuning logic to calculate new RC tuning values" "Disabled,Enabled" bitfld.long 0x18 0. " TUNE_START ,Starts/stops the RC tuning calculation logic" "Stopped,Started" line.long 0x1C "RCOSC_CONFIG0_TOG,Anadig 24mhz RC Oscillator Config0 Toggle Register" hexmask.long.byte 0x1C 24.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x1C 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 4.--11. 1. " RC_OSC_PROG ,RC oscillator tuning values" textline " " bitfld.long 0x1C 3. " TUNE_INVERT ,Inverts the stepping of the calculated RC tuning value" "Not inverted,Inverted" bitfld.long 0x1C 2. " TUNE_BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "Not bypassed,Bypassed" bitfld.long 0x1C 1. " TUNE_ENABLE ,Enables the tuning logic to calculate new RC tuning values" "Disabled,Enabled" bitfld.long 0x1C 0. " TUNE_START ,Starts/stops the RC tuning calculation logic" "Stopped,Started" line.long 0x20 "RCOSC_CONFIG1,Anadig 24mhz RC Oscillator Config1 Register" hexmask.long.word 0x20 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x20 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x24 "RCOSC_CONFIG1_SET,Anadig 24mhz RC Oscillator Config1 Set Register" hexmask.long.word 0x24 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x24 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x28 "RCOSC_CONFIG1_CLR,Anadig 24mhz RC Oscillator Config1 Clear Register" hexmask.long.word 0x28 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x28 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x2C "RCOSC_CONFIG1_TOG,Anadig 24mhz RC Oscillator Config1 Toggle Register" hexmask.long.word 0x2C 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x2C 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x30 "RCOSC_CONFIG2,Anadig 24mhz RC Oscillator Config2 Register" eventfld.long 0x30 31. " CLK_1M_ERR_FL ,Indicates that the count_1m count wasn't reached within 1 32khz period" "Not reached,Reached" bitfld.long 0x30 17. " MUX_1M ,Mux the corrected or uncorrected 1mhz clock to the output" "Not muxed,Muxed" bitfld.long 0x30 16. " ENABLE_1M ,Enable the 1mhz clock output" "Disabled,Enabled" hexmask.long.word 0x30 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x34 "RCOSC_CONFIG2_SET,Anadig 24mhz RC Oscillator Config2 Set Register" eventfld.long 0x34 31. " CLK_1M_ERR_FL ,Indicates that the count_1m count wasn't reached within 1 32khz period" "Not reached,Reached" bitfld.long 0x34 17. " MUX_1M ,Mux the corrected or uncorrected 1mhz clock to the output" "Not muxed,Muxed" bitfld.long 0x34 16. " ENABLE_1M ,Enable the 1mhz clock output" "Disabled,Enabled" hexmask.long.word 0x34 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x38 "RCOSC_CONFIG2_CLR,Anadig 24mhz RC Oscillator Config2 Clear Register" eventfld.long 0x38 31. " CLK_1M_ERR_FL ,Indicates that the count_1m count wasn't reached within 1 32khz period" "Not reached,Reached" bitfld.long 0x38 17. " MUX_1M ,Mux the corrected or uncorrected 1mhz clock to the output" "Not muxed,Muxed" bitfld.long 0x38 16. " ENABLE_1M ,Enable the 1mhz clock output" "Disabled,Enabled" hexmask.long.word 0x38 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x3C "RCOSC_CONFIG2_TOG,Anadig 24mhz RC Oscillator Config2 Toggle Register" eventfld.long 0x3C 31. " CLK_1M_ERR_FL ,Indicates that the count_1m count wasn't reached within 1 32khz period" "Not reached,Reached" bitfld.long 0x3C 17. " MUX_1M ,Mux the corrected or uncorrected 1mhz clock to the output" "Not muxed,Muxed" bitfld.long 0x3C 16. " ENABLE_1M ,Enable the 1mhz clock output" "Disabled,Enabled" hexmask.long.word 0x3C 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" textline " " rgroup.long 0x50++0x03 line.long 0x00 "OSC_32K,32K Oscillator Control Register" rbitfld.long 0x00 0. " RTC_XTAL_SOURCE ,Indicates which chip source is being used for the rtc clock" "Internal ring oscillator,Rtc_xtal" group.long 0x54++0x0B line.long 0x00 "OSC_32K_SET,32K Oscillator Control Set Register" bitfld.long 0x00 0. " RTC_XTAL_SOURCE ,Indicates which chip source is being used for the rtc clock" "Internal ring oscillator,Rtc_xtal" line.long 0x04 "OSC_32K_CLR,32K Oscillator Control Clear Register" bitfld.long 0x04 0. " RTC_XTAL_SOURCE ,Indicates which chip source is being used for the rtc clock" "Internal ring oscillator,Rtc_xtal" line.long 0x08 "OSC_32K_TOG,32K Oscillator Control Toggle Register" bitfld.long 0x08 0. " RTC_XTAL_SOURCE ,Indicates which chip source is being used for the rtc clock" "Internal ring oscillator,Rtc_xtal" width 0x0B tree.end tree "PMU (Power Management Unit)" base ad:0x30360200 width 20. group.long 0x200++0x0F line.long 0x00 "REG_1P0A,Anadig 1.0V A Regulator Control Register" bitfld.long 0x00 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" newline rbitfld.long 0x00 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x00 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Control bits to adjust the regulator output voltage in 25mv steps" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" newline bitfld.long 0x00 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x00 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_1P0A_SET,Anadig 1.0V A Regulator Control Set Register" bitfld.long 0x04 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" newline rbitfld.long 0x04 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x04 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" bitfld.long 0x04 8.--12. " OUTPUT_TRG ,Control bits to adjust the regulator output voltage in 25mv steps" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" newline bitfld.long 0x04 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x04 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_1P0A_CLR,Anadig 1.0V A Regulator Control Clear Register" bitfld.long 0x08 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" newline rbitfld.long 0x08 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x08 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" bitfld.long 0x08 8.--12. " OUTPUT_TRG ,Control bits to adjust the regulator output voltage in 25mv steps" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" newline bitfld.long 0x08 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x08 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x0C "REG_1P0A_TOG,Anadig 1.0V A Regulator Control Toggle Register" bitfld.long 0x0C 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" bitfld.long 0x0C 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" newline rbitfld.long 0x0C 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x0C 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" bitfld.long 0x0C 8.--12. " OUTPUT_TRG ,Control bits to adjust the regulator output voltage in 25mv steps" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" newline bitfld.long 0x0C 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x0C 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" bitfld.long 0x0C 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x0C 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" group.long 0x210++0x0F line.long 0x00 "REG_1P0D,Anadig 1.0V D Regulator Control Register" bitfld.long 0x00 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x00 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x00 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x00 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x00 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x00 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_1P0D_SET,Anadig 1.0V D Regulator Control Set Register" bitfld.long 0x04 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x04 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x04 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x04 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x04 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x04 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x04 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_1P0D_CLR,Anadig 1.0V D Regulator Control Clear Register" bitfld.long 0x08 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x08 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x08 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x08 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x08 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x08 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x08 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x0C "REG_1P0D_TOG,Anadig 1.0V D Regulator Control Toggle Register" bitfld.long 0x0C 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x0C 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x0C 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x0C 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x0C 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x0C 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x0C 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x0C 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x0C 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" group.long 0x220++0x0F line.long 0x00 "REG_HSIC_1P2,Anadig 1.2V HSIC Regulator Control Register" bitfld.long 0x00 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x00 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x00 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x00 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x00 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x00 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_HSIC_1P2_SET,Anadig 1.2V HSIC Regulator Control Set Register" bitfld.long 0x04 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x04 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x04 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x04 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x04 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x04 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x04 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_HSIC_1P2_CLR,Anadig 1.2V HSIC Regulator Control Clear Register" bitfld.long 0x08 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x08 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x08 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x08 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x08 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x08 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x08 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x0C "REG_HSIC_1P2_TOG,Anadig 1.2V HSIC Regulator Control Toggle Register" bitfld.long 0x0C 31. " OVERRIDE ,The OVERRIDE bit allows the GPC module to automatically override portions of the register" "No override,Override" bitfld.long 0x0C 20.--23. " REG_TEST ,Test bits to monitor different analog signals though anamux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 19. " SELREF_WEAK_LINREG ,Selects the source for the reference voltage of the weak 1p1 regulator" "Lowpower-bandgap,VDD_SOC_CAP" newline bitfld.long 0x0C 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x0C 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" eventfld.long 0x0C 16. " BO ,Interrupt/status bit that signals when a brown-out is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x0C 8.--12. " OUTPUT_TRG ,OUTPUT_TRG" "0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775,0.8,0.825,0.85,0.875,0.9,0.925,0.95,0.975,1.0,1.025,1.05,1.075,1.1,1.125,1.15,1.175,1.2,1.225,1.25,1.275,1.3,1.325,1.35,1.375" bitfld.long 0x0C 7. " ENABLE_PWRUPLOAD ,ENABLE_PWRUPLOAD" "Disabled,?..." bitfld.long 0x0C 4.--6. " BO_OFFSET ,Control bits to adjust the regulator brown-out offset voltage in 25mv steps" "0,25,50,75,100,125,150,175" newline bitfld.long 0x0C 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x0C 1. " ENABLE_BO ,Control bit to enable the brown-out circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" group.long 0x230++0x0F line.long 0x00 "REG_LPSR_1P0,Anadig 1.0V Low Power State Retention Regulator Control Register" hexmask.long.byte 0x00 24.--31. 1. " RSVD1 ,RSVD1" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" ",Enabled" rbitfld.long 0x00 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" newline bitfld.long 0x00 7. " ENABLE_PWRUPLOAD ,Enables a ~100kohm load to ground" "Disabled,Enabled" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Enables a ~50kohm load to ground" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" ",Enabled" line.long 0x04 "REG_LPSR_1P0_SET,Anadig 1.0V Low Power State Retention Regulator Control Set Register" hexmask.long.byte 0x04 24.--31. 1. " RSVD1 ,RSVD1" bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" ",Enabled" rbitfld.long 0x04 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" newline bitfld.long 0x04 7. " ENABLE_PWRUPLOAD ,Enables a ~100kohm load to ground." "Disabled,Enabled" bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Enables a ~50kohm load to ground" "Disabled,Enabled" bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" ",Enabled" line.long 0x08 "REG_LPSR_1P0_CLR,Anadig 1.0V Low Power State Retention Regulator Control Clear Register" hexmask.long.byte 0x08 24.--31. 1. " RSVD1 ,RSVD1" bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" ",Enabled" rbitfld.long 0x08 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" newline bitfld.long 0x08 7. " ENABLE_PWRUPLOAD ,Enables a ~100kohm load to ground." "Disabled,Enabled" bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Enables a ~50kohm load to ground" "Disabled,Enabled" bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" ",Enabled" line.long 0x0C "REG_LPSR_1P0_TOG,Anadig 1.0V Low Power State Retention Regulator Control Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " RSVD1 ,RSVD1" bitfld.long 0x0C 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" ",Enabled" rbitfld.long 0x0C 17. " OK ,Status bit that signals when the regulator output is ok" "Not ok,Ok" newline bitfld.long 0x0C 7. " ENABLE_PWRUPLOAD ,Enables a ~100kohm load to ground." "Disabled,Enabled" bitfld.long 0x0C 3. " ENABLE_PULLDOWN ,Enables a ~50kohm load to ground" "Disabled,Enabled" bitfld.long 0x0C 0. " ENABLE_LINREG ,Control bit to enable the regulator output" ",Enabled" group.long 0x270++0x0F line.long 0x00 "REF,Anadig Reference Analog Control And Status Register" bitfld.long 0x00 13. " REFTOP_LINREGREF_EN ,Enables buffer from the main bandgap for use with the linear regulators" "Disabled,Enabled" bitfld.long 0x00 12. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x00 11. " LPBG_TEST ,Low power bandgap test bit" "0,1" newline bitfld.long 0x00 10. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x00 8.--9. " REFTOP_BIAS_TST ,Freescale debug/test bits" "Nom,90% ibias,80% ibias,110% ibias" rbitfld.long 0x00 7. " REFTOP_VBGUP ,Status bit which signals that the analog bandgap voltage is up and stable" "Down & unstable,Up & stable" newline bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,Freescale debug/test bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x00 2. " REFTOP_LOWPOWER ,Control bit to enable the low-power mode in the analog bandgap" "Disabled,Enabled" newline bitfld.long 0x00 1. " REFTOP_PWDVBGUP ,Control bit to power-down the VBG-up detection circuitry in the analog bandgap" "Not powered-down,Powered-down" bitfld.long 0x00 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Not powered-down,Powered-down" line.long 0x04 "REF_SET,Anadig Reference Analog Control And Status Set Register" bitfld.long 0x04 13. " REFTOP_LINREGREF_EN ,Enables buffer from the main bandgap for use with the linear regulators" "Disabled,Enabled" bitfld.long 0x04 12. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x04 11. " LPBG_TEST ,Low power bandgap test bit" "0,1" newline bitfld.long 0x04 10. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x04 8.--9. " REFTOP_BIAS_TST ,Freescale debug/test bits" "Nom,90% ibias,80% ibias,110% ibias" rbitfld.long 0x04 7. " REFTOP_VBGUP ,Status bit which signals that the analog bandgap voltage is up and stable" "Down & unstable,Up & stable" newline bitfld.long 0x04 4.--6. " REFTOP_VBGADJ ,Freescale debug/test bits" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x04 2. " REFTOP_LOWPOWER ,Control bit to enable the low-power mode in the analog bandgap" "Disabled,Enabled" newline bitfld.long 0x04 1. " REFTOP_PWDVBGUP ,Control bit to power-down the VBG-up detection circuitry in the analog bandgap" "Not powered-down,Powered-down" bitfld.long 0x04 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Not powered-down,Powered-down" line.long 0x08 "REF_CLR,Anadig Reference Analog Control And Status Clear Register" bitfld.long 0x08 13. " REFTOP_LINREGREF_EN ,Enables buffer from the main bandgap for use with the linear regulators" "Disabled,Enabled" bitfld.long 0x08 12. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x08 11. " LPBG_TEST ,Low power bandgap test bit" "0,1" newline bitfld.long 0x08 10. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x08 8.--9. " REFTOP_BIAS_TST ,Freescale debug/test bits" "Nom,90% ibias,80% ibias,110% ibias" rbitfld.long 0x08 7. " REFTOP_VBGUP ,Status bit which signals that the analog bandgap voltage is up and stable" "Down & unstable,Up & stable" newline bitfld.long 0x08 4.--6. " REFTOP_VBGADJ ,Freescale debug/test bits" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x08 2. " REFTOP_LOWPOWER ,Control bit to enable the low-power mode in the analog bandgap" "Disabled,Enabled" newline bitfld.long 0x08 1. " REFTOP_PWDVBGUP ,Control bit to power-down the VBG-up detection circuitry in the analog bandgap" "Not powered-down,Powered-down" bitfld.long 0x08 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Not powered-down,Powered-down" line.long 0x0C "REF_TOG,Anadig Reference Analog Control And Status Toggle Register" bitfld.long 0x0C 13. " REFTOP_LINREGREF_EN ,Enables buffer from the main bandgap for use with the linear regulators" "Disabled,Enabled" bitfld.long 0x0C 12. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x0C 11. " LPBG_TEST ,Low power bandgap test bit" "0,1" newline bitfld.long 0x0C 10. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x0C 8.--9. " REFTOP_BIAS_TST ,Freescale debug/test bits" "Nom,90% ibias,80% ibias,110% ibias" rbitfld.long 0x0C 7. " REFTOP_VBGUP ,Status bit which signals that the analog bandgap voltage is up and stable" "Down & unstable,Up & stable" newline bitfld.long 0x0C 4.--6. " REFTOP_VBGADJ ,Freescale debug/test bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x0C 2. " REFTOP_LOWPOWER ,Control bit to enable the low-power mode in the analog bandgap" "Disabled,Enabled" newline bitfld.long 0x0C 1. " REFTOP_PWDVBGUP ,Control bit to power-down the VBG-up detection circuitry in the analog bandgap" "Not powered-down,Powered-down" bitfld.long 0x0C 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Not powered-down,Powered-down" group.long 0x330++0x0F line.long 0x00 "LOWPWR_CTRL,Anadig Low Power Control Register" bitfld.long 0x00 13. " GPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x00 12. " MIX_PWRGATE ,Display power gate control" "Ungated,Gated" bitfld.long 0x00 11. " DISPLAY_PWRGATED ,Display power gate control" "Ungated,Gated" newline bitfld.long 0x00 10. " CPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x00 9. " L2_PWRGATE ,L2 power gate control" "Ungated,Gated" bitfld.long 0x00 8. " L1_PWRGATE ,L1 power gate control" "Ungated,Gated" newline bitfld.long 0x00 0.--1. " STOP_MODE_CONFIG ,Configure the analog behavior in stop Mode (XTALOSC/RCOSC/Old BG/New BG)" "On/Off/-/-,On/Off/-/-,Off/On/On/Off,Off/On/Off/On" line.long 0x04 "LOWPWR_CTRL_SET,Anadig Low Power Control Set Register" bitfld.long 0x04 13. " GPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x04 12. " MIX_PWRGATE ,Display power gate control" "Ungated,Gated" bitfld.long 0x04 11. " DISPLAY_PWRGATED ,Display power gate control" "Ungated,Gated" newline bitfld.long 0x04 10. " CPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x04 9. " L2_PWRGATE ,L2 power gate control" "Ungated,Gated" bitfld.long 0x04 8. " L1_PWRGATE ,L1 power gate control" "Ungated,Gated" newline bitfld.long 0x04 0.--1. " STOP_MODE_CONFIG ,Configure the analog behavior in stop Mode (XTALOSC/RCOSC/Old BG/New BG)" "On/Off/-/-,On/Off/-/-,Off/On/On/Off,Off/On/Off/On" line.long 0x08 "LOWPWR_CTRL_CLR,Anadig Low Power Control Clear Register" bitfld.long 0x08 13. " GPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x08 12. " MIX_PWRGATE ,Display power gate control" "Ungated,Gated" bitfld.long 0x08 11. " DISPLAY_PWRGATED ,Display power gate control" "Ungated,Gated" newline bitfld.long 0x08 10. " CPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x08 9. " L2_PWRGATE ,L2 power gate control" "Ungated,Gated" bitfld.long 0x08 8. " L1_PWRGATE ,L1 power gate control" "Ungated,Gated" newline bitfld.long 0x08 0.--1. " STOP_MODE_CONFIG ,Configure the analog behavior in stop Mode (XTALOSC/RCOSC/Old BG/New BG)" "On/Off/-/-,On/Off/-/-,Off/On/On/Off,Off/On/Off/On" line.long 0x0C "LOWPWR_CTRL_TOG,Anadig Low Power Control Toggle Register" bitfld.long 0x0C 13. " GPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x0C 12. " MIX_PWRGATE ,Display power gate control" "Ungated,Gated" bitfld.long 0x0C 11. " DISPLAY_PWRGATED ,Display power gate control" "Ungated,Gated" newline bitfld.long 0x0C 10. " CPU_PWRGATE ,GPU power gate control" "Ungated,Gated" bitfld.long 0x0C 9. " L2_PWRGATE ,L2 power gate control" "Ungated,Gated" bitfld.long 0x0C 8. " L1_PWRGATE ,L1 power gate control" "Ungated,Gated" newline bitfld.long 0x0C 0.--1. " STOP_MODE_CONFIG ,Configure the analog behavior in stop Mode (XTALOSC/RCOSC/Old BG/New BG)" "On/Off/-/-,On/Off/-/-,Off/On/On/Off,Off/On/Off/On" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") group.long 0x380++0x0F line.long 0x00 "SNVS_MISC_CTRL,Anadig SNVS Miscellaneous Control Register" bitfld.long 0x00 31. " SNVS_ISOLATION_REMOVE ,Isolation on software trims/pull controls disable" "No,Yes" bitfld.long 0x00 30. " DDR_PAD_CTRL ,Retention mode control" "Retention,Normal" bitfld.long 0x00 29. " DDR_PWR_GATE ,Signal to control external power switch to be able to turn DRAM power ON and OFF" "0,1" newline bitfld.long 0x00 28. " DDR_PWR_GATE_SHDW ,Readback of DDR_PWR_GATE shadow bit from SNVS shadow register" "DDR PFET is gated on,DDR PFET is gated off" bitfld.long 0x00 27. " DDR_PAD_CTRL_SHDW ,Readback of DDR_PAD_CTRL shadow bit from SNVS shadow register" "Normal mode,Retention mode" bitfld.long 0x00 0.--3. " OSC_CAP_TRIM ,Trims to control the CAP on 32K oscillator" "Add 0pF load on EXTAL/XTAL,Add 2pF load on EXTAL/XTAL,Add 4pF load on EXTAL/XTAL,Add 6pF load on EXTAL/XTAL,Add 8pF load on EXTAL/XTAL,Add 10pF load on EXTAL/XTAL,Add 12pF load on EXTAL/XTAL,Add 14pF load on EXTAL/XTAL,Add 16pF load on EXTAL/XTAL,Add 18pF load on EXTAL/XTAL,Add 20pF load on EXTAL/XTAL,Add 22pF load on EXTAL/XTAL,Add 24pF load on EXTAL/XTAL,Add 26pF load on EXTAL/XTAL,Add 28pF load on EXTAL/XTAL,Add 30pF load on EXTAL/XTAL" line.long 0x04 "SNVS_MISC_CTRL_SET,Anadig SNVS Miscellaneous Control Set Register" bitfld.long 0x04 31. " SNVS_ISOLATION_REMOVE ,Isolation on software trims/pull controls disable" "No,Yes" bitfld.long 0x04 30. " DDR_PAD_CTRL ,Retention mode control" "Retention,Normal" bitfld.long 0x04 29. " DDR_PWR_GATE ,Signal to control external power switch to be able to turn DRAM power ON and OFF" "0,1" newline bitfld.long 0x04 28. " DDR_PWR_GATE_SHDW ,Readback of DDR_PWR_GATE shadow bit from SNVS shadow register" "DDR PFET is gated on,DDR PFET is gated off" bitfld.long 0x04 27. " DDR_PAD_CTRL_SHDW ,Readback of DDR_PAD_CTRL shadow bit from SNVS shadow register" "Normal mode,Retention mode" bitfld.long 0x04 0.--3. " OSC_CAP_TRIM ,Trims to control the CAP on 32K oscillator" "Add 0pF load on EXTAL/XTAL,Add 2pF load on EXTAL/XTAL,Add 4pF load on EXTAL/XTAL,Add 6pF load on EXTAL/XTAL,Add 8pF load on EXTAL/XTAL,Add 10pF load on EXTAL/XTAL,Add 12pF load on EXTAL/XTAL,Add 14pF load on EXTAL/XTAL,Add 16pF load on EXTAL/XTAL,Add 18pF load on EXTAL/XTAL,Add 20pF load on EXTAL/XTAL,Add 22pF load on EXTAL/XTAL,Add 24pF load on EXTAL/XTAL,Add 26pF load on EXTAL/XTAL,Add 28pF load on EXTAL/XTAL,Add 30pF load on EXTAL/XTAL" line.long 0x08 "SNVS_MISC_CTRL_CLR,Anadig SNVS Miscellaneous Control Clear Register" bitfld.long 0x08 31. " SNVS_ISOLATION_REMOVE ,Isolation on software trims/pull controls disable" "No,Yes" bitfld.long 0x08 30. " DDR_PAD_CTRL ,Retention mode control" "Retention,Normal" bitfld.long 0x08 29. " DDR_PWR_GATE ,Signal to control external power switch to be able to turn DRAM power ON and OFF" "0,1" newline bitfld.long 0x08 28. " DDR_PWR_GATE_SHDW ,Readback of DDR_PWR_GATE shadow bit from SNVS shadow register" "DDR PFET is gated on,DDR PFET is gated off" bitfld.long 0x08 27. " DDR_PAD_CTRL_SHDW ,Readback of DDR_PAD_CTRL shadow bit from SNVS shadow register" "Normal mode,Retention mode" bitfld.long 0x08 0.--3. " OSC_CAP_TRIM ,Trims to control the CAP on 32K oscillator" "Add 0pF load on EXTAL/XTAL,Add 2pF load on EXTAL/XTAL,Add 4pF load on EXTAL/XTAL,Add 6pF load on EXTAL/XTAL,Add 8pF load on EXTAL/XTAL,Add 10pF load on EXTAL/XTAL,Add 12pF load on EXTAL/XTAL,Add 14pF load on EXTAL/XTAL,Add 16pF load on EXTAL/XTAL,Add 18pF load on EXTAL/XTAL,Add 20pF load on EXTAL/XTAL,Add 22pF load on EXTAL/XTAL,Add 24pF load on EXTAL/XTAL,Add 26pF load on EXTAL/XTAL,Add 28pF load on EXTAL/XTAL,Add 30pF load on EXTAL/XTAL" line.long 0x0C "SNVS_MISC_CTRL_TOG,Anadig SNVS Miscellaneous Control Toggle Register" bitfld.long 0x0C 31. " SNVS_ISOLATION_REMOVE ,Isolation on software trims/pull controls disable" "No,Yes" bitfld.long 0x0C 30. " DDR_PAD_CTRL ,Retention mode control" "Retention,Normal" bitfld.long 0x0C 29. " DDR_PWR_GATE ,Signal to control external power switch to be able to turn DRAM power ON and OFF" "0,1" newline bitfld.long 0x0C 28. " DDR_PWR_GATE_SHDW ,Readback of DDR_PWR_GATE shadow bit from SNVS shadow register" "DDR PFET is gated on,DDR PFET is gated off" bitfld.long 0x0C 27. " DDR_PAD_CTRL_SHDW ,Readback of DDR_PAD_CTRL shadow bit from SNVS shadow register" "Normal mode,Retention mode" bitfld.long 0x0C 0.--3. " OSC_CAP_TRIM ,Trims to control the CAP on 32K oscillator" "Add 0pF load on EXTAL/XTAL,Add 2pF load on EXTAL/XTAL,Add 4pF load on EXTAL/XTAL,Add 6pF load on EXTAL/XTAL,Add 8pF load on EXTAL/XTAL,Add 10pF load on EXTAL/XTAL,Add 12pF load on EXTAL/XTAL,Add 14pF load on EXTAL/XTAL,Add 16pF load on EXTAL/XTAL,Add 18pF load on EXTAL/XTAL,Add 20pF load on EXTAL/XTAL,Add 22pF load on EXTAL/XTAL,Add 24pF load on EXTAL/XTAL,Add 26pF load on EXTAL/XTAL,Add 28pF load on EXTAL/XTAL,Add 30pF load on EXTAL/XTAL" endif width 0x0B tree.end tree.open "GPC (General Power Controller)" tree "GPC" base ad:0x303A0000 width 24. group.long 0x00++0x0B line.long 0x00 "LPCR_A7_BSC,Basic Low Power Control Register Of A7 Platform" bitfld.long 0x00 31. " MASK_DSM_TRIGGER ,DSM trigger mask" "Not masked,Masked" bitfld.long 0x00 30. " IRQ_SRC_A7_WUP ,Wake up source for A7 LPM power" "OR result of 28|29 bits,External INT" newline bitfld.long 0x00 29. " IRQ_SRC_C1 ,Wake up source for core1 power" "External int&masked by IMR1,GIC" bitfld.long 0x00 28. " IRQ_SRC_C0 ,Wake up source for core0 power" "External int&masked by IMR0,GIC" newline bitfld.long 0x00 26. " MASK_L2CC_WFI ,L2 cache controller wait for interrupt mask register" "Not masked,Masked" bitfld.long 0x00 17. " MASK_CORE1_WFI ,CORE1 wait for interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 16. " MASK_CORE0_WFI ,CORE0 wait for interrupt mask" "Not masked,Masked" bitfld.long 0x00 14. " CPU_CLK_ON_LPM ,Define if A7 clocks will be disabled on wait/stop mode" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " LPM1 ,CORE1 setting the low power mode that system will enter on next assertion of dsm_request signal" "RUN,WAIT,STOP,?..." bitfld.long 0x00 0.--1. " LPM0 ,CORE0 setting the low power mode that system will enter on next assertion of dsm_request signal" "RUN,WAIT,STOP,?..." line.long 0x04 "LPCR_A7_AD,Advanced Low Power Control Register Of A7 Platform" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x04 16. " L2_PGE ,L2 cache RAM will power down with SCU power domain in A7 platform" "No,Yes" bitfld.long 0x04 11. " EN_C1_PUP ,CORE1 will power up with low power mode request" "No,Yes" else bitfld.long 0x04 16. " L2_PGE ,L2 cache RAM will not power down with SCU power domain in A7 platform" "No,Yes" bitfld.long 0x04 11. " EN_C1_PUP ,CORE1 will not power up with low power mode request" "No,Yes" endif newline bitfld.long 0x04 10. " EN_C1_IRQ_PUP ,CORE1 will not power up with IRQ request" "No,Yes" bitfld.long 0x04 9. " EN_C0_PUP ,CORE0 will not power up with low power mode request" "No,Yes" newline bitfld.long 0x04 8. " EN_C0_IRQ_PUP ,CORE0 will not power up with IRQ request" "No,Yes" bitfld.long 0x04 4. " EN_PLAT_PDN ,SCU and L2 cache RAM will be power down with low power mode request" "No,Yes" newline bitfld.long 0x04 3. " EN_C1_PDN ,CORE1 will be power down with low power mode request" "No,Yes" bitfld.long 0x04 2. " EN_C1_WFI_PDN ,CORE1 will be power down with WFI request" "No,Yes" newline bitfld.long 0x04 1. " EN_C0_PDN ,CORE0 will be power down with low power mode request" "No,Yes" bitfld.long 0x04 0. " EN_C0_WFI_PDN ,CORE0 will be power down with WFI request" "No,Yes" line.long 0x08 "LPCR_M4,Low Power Control Register Of CPU1" bitfld.long 0x08 31. " MASK_DSM_TRIGGER ,DSM trigger mask" "Not masked,Masked" bitfld.long 0x08 16. " MASK_M4_WFI ,M4 WFI mask" "Not masked,Masked" newline bitfld.long 0x08 14. " CPU_CLK_ON_LPM ,Define if M4 clocks will be disabled on wait/stop mode" "Disabled,Enabled" bitfld.long 0x08 3. " EN_M4_PUP ,Enable m4 virtual PGC power up with LPM enter" "Disabled,Enabled" newline bitfld.long 0x08 2. " EN_M4_PDN ,Enable m4 virtual PGC power down with LPM enter" "Disabled,Enabled" bitfld.long 0x08 0.--1. " LPM0 ,Setting the low power mode that system will enter on next assertion of dsm_request signal" "RUN,WAIT,STOP,?..." group.long 0x14++0x03 line.long 0x00 "SLPCR,System Low Power Control Register" bitfld.long 0x00 31. " EN_DSM ,DSM enable" "Disabled,Enabled" bitfld.long 0x00 30. " RBC_EN ,Enable for REG_BYPASS_COUNTER" "Disabled,Enabled" newline bitfld.long 0x00 24.--29. " REG_BYPASS_COUNT ,Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ (Ckil clock periods)" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " DISABLE_A7_IS_DSM ,Disable a7 isolation signal in DSM" "No,Yes" newline bitfld.long 0x00 19. " EN_M4_FASTWUP_STOP_MODE ,Enable M4 fast wake up stop mode, relevant plls will not be closed in this mode" "Disabled,Enabled" bitfld.long 0x00 18. " EN_M4_FASTWUP_WAIT_MODE ,Enable M4 fast wake up wait mode, relevant plls will not be closed in this mode" "Disabled,Enabled" newline bitfld.long 0x00 17. " EN_A7_FASTWUP_STOP_MODE ,Enable A7 fast wake up stop mode, relevant plls will not be closed in this mode" "Disabled,Enabled" bitfld.long 0x00 16. " EN_A7_FASTWUP_WAIT_MODE ,Enable A7 fast wake up wait mode, relevant plls will not be closed in this mode" "Disabled,Enabled" newline hexmask.long.byte 0x00 8.--15. 1. " OSCCNT ,Oscillator ready counter value" bitfld.long 0x00 7. " COSC_EN ,On-chip oscillator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. " COSC_PWRDOWN ,Controls powering down of on chip oscillator" "Not powered down,Powered down" bitfld.long 0x00 3.--5. " STBY_COUNT ,Standby counter definition" "4 CKIL,8 CKIL,16 CKIL,32 CKIL,64 CKIL,128 CKIL,256 CKIL,512CKIL" newline bitfld.long 0x00 2. " VSTBY ,Voltage standby request bit" "Not changed,Changed" bitfld.long 0x00 1. " SBYOS ,Standby clock oscillator bit" "Not powered down,Powered down" newline bitfld.long 0x00 0. " BYPASS_PMIC_READY ,By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM" "Not bypassed,Bypassed" group.long 0x20++0x2F line.long 0x00 "MLPCR,Memory Low Power Control Register" hexmask.long.byte 0x00 24.--31. 1. " MEMLP_RET_PGEN ,Delay conter for retnx and pgen" hexmask.long.byte 0x00 16.--23. 1. " MEM_EXT_CNT ,Delay counter to start existing from memory low power" newline hexmask.long.byte 0x00 8.--15. 1. " MEMLP_ENT_CNT ,Delay counter to make sure all clock off after pll_dis_req is issued by SMC" bitfld.long 0x00 2. " ROMLP_PDN_DIS ,Disable ROM shut down control" "No,Yes" newline bitfld.long 0x00 1. " MEMLP_RET_SEL ,Retention select" "Mode 2,Mode 1" bitfld.long 0x00 0. " MEMLP_CTL_DIS ,Disable RAM low-power control" "No,Yes" line.long 0x04 "PGC_ACK_SEL_A7,PGC Acknowledge Signal Selection Of A7 Platform" bitfld.long 0x04 31. " A7_PGC_PUP_ACK ,Select power up acknowledge signal of A7 (Dummy) PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 24. " USB_HSIC_PGC_PUP_ACK ,Select power up acknowledge signal of USB_HSIC PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 23. " USB_OTG2_PGC_PUP_ACK ,Select power up acknowledge signal of USB_OTG2 PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 22. " USB_OTG1_PGC_PUP_ACK ,Select power up acknowledge signal of USB_OTG1 PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 21. " PCIE_PGC_PUP_ACK ,Select power up acknowledge signal of PCIE PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 20. " MIPI_PGC_PUP_ACK ,Select power up acknowledge signal of MIPI PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 19. " MF_PGC_PUP_ACK ,Select power up acknowledge signal of MF PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 18. " A7_PLAT_PGC_PUP_ACK ,Select power up acknowledge signal of A7 PLATFORM PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 17. " A7_C1_PGC_PUP_ACK ,Select power up acknowledge signal of A7 CORE1 PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 16. " A7_C0_PGC_PUP_ACK ,Select power up acknowledge signal of A7 CORE0 PGC as the power up acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 15. " A7_PGC_PDN_ACK ,Select power down acknowledge signal of A7 (Dummy) PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 8. " USB_HSIC_PGC_PDN_ACK ,Select power down acknowledge signal of USB_HSIC PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 7. " USB_OTG2_PGC_PDN_ACK ,Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 6. " USB_OTG1_PGC_PDN_ACK ,Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 5. " PCIE_PGC_PDN_ACK ,Select power down acknowledge signal of PCIE PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 4. " MIPI_PGC_PDN_ACK ,Select power down acknowledge signal of MIPI PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 3. " MF_PGC_PDN_ACK ,Select power down acknowledge signal of MIX PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 2. " A7_PLAT_PGC_PDN_ACK ,Select power down acknowledge signal of A7 PLATFORM PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" newline bitfld.long 0x04 1. " A7_C1_PGC_PDN_ACK ,Select power down acknowledge signal of A7 CORE1 PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" bitfld.long 0x04 0. " A7_C0_PGC_PDN_ACK ,Select power down acknowledge signal of A7 CORE0 PGC as the power down acknowledge for A7 LPM" "Not selected,Selected" line.long 0x08 "PGC_ACK_SEL_M4,PGC Acknowledge Signal Selection Of M4 Platform" bitfld.long 0x08 31. " M4_DUMMY_PGC_PUP_ACK ,Select power up acknowledge signal of M4 (Dummy) PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 24. " USB_HSIC_PGC_PUP_ACK ,Select power up acknowledge signal of USB_HSIC PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 23. " USB_OTG2_PGC_PUP_ACK ,Select power up acknowledge signal of USB_OTG2 PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 22. " USB_OTG1_PGC_PUP_ACK ,Select power up acknowledge signal of USB_OTG1 PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 21. " PCIE_PGC_PUP_ACK ,Select power up acknowledge signal of PCIE PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 20. " MIPI_PGC_PUP_ACK ,Select power up acknowledge signal of MIPI PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 19. " MF_PGC_PUP_ACK ,Select power up acknowledge signal of MF PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 16. " M4_VIRTUAL_PGC_PUP_ACK ,Select power up acknowledge signal of M4 virtual PGC as the power up acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 15. " M4_DUMMY_PGC_PDN_ACK ,Select power down acknowledge signal of M4 (Dummy) PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 8. " USB_HSIC_PGC_PDN_ACK ,Select power down acknowledge signal of USB_HSIC PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 7. " USB_OTG2_PGC_PDN_ACK ,Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 6. " USB_OTG1_PGC_PDN_ACK ,Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 5. " PCIE_PGC_PDN_ACK ,Select power down acknowledge signal of PCIE PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 4. " MIPI_PGC_PDN_ACK ,Select power down acknowledge signal of MIPI PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" newline bitfld.long 0x08 3. " MF_PGC_PDN_ACK ,Select power down acknowledge signal of MIX PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" bitfld.long 0x08 0. " M4_VIRTUAL_PGC_PDN_ACK ,Select power down acknowledge signal of M4 virtual PGC as the power down acknowledge for M4 LPM" "Not selected,Selected" line.long 0x0C "MISC,GPC Miscellaneous Register" bitfld.long 0x0C 8. " M4_PDN_REQ_MASK ,M4 power-down mask" "Masked,Not masked" bitfld.long 0x0C 5. " GPC_IRQ_MASK ,GPC interrupt/event masking" "Not masked,Masked" newline bitfld.long 0x0C 0. " M4_SLEEP_HOLD_REQ_B ,M4 sleep hold" "Sleep mode,No sleep mode" line.long 0x10 "IMR1_CORE0_A7,IRQ Masking Register 1 Of A7 Core0" bitfld.long 0x10 31. " IMR1_CORE0_A7[31] ,A7 core0 IRQ[31] masking bit" "Not masked,Masked" bitfld.long 0x10 30. " [30] ,A7 core0 IRQ[30] masking bit" "Not masked,Masked" newline bitfld.long 0x10 29. " [29] ,A7 core0 IRQ[29] masking bit" "Not masked,Masked" bitfld.long 0x10 28. " [28] ,A7 core0 IRQ[28] masking bit" "Not masked,Masked" newline bitfld.long 0x10 27. " [27] ,A7 core0 IRQ[27] masking bit" "Not masked,Masked" bitfld.long 0x10 26. " [26] ,A7 core0 IRQ[26] masking bit" "Not masked,Masked" newline bitfld.long 0x10 25. " [25] ,A7 core0 IRQ[25] masking bit" "Not masked,Masked" bitfld.long 0x10 24. " [24] ,A7 core0 IRQ[24] masking bit" "Not masked,Masked" newline bitfld.long 0x10 23. " [23] ,A7 core0 IRQ[23] masking bit" "Not masked,Masked" bitfld.long 0x10 22. " [22] ,A7 core0 IRQ[22] masking bit" "Not masked,Masked" newline bitfld.long 0x10 21. " [21] ,A7 core0 IRQ[21] masking bit" "Not masked,Masked" bitfld.long 0x10 20. " [20] ,A7 core0 IRQ[20] masking bit" "Not masked,Masked" newline bitfld.long 0x10 19. " [19] ,A7 core0 IRQ[19] masking bit" "Not masked,Masked" bitfld.long 0x10 18. " [18] ,A7 core0 IRQ[18] masking bit" "Not masked,Masked" newline bitfld.long 0x10 17. " [17] ,A7 core0 IRQ[17] masking bit" "Not masked,Masked" bitfld.long 0x10 16. " [16] ,A7 core0 IRQ[16] masking bit" "Not masked,Masked" newline bitfld.long 0x10 15. " [15] ,A7 core0 IRQ[15] masking bit" "Not masked,Masked" bitfld.long 0x10 14. " [14] ,A7 core0 IRQ[14] masking bit" "Not masked,Masked" newline bitfld.long 0x10 13. " [13] ,A7 core0 IRQ[13] masking bit" "Not masked,Masked" bitfld.long 0x10 12. " [12] ,A7 core0 IRQ[12] masking bit" "Not masked,Masked" newline bitfld.long 0x10 11. " [11] ,A7 core0 IRQ[11] masking bit" "Not masked,Masked" bitfld.long 0x10 10. " [10] ,A7 core0 IRQ[10] masking bit" "Not masked,Masked" newline bitfld.long 0x10 9. " [9] ,A7 core0 IRQ[9] masking bit" "Not masked,Masked" bitfld.long 0x10 8. " [8] ,A7 core0 IRQ[8] masking bit" "Not masked,Masked" newline bitfld.long 0x10 7. " [7] ,A7 core0 IRQ[7] masking bit" "Not masked,Masked" bitfld.long 0x10 6. " [6] ,A7 core0 IRQ[6] masking bit" "Not masked,Masked" newline bitfld.long 0x10 5. " [5] ,A7 core0 IRQ[5] masking bit" "Not masked,Masked" bitfld.long 0x10 4. " [4] ,A7 core0 IRQ[4] masking bit" "Not masked,Masked" newline bitfld.long 0x10 3. " [3] ,A7 core0 IRQ[3] masking bit" "Not masked,Masked" bitfld.long 0x10 2. " [2] ,A7 core0 IRQ[2] masking bit" "Not masked,Masked" newline bitfld.long 0x10 1. " [1] ,A7 core0 IRQ[1] masking bit" "Not masked,Masked" bitfld.long 0x10 0. " [0] ,A7 core0 IRQ[0] masking bit" "Not masked,Masked" line.long 0x14 "IMR2_CORE0_A7,IRQ Masking Register 2 Of A7 Core0" bitfld.long 0x14 31. " IMR2_CORE0_A7[63] ,A7 core0 IRQ[63] masking bit" "Not masked,Masked" bitfld.long 0x14 30. " [62] ,A7 core0 IRQ[62] masking bit" "Not masked,Masked" newline bitfld.long 0x14 29. " [61] ,A7 core0 IRQ[61] masking bit" "Not masked,Masked" bitfld.long 0x14 28. " [60] ,A7 core0 IRQ[60] masking bit" "Not masked,Masked" newline bitfld.long 0x14 27. " [59] ,A7 core0 IRQ[59] masking bit" "Not masked,Masked" bitfld.long 0x14 26. " [58] ,A7 core0 IRQ[58] masking bit" "Not masked,Masked" newline bitfld.long 0x14 25. " [57] ,A7 core0 IRQ[57] masking bit" "Not masked,Masked" bitfld.long 0x14 24. " [56] ,A7 core0 IRQ[56] masking bit" "Not masked,Masked" newline bitfld.long 0x14 23. " [55] ,A7 core0 IRQ[55] masking bit" "Not masked,Masked" bitfld.long 0x14 22. " [54] ,A7 core0 IRQ[54] masking bit" "Not masked,Masked" newline bitfld.long 0x14 21. " [53] ,A7 core0 IRQ[53] masking bit" "Not masked,Masked" bitfld.long 0x14 20. " [52] ,A7 core0 IRQ[52] masking bit" "Not masked,Masked" newline bitfld.long 0x14 19. " [51] ,A7 core0 IRQ[51] masking bit" "Not masked,Masked" bitfld.long 0x14 18. " [50] ,A7 core0 IRQ[50] masking bit" "Not masked,Masked" newline bitfld.long 0x14 17. " [49] ,A7 core0 IRQ[49] masking bit" "Not masked,Masked" bitfld.long 0x14 16. " [48] ,A7 core0 IRQ[48] masking bit" "Not masked,Masked" newline bitfld.long 0x14 15. " [47] ,A7 core0 IRQ[47] masking bit" "Not masked,Masked" bitfld.long 0x14 14. " [46] ,A7 core0 IRQ[46] masking bit" "Not masked,Masked" newline bitfld.long 0x14 13. " [45] ,A7 core0 IRQ[45] masking bit" "Not masked,Masked" bitfld.long 0x14 12. " [44] ,A7 core0 IRQ[44] masking bit" "Not masked,Masked" newline bitfld.long 0x14 11. " [43] ,A7 core0 IRQ[43] masking bit" "Not masked,Masked" bitfld.long 0x14 10. " [42] ,A7 core0 IRQ[42] masking bit" "Not masked,Masked" newline bitfld.long 0x14 9. " [41] ,A7 core0 IRQ[41] masking bit" "Not masked,Masked" bitfld.long 0x14 8. " [40] ,A7 core0 IRQ[40] masking bit" "Not masked,Masked" newline bitfld.long 0x14 7. " [39] ,A7 core0 IRQ[39] masking bit" "Not masked,Masked" bitfld.long 0x14 6. " [38] ,A7 core0 IRQ[38] masking bit" "Not masked,Masked" newline bitfld.long 0x14 5. " [37] ,A7 core0 IRQ[37] masking bit" "Not masked,Masked" bitfld.long 0x14 4. " [36] ,A7 core0 IRQ[36] masking bit" "Not masked,Masked" newline bitfld.long 0x14 3. " [35] ,A7 core0 IRQ[35] masking bit" "Not masked,Masked" bitfld.long 0x14 2. " [34] ,A7 core0 IRQ[34] masking bit" "Not masked,Masked" newline bitfld.long 0x14 1. " [33] ,A7 core0 IRQ[33] masking bit" "Not masked,Masked" bitfld.long 0x14 0. " [32] ,A7 core0 IRQ[32] masking bit" "Not masked,Masked" line.long 0x18 "IMR3_CORE0_A7,IRQ Masking Register 3 Of A7 Core0" bitfld.long 0x18 31. " IMR3_CORE0_A7[95] ,A7 core0 IRQ[95] masking bit" "Not masked,Masked" bitfld.long 0x18 30. " [94] ,A7 core0 IRQ[94] masking bit" "Not masked,Masked" newline bitfld.long 0x18 29. " [93] ,A7 core0 IRQ[93] masking bit" "Not masked,Masked" bitfld.long 0x18 28. " [92] ,A7 core0 IRQ[92] masking bit" "Not masked,Masked" newline bitfld.long 0x18 27. " [91] ,A7 core0 IRQ[91] masking bit" "Not masked,Masked" bitfld.long 0x18 26. " [90] ,A7 core0 IRQ[90] masking bit" "Not masked,Masked" newline bitfld.long 0x18 25. " [89] ,A7 core0 IRQ[89] masking bit" "Not masked,Masked" bitfld.long 0x18 24. " [88] ,A7 core0 IRQ[88] masking bit" "Not masked,Masked" newline bitfld.long 0x18 23. " [87] ,A7 core0 IRQ[87] masking bit" "Not masked,Masked" bitfld.long 0x18 22. " [86] ,A7 core0 IRQ[86] masking bit" "Not masked,Masked" newline bitfld.long 0x18 21. " [85] ,A7 core0 IRQ[85] masking bit" "Not masked,Masked" bitfld.long 0x18 20. " [84] ,A7 core0 IRQ[84] masking bit" "Not masked,Masked" newline bitfld.long 0x18 19. " [83] ,A7 core0 IRQ[83] masking bit" "Not masked,Masked" bitfld.long 0x18 18. " [82] ,A7 core0 IRQ[82] masking bit" "Not masked,Masked" newline bitfld.long 0x18 17. " [81] ,A7 core0 IRQ[81] masking bit" "Not masked,Masked" bitfld.long 0x18 16. " [80] ,A7 core0 IRQ[80] masking bit" "Not masked,Masked" newline bitfld.long 0x18 15. " [79] ,A7 core0 IRQ[79] masking bit" "Not masked,Masked" bitfld.long 0x18 14. " [78] ,A7 core0 IRQ[78] masking bit" "Not masked,Masked" newline bitfld.long 0x18 13. " [77] ,A7 core0 IRQ[77] masking bit" "Not masked,Masked" bitfld.long 0x18 12. " [76] ,A7 core0 IRQ[76] masking bit" "Not masked,Masked" newline bitfld.long 0x18 11. " [75] ,A7 core0 IRQ[75] masking bit" "Not masked,Masked" bitfld.long 0x18 10. " [74] ,A7 core0 IRQ[74] masking bit" "Not masked,Masked" newline bitfld.long 0x18 9. " [73] ,A7 core0 IRQ[73] masking bit" "Not masked,Masked" bitfld.long 0x18 8. " [72] ,A7 core0 IRQ[72] masking bit" "Not masked,Masked" newline bitfld.long 0x18 7. " [71] ,A7 core0 IRQ[71] masking bit" "Not masked,Masked" bitfld.long 0x18 6. " [70] ,A7 core0 IRQ[70] masking bit" "Not masked,Masked" newline bitfld.long 0x18 5. " [69] ,A7 core0 IRQ[69] masking bit" "Not masked,Masked" bitfld.long 0x18 4. " [68] ,A7 core0 IRQ[68] masking bit" "Not masked,Masked" newline bitfld.long 0x18 3. " [67] ,A7 core0 IRQ[67] masking bit" "Not masked,Masked" bitfld.long 0x18 2. " [66] ,A7 core0 IRQ[66] masking bit" "Not masked,Masked" newline bitfld.long 0x18 1. " [65] ,A7 core0 IRQ[65] masking bit" "Not masked,Masked" bitfld.long 0x18 0. " [64] ,A7 core0 IRQ[64] masking bit" "Not masked,Masked" line.long 0x1C "IMR4_CORE0_A7,IRQ Masking Register 4 Of A7 Core0" bitfld.long 0x1C 31. " IMR4_CORE0_A7[127] ,A7 core0 IRQ[127] masking bit" "Not masked,Masked" bitfld.long 0x1C 30. " [126] ,A7 core0 IRQ[126] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 29. " [125] ,A7 core0 IRQ[125] masking bit" "Not masked,Masked" bitfld.long 0x1C 28. " [124] ,A7 core0 IRQ[124] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 27. " [123] ,A7 core0 IRQ[123] masking bit" "Not masked,Masked" bitfld.long 0x1C 26. " [122] ,A7 core0 IRQ[122] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 25. " [121] ,A7 core0 IRQ[121] masking bit" "Not masked,Masked" bitfld.long 0x1C 24. " [120] ,A7 core0 IRQ[120] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 23. " [119] ,A7 core0 IRQ[119] masking bit" "Not masked,Masked" bitfld.long 0x1C 22. " [118] ,A7 core0 IRQ[118] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 21. " [117] ,A7 core0 IRQ[117] masking bit" "Not masked,Masked" bitfld.long 0x1C 20. " [116] ,A7 core0 IRQ[116] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 19. " [115] ,A7 core0 IRQ[115] masking bit" "Not masked,Masked" bitfld.long 0x1C 18. " [114] ,A7 core0 IRQ[114] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 17. " [113] ,A7 core0 IRQ[113] masking bit" "Not masked,Masked" bitfld.long 0x1C 16. " [112] ,A7 core0 IRQ[112] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 15. " [111] ,A7 core0 IRQ[111] masking bit" "Not masked,Masked" bitfld.long 0x1C 14. " [110] ,A7 core0 IRQ[110] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 13. " [109] ,A7 core0 IRQ[109] masking bit" "Not masked,Masked" bitfld.long 0x1C 12. " [108] ,A7 core0 IRQ[108] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 11. " [107] ,A7 core0 IRQ[107] masking bit" "Not masked,Masked" bitfld.long 0x1C 10. " [106] ,A7 core0 IRQ[106] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 9. " [105] ,A7 core0 IRQ[105] masking bit" "Not masked,Masked" bitfld.long 0x1C 8. " [104] ,A7 core0 IRQ[104] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 7. " [103] ,A7 core0 IRQ[103] masking bit" "Not masked,Masked" bitfld.long 0x1C 6. " [102] ,A7 core0 IRQ[102] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 5. " [101] ,A7 core0 IRQ[101] masking bit" "Not masked,Masked" bitfld.long 0x1C 4. " [100] ,A7 core0 IRQ[100] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 3. " [99] ,A7 core0 IRQ[99] masking bit" "Not masked,Masked" bitfld.long 0x1C 2. " [98] ,A7 core0 IRQ[98] masking bit" "Not masked,Masked" newline bitfld.long 0x1C 1. " [97] ,A7 core0 IRQ[97] masking bit" "Not masked,Masked" bitfld.long 0x1C 0. " [96] ,A7 core0 IRQ[96] masking bit" "Not masked,Masked" line.long 0x20 "IMR1_CORE1_A7,IRQ Masking Register 1 Of A7 Core1" bitfld.long 0x20 31. " IMR1_CORE1_A7[31] ,A7 core1 IRQ[31] masking bit" "Not masked,Masked" bitfld.long 0x20 30. " [30] ,A7 core1 IRQ[30] masking bit" "Not masked,Masked" newline bitfld.long 0x20 29. " [29] ,A7 core1 IRQ[29] masking bit" "Not masked,Masked" bitfld.long 0x20 28. " [28] ,A7 core1 IRQ[28] masking bit" "Not masked,Masked" newline bitfld.long 0x20 27. " [27] ,A7 core1 IRQ[27] masking bit" "Not masked,Masked" bitfld.long 0x20 26. " [26] ,A7 core1 IRQ[26] masking bit" "Not masked,Masked" newline bitfld.long 0x20 25. " [25] ,A7 core1 IRQ[25] masking bit" "Not masked,Masked" bitfld.long 0x20 24. " [24] ,A7 core1 IRQ[24] masking bit" "Not masked,Masked" newline bitfld.long 0x20 23. " [23] ,A7 core1 IRQ[23] masking bit" "Not masked,Masked" bitfld.long 0x20 22. " [22] ,A7 core1 IRQ[22] masking bit" "Not masked,Masked" newline bitfld.long 0x20 21. " [21] ,A7 core1 IRQ[21] masking bit" "Not masked,Masked" bitfld.long 0x20 20. " [20] ,A7 core1 IRQ[20] masking bit" "Not masked,Masked" newline bitfld.long 0x20 19. " [19] ,A7 core1 IRQ[19] masking bit" "Not masked,Masked" bitfld.long 0x20 18. " [18] ,A7 core1 IRQ[18] masking bit" "Not masked,Masked" newline bitfld.long 0x20 17. " [17] ,A7 core1 IRQ[17] masking bit" "Not masked,Masked" bitfld.long 0x20 16. " [16] ,A7 core1 IRQ[16] masking bit" "Not masked,Masked" newline bitfld.long 0x20 15. " [15] ,A7 core1 IRQ[15] masking bit" "Not masked,Masked" bitfld.long 0x20 14. " [14] ,A7 core1 IRQ[14] masking bit" "Not masked,Masked" newline bitfld.long 0x20 13. " [13] ,A7 core1 IRQ[13] masking bit" "Not masked,Masked" bitfld.long 0x20 12. " [12] ,A7 core1 IRQ[12] masking bit" "Not masked,Masked" newline bitfld.long 0x20 11. " [11] ,A7 core1 IRQ[11] masking bit" "Not masked,Masked" bitfld.long 0x20 10. " [10] ,A7 core1 IRQ[10] masking bit" "Not masked,Masked" newline bitfld.long 0x20 9. " [9] ,A7 core1 IRQ[9] masking bit" "Not masked,Masked" bitfld.long 0x20 8. " [8] ,A7 core1 IRQ[8] masking bit" "Not masked,Masked" newline bitfld.long 0x20 7. " [7] ,A7 core1 IRQ[7] masking bit" "Not masked,Masked" bitfld.long 0x20 6. " [6] ,A7 core1 IRQ[6] masking bit" "Not masked,Masked" newline bitfld.long 0x20 5. " [5] ,A7 core1 IRQ[5] masking bit" "Not masked,Masked" bitfld.long 0x20 4. " [4] ,A7 core1 IRQ[4] masking bit" "Not masked,Masked" newline bitfld.long 0x20 3. " [3] ,A7 core1 IRQ[3] masking bit" "Not masked,Masked" bitfld.long 0x20 2. " [2] ,A7 core1 IRQ[2] masking bit" "Not masked,Masked" newline bitfld.long 0x20 1. " [1] ,A7 core1 IRQ[1] masking bit" "Not masked,Masked" bitfld.long 0x20 0. " [0] ,A7 core1 IRQ[0] masking bit" "Not masked,Masked" line.long 0x24 "IMR2_CORE1_A7,IRQ Masking Register 2 Of A7 Core1" bitfld.long 0x24 31. " IMR2_CORE1_A7[63] ,A7 core1 IRQ[63] masking bit" "Not masked,Masked" bitfld.long 0x24 30. " [62] ,A7 core1 IRQ[62] masking bit" "Not masked,Masked" newline bitfld.long 0x24 29. " [61] ,A7 core1 IRQ[61] masking bit" "Not masked,Masked" bitfld.long 0x24 28. " [60] ,A7 core1 IRQ[60] masking bit" "Not masked,Masked" newline bitfld.long 0x24 27. " [59] ,A7 core1 IRQ[59] masking bit" "Not masked,Masked" bitfld.long 0x24 26. " [58] ,A7 core1 IRQ[58] masking bit" "Not masked,Masked" newline bitfld.long 0x24 25. " [57] ,A7 core1 IRQ[57] masking bit" "Not masked,Masked" bitfld.long 0x24 24. " [56] ,A7 core1 IRQ[56] masking bit" "Not masked,Masked" newline bitfld.long 0x24 23. " [55] ,A7 core1 IRQ[55] masking bit" "Not masked,Masked" bitfld.long 0x24 22. " [54] ,A7 core1 IRQ[54] masking bit" "Not masked,Masked" newline bitfld.long 0x24 21. " [53] ,A7 core1 IRQ[53] masking bit" "Not masked,Masked" bitfld.long 0x24 20. " [52] ,A7 core1 IRQ[52] masking bit" "Not masked,Masked" newline bitfld.long 0x24 19. " [51] ,A7 core1 IRQ[51] masking bit" "Not masked,Masked" bitfld.long 0x24 18. " [50] ,A7 core1 IRQ[50] masking bit" "Not masked,Masked" newline bitfld.long 0x24 17. " [49] ,A7 core1 IRQ[49] masking bit" "Not masked,Masked" bitfld.long 0x24 16. " [48] ,A7 core1 IRQ[48] masking bit" "Not masked,Masked" newline bitfld.long 0x24 15. " [47] ,A7 core1 IRQ[47] masking bit" "Not masked,Masked" bitfld.long 0x24 14. " [46] ,A7 core1 IRQ[46] masking bit" "Not masked,Masked" newline bitfld.long 0x24 13. " [45] ,A7 core1 IRQ[45] masking bit" "Not masked,Masked" bitfld.long 0x24 12. " [44] ,A7 core1 IRQ[44] masking bit" "Not masked,Masked" newline bitfld.long 0x24 11. " [43] ,A7 core1 IRQ[43] masking bit" "Not masked,Masked" bitfld.long 0x24 10. " [42] ,A7 core1 IRQ[42] masking bit" "Not masked,Masked" newline bitfld.long 0x24 9. " [41] ,A7 core1 IRQ[41] masking bit" "Not masked,Masked" bitfld.long 0x24 8. " [40] ,A7 core1 IRQ[40] masking bit" "Not masked,Masked" newline bitfld.long 0x24 7. " [39] ,A7 core1 IRQ[39] masking bit" "Not masked,Masked" bitfld.long 0x24 6. " [38] ,A7 core1 IRQ[38] masking bit" "Not masked,Masked" newline bitfld.long 0x24 5. " [37] ,A7 core1 IRQ[37] masking bit" "Not masked,Masked" bitfld.long 0x24 4. " [36] ,A7 core1 IRQ[36] masking bit" "Not masked,Masked" newline bitfld.long 0x24 3. " [35] ,A7 core1 IRQ[35] masking bit" "Not masked,Masked" bitfld.long 0x24 2. " [34] ,A7 core1 IRQ[34] masking bit" "Not masked,Masked" newline bitfld.long 0x24 1. " [33] ,A7 core1 IRQ[33] masking bit" "Not masked,Masked" bitfld.long 0x24 0. " [32] ,A7 core1 IRQ[32] masking bit" "Not masked,Masked" line.long 0x28 "IMR3_CORE1_A7,IRQ Masking Register 3 Of A7 Core1" bitfld.long 0x28 31. " IMR3_CORE1_A7[95] ,A7 core1 IRQ[95] masking bit" "Not masked,Masked" bitfld.long 0x28 30. " [94] ,A7 core1 IRQ[94] masking bit" "Not masked,Masked" newline bitfld.long 0x28 29. " [93] ,A7 core1 IRQ[93] masking bit" "Not masked,Masked" bitfld.long 0x28 28. " [92] ,A7 core1 IRQ[92] masking bit" "Not masked,Masked" newline bitfld.long 0x28 27. " [91] ,A7 core1 IRQ[91] masking bit" "Not masked,Masked" bitfld.long 0x28 26. " [90] ,A7 core1 IRQ[90] masking bit" "Not masked,Masked" newline bitfld.long 0x28 25. " [89] ,A7 core1 IRQ[89] masking bit" "Not masked,Masked" bitfld.long 0x28 24. " [88] ,A7 core1 IRQ[88] masking bit" "Not masked,Masked" newline bitfld.long 0x28 23. " [87] ,A7 core1 IRQ[87] masking bit" "Not masked,Masked" bitfld.long 0x28 22. " [86] ,A7 core1 IRQ[86] masking bit" "Not masked,Masked" newline bitfld.long 0x28 21. " [85] ,A7 core1 IRQ[85] masking bit" "Not masked,Masked" bitfld.long 0x28 20. " [84] ,A7 core1 IRQ[84] masking bit" "Not masked,Masked" newline bitfld.long 0x28 19. " [83] ,A7 core1 IRQ[83] masking bit" "Not masked,Masked" bitfld.long 0x28 18. " [82] ,A7 core1 IRQ[82] masking bit" "Not masked,Masked" newline bitfld.long 0x28 17. " [81] ,A7 core1 IRQ[81] masking bit" "Not masked,Masked" bitfld.long 0x28 16. " [80] ,A7 core1 IRQ[80] masking bit" "Not masked,Masked" newline bitfld.long 0x28 15. " [79] ,A7 core1 IRQ[79] masking bit" "Not masked,Masked" bitfld.long 0x28 14. " [78] ,A7 core1 IRQ[78] masking bit" "Not masked,Masked" newline bitfld.long 0x28 13. " [77] ,A7 core1 IRQ[77] masking bit" "Not masked,Masked" bitfld.long 0x28 12. " [76] ,A7 core1 IRQ[76] masking bit" "Not masked,Masked" newline bitfld.long 0x28 11. " [75] ,A7 core1 IRQ[75] masking bit" "Not masked,Masked" bitfld.long 0x28 10. " [74] ,A7 core1 IRQ[74] masking bit" "Not masked,Masked" newline bitfld.long 0x28 9. " [73] ,A7 core1 IRQ[73] masking bit" "Not masked,Masked" bitfld.long 0x28 8. " [72] ,A7 core1 IRQ[72] masking bit" "Not masked,Masked" newline bitfld.long 0x28 7. " [71] ,A7 core1 IRQ[71] masking bit" "Not masked,Masked" bitfld.long 0x28 6. " [70] ,A7 core1 IRQ[70] masking bit" "Not masked,Masked" newline bitfld.long 0x28 5. " [69] ,A7 core1 IRQ[69] masking bit" "Not masked,Masked" bitfld.long 0x28 4. " [68] ,A7 core1 IRQ[68] masking bit" "Not masked,Masked" newline bitfld.long 0x28 3. " [67] ,A7 core1 IRQ[67] masking bit" "Not masked,Masked" bitfld.long 0x28 2. " [66] ,A7 core1 IRQ[66] masking bit" "Not masked,Masked" newline bitfld.long 0x28 1. " [65] ,A7 core1 IRQ[65] masking bit" "Not masked,Masked" bitfld.long 0x28 0. " [64] ,A7 core1 IRQ[64] masking bit" "Not masked,Masked" line.long 0x2C "IMR4_CORE1_A7,IRQ Masking Register 4 Of A7 Core1" bitfld.long 0x2C 31. " IMR4_CORE1_A7[127] ,A7 core1 IRQ[127] masking bit" "Not masked,Masked" bitfld.long 0x2C 30. " [126] ,A7 core1 IRQ[126] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 29. " [125] ,A7 core1 IRQ[125] masking bit" "Not masked,Masked" bitfld.long 0x2C 28. " [124] ,A7 core1 IRQ[124] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 27. " [123] ,A7 core1 IRQ[123] masking bit" "Not masked,Masked" bitfld.long 0x2C 26. " [122] ,A7 core1 IRQ[122] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 25. " [121] ,A7 core1 IRQ[121] masking bit" "Not masked,Masked" bitfld.long 0x2C 24. " [120] ,A7 core1 IRQ[120] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 23. " [119] ,A7 core1 IRQ[119] masking bit" "Not masked,Masked" bitfld.long 0x2C 22. " [118] ,A7 core1 IRQ[118] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 21. " [117] ,A7 core1 IRQ[117] masking bit" "Not masked,Masked" bitfld.long 0x2C 20. " [116] ,A7 core1 IRQ[116] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 19. " [115] ,A7 core1 IRQ[115] masking bit" "Not masked,Masked" bitfld.long 0x2C 18. " [114] ,A7 core1 IRQ[114] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 17. " [113] ,A7 core1 IRQ[113] masking bit" "Not masked,Masked" bitfld.long 0x2C 16. " [112] ,A7 core1 IRQ[112] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 15. " [111] ,A7 core1 IRQ[111] masking bit" "Not masked,Masked" bitfld.long 0x2C 14. " [110] ,A7 core1 IRQ[110] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 13. " [109] ,A7 core1 IRQ[109] masking bit" "Not masked,Masked" bitfld.long 0x2C 12. " [108] ,A7 core1 IRQ[108] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 11. " [107] ,A7 core1 IRQ[107] masking bit" "Not masked,Masked" bitfld.long 0x2C 10. " [106] ,A7 core1 IRQ[106] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 9. " [105] ,A7 core1 IRQ[105] masking bit" "Not masked,Masked" bitfld.long 0x2C 8. " [104] ,A7 core1 IRQ[104] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 7. " [103] ,A7 core1 IRQ[103] masking bit" "Not masked,Masked" bitfld.long 0x2C 6. " [102] ,A7 core1 IRQ[102] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 5. " [101] ,A7 core1 IRQ[101] masking bit" "Not masked,Masked" bitfld.long 0x2C 4. " [100] ,A7 core1 IRQ[100] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 3. " [99] ,A7 core1 IRQ[99] masking bit" "Not masked,Masked" bitfld.long 0x2C 2. " [98] ,A7 core1 IRQ[98] masking bit" "Not masked,Masked" newline bitfld.long 0x2C 1. " [97] ,A7 core1 IRQ[97] masking bit" "Not masked,Masked" bitfld.long 0x2C 0. " [96] ,A7 core1 IRQ[96] masking bit" "Not masked,Masked" group.long 0x50++0x0F line.long 0x00 "IMR1_M4,IRQ Masking Register 1 Of M4" bitfld.long 0x00 31. " IMR1_M4[31] ,M4 IRQ[31] masking bit" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,M4 IRQ[30] masking bit" "Not masked,Masked" newline bitfld.long 0x00 29. " I[29] ,M4 IRQ[29] masking bit" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,M4 IRQ[28] masking bit" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,M4 IRQ[27] masking bit" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,M4 IRQ[26] masking bit" "Not masked,Masked" newline bitfld.long 0x00 25. " [25] ,M4 IRQ[25] masking bit" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,M4 IRQ[24] masking bit" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,M4 IRQ[23] masking bit" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,M4 IRQ[22] masking bit" "Not masked,Masked" newline bitfld.long 0x00 21. " [21] ,M4 IRQ[21] masking bit" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,M4 IRQ[20] masking bit" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,M4 IRQ[19] masking bit" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,M4 IRQ[18] masking bit" "Not masked,Masked" newline bitfld.long 0x00 17. " [17] ,M4 IRQ[17] masking bit" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,M4 IRQ[16] masking bit" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,M4 IRQ[15] masking bit" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,M4 IRQ[14] masking bit" "Not masked,Masked" newline bitfld.long 0x00 13. " [13] ,M4 IRQ[13] masking bit" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,M4 IRQ[12] masking bit" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,M4 IRQ[11] masking bit" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,M4 IRQ[10] masking bit" "Not masked,Masked" newline bitfld.long 0x00 9. " [9] ,M4 IRQ[9] masking bit" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,M4 IRQ[8] masking bit" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,M4 IRQ[7] masking bit" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,M4 IRQ[6] masking bit" "Not masked,Masked" newline bitfld.long 0x00 5. " [5] ,M4 IRQ[5] masking bit" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,M4 IRQ[4] masking bit" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,M4 IRQ[3] masking bit" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,M4 IRQ[2] masking bit" "Not masked,Masked" newline bitfld.long 0x00 1. " [1] ,M4 IRQ[1] masking bit" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,M4 IRQ[0] masking bit" "Not masked,Masked" line.long 0x04 "IMR2_M4,IRQ Masking Register 2 Of M4" bitfld.long 0x04 31. " IMR2_M4[63] ,M4 IRQ[63] masking bit" "Not masked,Masked" bitfld.long 0x04 30. " [62] ,M4 IRQ[62] masking bit" "Not masked,Masked" newline bitfld.long 0x04 29. " [61] ,M4 IRQ[61] masking bit" "Not masked,Masked" bitfld.long 0x04 28. " [60] ,M4 IRQ[60] masking bit" "Not masked,Masked" newline bitfld.long 0x04 27. " [59] ,M4 IRQ[59] masking bit" "Not masked,Masked" bitfld.long 0x04 26. " [58] ,M4 IRQ[58] masking bit" "Not masked,Masked" newline bitfld.long 0x04 25. " [57] ,M4 IRQ[57] masking bit" "Not masked,Masked" bitfld.long 0x04 24. " [56] ,M4 IRQ[56] masking bit" "Not masked,Masked" newline bitfld.long 0x04 23. " [55] ,M4 IRQ[55] masking bit" "Not masked,Masked" bitfld.long 0x04 22. " [54] ,M4 IRQ[54] masking bit" "Not masked,Masked" newline bitfld.long 0x04 21. " [53] ,M4 IRQ[53] masking bit" "Not masked,Masked" bitfld.long 0x04 20. " [52] ,M4 IRQ[52] masking bit" "Not masked,Masked" newline bitfld.long 0x04 19. " [51] ,M4 IRQ[51] masking bit" "Not masked,Masked" bitfld.long 0x04 18. " [50] ,M4 IRQ[50] masking bit" "Not masked,Masked" newline bitfld.long 0x04 17. " [49] ,M4 IRQ[49] masking bit" "Not masked,Masked" bitfld.long 0x04 16. " [48] ,M4 IRQ[48] masking bit" "Not masked,Masked" newline bitfld.long 0x04 15. " [47] ,M4 IRQ[47] masking bit" "Not masked,Masked" bitfld.long 0x04 14. " [46] ,M4 IRQ[46] masking bit" "Not masked,Masked" newline bitfld.long 0x04 13. " [45] ,M4 IRQ[45] masking bit" "Not masked,Masked" bitfld.long 0x04 12. " [44] ,M4 IRQ[44] masking bit" "Not masked,Masked" newline bitfld.long 0x04 11. " [43] ,M4 IRQ[43] masking bit" "Not masked,Masked" bitfld.long 0x04 10. " [42] ,M4 IRQ[42] masking bit" "Not masked,Masked" newline bitfld.long 0x04 9. " [41] ,M4 IRQ[41] masking bit" "Not masked,Masked" bitfld.long 0x04 8. " [40] ,M4 IRQ[40] masking bit" "Not masked,Masked" newline bitfld.long 0x04 7. " [39] ,M4 IRQ[39] masking bit" "Not masked,Masked" bitfld.long 0x04 6. " [38] ,M4 IRQ[38] masking bit" "Not masked,Masked" newline bitfld.long 0x04 5. " [37] ,M4 IRQ[37] masking bit" "Not masked,Masked" bitfld.long 0x04 4. " [36] ,M4 IRQ[36] masking bit" "Not masked,Masked" newline bitfld.long 0x04 3. " [35] ,M4 IRQ[35] masking bit" "Not masked,Masked" bitfld.long 0x04 2. " [34] ,M4 IRQ[34] masking bit" "Not masked,Masked" newline bitfld.long 0x04 1. " [33] ,M4 IRQ[33] masking bit" "Not masked,Masked" bitfld.long 0x04 0. " [32] ,M4 IRQ[32] masking bit" "Not masked,Masked" line.long 0x08 "IMR3_M4,IRQ Masking Register 3 Of M4" bitfld.long 0x08 31. " IMR3_M4[95] ,M4 IRQ[95] masking bit" "Not masked,Masked" bitfld.long 0x08 30. " [94] ,M4 IRQ[94] masking bit" "Not masked,Masked" newline bitfld.long 0x08 29. " [93] ,M4 IRQ[93] masking bit" "Not masked,Masked" bitfld.long 0x08 28. " [92] ,M4 IRQ[92] masking bit" "Not masked,Masked" newline bitfld.long 0x08 27. " [91] ,M4 IRQ[91] masking bit" "Not masked,Masked" bitfld.long 0x08 26. " [90] ,M4 IRQ[90] masking bit" "Not masked,Masked" newline bitfld.long 0x08 25. " [89] ,M4 IRQ[89] masking bit" "Not masked,Masked" bitfld.long 0x08 24. " [88] ,M4 IRQ[88] masking bit" "Not masked,Masked" newline bitfld.long 0x08 23. " [87] ,M4 IRQ[87] masking bit" "Not masked,Masked" bitfld.long 0x08 22. " [86] ,M4 IRQ[86] masking bit" "Not masked,Masked" newline bitfld.long 0x08 21. " [85] ,M4 IRQ[85] masking bit" "Not masked,Masked" bitfld.long 0x08 20. " [84] ,M4 IRQ[84] masking bit" "Not masked,Masked" newline bitfld.long 0x08 19. " [83] ,M4 IRQ[83] masking bit" "Not masked,Masked" bitfld.long 0x08 18. " [82] ,M4 IRQ[82] masking bit" "Not masked,Masked" newline bitfld.long 0x08 17. " [81] ,M4 IRQ[81] masking bit" "Not masked,Masked" bitfld.long 0x08 16. " [80] ,M4 IRQ[80] masking bit" "Not masked,Masked" newline bitfld.long 0x08 15. " [79] ,M4 IRQ[79] masking bit" "Not masked,Masked" bitfld.long 0x08 14. " [78] ,M4 IRQ[78] masking bit" "Not masked,Masked" newline bitfld.long 0x08 13. " [77] ,M4 IRQ[77] masking bit" "Not masked,Masked" bitfld.long 0x08 12. " [76] ,M4 IRQ[76] masking bit" "Not masked,Masked" newline bitfld.long 0x08 11. " [75] ,M4 IRQ[75] masking bit" "Not masked,Masked" bitfld.long 0x08 10. " [74] ,M4 IRQ[74] masking bit" "Not masked,Masked" newline bitfld.long 0x08 9. " [73] ,M4 IRQ[73] masking bit" "Not masked,Masked" bitfld.long 0x08 8. " [72] ,M4 IRQ[72] masking bit" "Not masked,Masked" newline bitfld.long 0x08 7. " [71] ,M4 IRQ[71] masking bit" "Not masked,Masked" bitfld.long 0x08 6. " [70] ,M4 IRQ[70] masking bit" "Not masked,Masked" newline bitfld.long 0x08 5. " [69] ,M4 IRQ[69] masking bit" "Not masked,Masked" bitfld.long 0x08 4. " [68] ,M4 IRQ[68] masking bit" "Not masked,Masked" newline bitfld.long 0x08 3. " [67] ,M4 IRQ[67] masking bit" "Not masked,Masked" bitfld.long 0x08 2. " [66] ,M4 IRQ[66] masking bit" "Not masked,Masked" newline bitfld.long 0x08 1. " [65] ,M4 IRQ[65] masking bit" "Not masked,Masked" bitfld.long 0x08 0. " [64] ,M4 IRQ[64] masking bit" "Not masked,Masked" line.long 0x0C "IMR4_M4,IRQ Masking Register 4 Of M4" bitfld.long 0x0C 31. " IMR4_M4[127] ,M4 IRQ[127] masking bit" "Not masked,Masked" bitfld.long 0x0C 30. " [126] ,M4 IRQ[126] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 29. " [125] ,M4 IRQ[125] masking bit" "Not masked,Masked" bitfld.long 0x0C 28. " [124] ,M4 IRQ[124] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 27. " [123] ,M4 IRQ[123] masking bit" "Not masked,Masked" bitfld.long 0x0C 26. " [122] ,M4 IRQ[122] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 25. " [121] ,M4 IRQ[121] masking bit" "Not masked,Masked" bitfld.long 0x0C 24. " [120] ,M4 IRQ[120] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 23. " [119] ,M4 IRQ[119] masking bit" "Not masked,Masked" bitfld.long 0x0C 22. " [118] ,M4 IRQ[118] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 21. " [117] ,M4 IRQ[117] masking bit" "Not masked,Masked" bitfld.long 0x0C 20. " [116] ,M4 IRQ[116] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 19. " [115] ,M4 IRQ[115] masking bit" "Not masked,Masked" bitfld.long 0x0C 18. " [114] ,M4 IRQ[114] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 17. " [113] ,M4 IRQ[113] masking bit" "Not masked,Masked" bitfld.long 0x0C 16. " [112] ,M4 IRQ[112] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 15. " [111] ,M4 IRQ[111] masking bit" "Not masked,Masked" bitfld.long 0x0C 14. " [110] ,M4 IRQ[110] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 13. " [109] ,M4 IRQ[109] masking bit" "Not masked,Masked" bitfld.long 0x0C 12. " [108] ,M4 IRQ[108] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 11. " [107] ,M4 IRQ[107] masking bit" "Not masked,Masked" bitfld.long 0x0C 10. " [106] ,M4 IRQ[106] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 9. " [105] ,M4 IRQ[105] masking bit" "Not masked,Masked" bitfld.long 0x0C 8. " [104] ,M4 IRQ[104] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 7. " [103] ,M4 IRQ[103] masking bit" "Not masked,Masked" bitfld.long 0x0C 6. " [102] ,M4 IRQ[102] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 5. " [101] ,M4 IRQ[101] masking bit" "Not masked,Masked" bitfld.long 0x0C 4. " [100] ,M4 IRQ[100] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 3. " [99] ,M4 IRQ[99] masking bit" "Not masked,Masked" bitfld.long 0x0C 2. " [98] ,M4 IRQ[98] masking bit" "Not masked,Masked" newline bitfld.long 0x0C 1. " [97] ,M4 IRQ[97] masking bit" "Not masked,Masked" bitfld.long 0x0C 0. " [96] ,M4 IRQ[96] masking bit" "Not masked,Masked" rgroup.long 0x70++0x1F line.long 0x00 "ISR1_A7,IRQ Status Register 1 Of A7" bitfld.long 0x00 31. " ISR1_A7[31] ,A7 IRQ[31] status bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,A7 IRQ[30] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 29. " [29] ,A7 IRQ[29] status bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,A7 IRQ[28] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,A7 IRQ[27] status bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,A7 IRQ[26] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 25. " [25] ,A7 IRQ[25] status bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,A7 IRQ[24] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,A7 IRQ[23] status bit" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,A7 IRQ[22] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 21. " [21] ,A7 IRQ[21] status bit" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,A7 IRQ[20] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,A7 IRQ[19] status bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,A7 IRQ[18] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 17. " [17] ,A7 IRQ[17] status bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,A7 IRQ[16] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,A7 IRQ[15] status bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,A7 IRQ[14] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 13. " [13] ,A7 IRQ[13] status bit" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,A7 IRQ[12] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,A7 IRQ[11] status bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,A7 IRQ[10] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " [9] ,A7 IRQ[9] status bit" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,A7 IRQ[8] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,A7 IRQ[7] status bit" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,A7 IRQ[6] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " [5] ,A7 IRQ[5] status bit" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,A7 IRQ[4] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,A7 IRQ[3] status bit" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,A7 IRQ[2] status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " [1] ,A7 IRQ[1] status bit" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,A7 IRQ[0] status bit" "No interrupt,Interrupt" line.long 0x04 "ISR2_A7,IRQ Status Register 2 Of A7" bitfld.long 0x04 31. " ISR2_A7[63] ,A7 IRQ[63] status bit" "No interrupt,Interrupt" bitfld.long 0x04 30. " [62] ,A7 IRQ[62] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 29. " [61] ,A7 IRQ[61] status bit" "No interrupt,Interrupt" bitfld.long 0x04 28. " [60] ,A7 IRQ[60] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [59] ,A7 IRQ[59] status bit" "No interrupt,Interrupt" bitfld.long 0x04 26. " [58] ,A7 IRQ[58] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 25. " [57] ,A7 IRQ[57] status bit" "No interrupt,Interrupt" bitfld.long 0x04 24. " [56] ,A7 IRQ[56] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " [55] ,A7 IRQ[55] status bit" "No interrupt,Interrupt" bitfld.long 0x04 22. " [54] ,A7 IRQ[54] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 21. " [53] ,A7 IRQ[53] status bit" "No interrupt,Interrupt" bitfld.long 0x04 20. " [52] ,A7 IRQ[52] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " [51] ,A7 IRQ[51] status bit" "No interrupt,Interrupt" bitfld.long 0x04 18. " [50] ,A7 IRQ[50] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 17. " [49] ,A7 IRQ[49] status bit" "No interrupt,Interrupt" bitfld.long 0x04 16. " [48] ,A7 IRQ[48] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " [47] ,A7 IRQ[47] status bit" "No interrupt,Interrupt" bitfld.long 0x04 14. " [46] ,A7 IRQ[46] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 13. " [45] ,A7 IRQ[45] status bit" "No interrupt,Interrupt" bitfld.long 0x04 12. " [44] ,A7 IRQ[44] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 11. " [43] ,A7 IRQ[43] status bit" "No interrupt,Interrupt" bitfld.long 0x04 10. " [42] ,A7 IRQ[42] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 9. " [41] ,A7 IRQ[41] status bit" "No interrupt,Interrupt" bitfld.long 0x04 8. " [40] ,A7 IRQ[40] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 7. " [39] ,A7 IRQ[39] status bit" "No interrupt,Interrupt" bitfld.long 0x04 6. " [38] ,A7 IRQ[38] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 5. " [37] ,A7 IRQ[37] status bit" "No interrupt,Interrupt" bitfld.long 0x04 4. " [36] ,A7 IRQ[36] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 3. " [35] ,A7 IRQ[35] status bit" "No interrupt,Interrupt" bitfld.long 0x04 2. " [34] ,A7 IRQ[34] status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 1. " [33] ,A7 IRQ[33] status bit" "No interrupt,Interrupt" bitfld.long 0x04 0. " [32] ,A7 IRQ[32] status bit" "No interrupt,Interrupt" line.long 0x08 "ISR3_A7,IRQ Status Register 3 Of A7" bitfld.long 0x08 31. " ISR3_A7[95] ,A7 IRQ[95] status bit" "No interrupt,Interrupt" bitfld.long 0x08 30. " [94] ,A7 IRQ[94] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 29. " [93] ,A7 IRQ[93] status bit" "No interrupt,Interrupt" bitfld.long 0x08 28. " [92] ,A7 IRQ[92] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 27. " [91] ,A7 IRQ[91] status bit" "No interrupt,Interrupt" bitfld.long 0x08 26. " [90] ,A7 IRQ[90] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 25. " [89] ,A7 IRQ[89] status bit" "No interrupt,Interrupt" bitfld.long 0x08 24. " [88] ,A7 IRQ[88] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " [87] ,A7 IRQ[87] status bit" "No interrupt,Interrupt" bitfld.long 0x08 22. " [86] ,A7 IRQ[86] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 21. " [85] ,A7 IRQ[85] status bit" "No interrupt,Interrupt" bitfld.long 0x08 20. " [84] ,A7 IRQ[84] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " [83] ,A7 IRQ[83] status bit" "No interrupt,Interrupt" bitfld.long 0x08 18. " [82] ,A7 IRQ[82] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 17. " [81] ,A7 IRQ[81] status bit" "No interrupt,Interrupt" bitfld.long 0x08 16. " [80] ,A7 IRQ[80] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " [79] ,A7 IRQ[79] status bit" "No interrupt,Interrupt" bitfld.long 0x08 14. " [78] ,A7 IRQ[78] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 13. " [77] ,A7 IRQ[77] status bit" "No interrupt,Interrupt" bitfld.long 0x08 12. " [76] ,A7 IRQ[76] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " [75] ,A7 IRQ[75] status bit" "No interrupt,Interrupt" bitfld.long 0x08 10. " [74] ,A7 IRQ[74] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 9. " [73] ,A7 IRQ[73] status bit" "No interrupt,Interrupt" bitfld.long 0x08 8. " [72] ,A7 IRQ[72] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 7. " [71] ,A7 IRQ[71] status bit" "No interrupt,Interrupt" bitfld.long 0x08 6. " [70] ,A7 IRQ[70] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 5. " [69] ,A7 IRQ[69] status bit" "No interrupt,Interrupt" bitfld.long 0x08 4. " [68] ,A7 IRQ[68] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 3. " [67] ,A7 IRQ[67] status bit" "No interrupt,Interrupt" bitfld.long 0x08 2. " [66] ,A7 IRQ[66] status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 1. " [65] ,A7 IRQ[65] status bit" "No interrupt,Interrupt" bitfld.long 0x08 0. " [64] ,A7 IRQ[64] status bit" "No interrupt,Interrupt" line.long 0x0C "ISR4_A7,IRQ Status Register 4 Of A7" bitfld.long 0x0C 31. " ISR4_A7[127] ,A7 IRQ[127] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 30. " [126] ,A7 IRQ[126] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 29. " [125] ,A7 IRQ[125] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 28. " [124] ,A7 IRQ[124] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 27. " [123] ,A7 IRQ[123] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 26. " [122] ,A7 IRQ[122] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " [121] ,A7 IRQ[121] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 24. " [120] ,A7 IRQ[120] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 23. " [119] ,A7 IRQ[119] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 22. " [118] ,A7 IRQ[118] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 21. " [117] ,A7 IRQ[117] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 20. " [116] ,A7 IRQ[116] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 19. " [115] ,A7 IRQ[115] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 18. " [114] ,A7 IRQ[114] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 17. " [113] ,A7 IRQ[113] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16. " [112] ,A7 IRQ[112] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 15. " [111] ,A7 IRQ[111] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 14. " [110] ,A7 IRQ[110] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 13. " [109] ,A7 IRQ[109] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 12. " [108] ,A7 IRQ[108] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 11. " [107] ,A7 IRQ[107] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 10. " [106] ,A7 IRQ[106] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 9. " [105] ,A7 IRQ[105] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 8. " [104] ,A7 IRQ[104] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 7. " [103] ,A7 IRQ[103] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 6. " [102] ,A7 IRQ[102] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " [101] ,A7 IRQ[101] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 4. " [100] ,A7 IRQ[100] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " [99] ,A7 IRQ[99] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 2. " [98] ,A7 IRQ[98] status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " [97] ,A7 IRQ[97] status bit" "No interrupt,Interrupt" bitfld.long 0x0C 0. " [96] ,A7 IRQ[96] status bit" "No interrupt,Interrupt" line.long 0x10 "ISR1_M4,IRQ Status Register 1 Of M4" bitfld.long 0x10 31. " ISR1_M4[31] ,M4 IRQ[31] status bit" "No interrupt,Interrupt" bitfld.long 0x10 30. " [30] ,M4 IRQ[30] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 29. " [29] ,M4 IRQ[29] status bit" "No interrupt,Interrupt" bitfld.long 0x10 28. " [28] ,M4 IRQ[28] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 27. " [27] ,M4 IRQ[27] status bit" "No interrupt,Interrupt" bitfld.long 0x10 26. " [26] ,M4 IRQ[26] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 25. " [25] ,M4 IRQ[25] status bit" "No interrupt,Interrupt" bitfld.long 0x10 24. " [24] ,M4 IRQ[24] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 23. " [23] ,M4 IRQ[23] status bit" "No interrupt,Interrupt" bitfld.long 0x10 22. " [22] ,M4 IRQ[22] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 21. " [21] ,M4 IRQ[21] status bit" "No interrupt,Interrupt" bitfld.long 0x10 20. " [20] ,M4 IRQ[20] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 19. " [19] ,M4 IRQ[19] status bit" "No interrupt,Interrupt" bitfld.long 0x10 18. " [18] ,M4 IRQ[18] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 17. " [17] ,M4 IRQ[17] status bit" "No interrupt,Interrupt" bitfld.long 0x10 16. " [16] ,M4 IRQ[16] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 15. " [15] ,M4 IRQ[15] status bit" "No interrupt,Interrupt" bitfld.long 0x10 14. " [14] ,M4 IRQ[14] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 13. " [13] ,M4 IRQ[13] status bit" "No interrupt,Interrupt" bitfld.long 0x10 12. " [12] ,M4 IRQ[12] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 11. " [11] ,M4 IRQ[11] status bit" "No interrupt,Interrupt" bitfld.long 0x10 10. " [10] ,M4 IRQ[10] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 9. " [9] ,M4 IRQ[9] status bit" "No interrupt,Interrupt" bitfld.long 0x10 8. " [8] ,M4 IRQ[8] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 7. " [7] ,M4 IRQ[7] status bit" "No interrupt,Interrupt" bitfld.long 0x10 6. " [6] ,M4 IRQ[6] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 5. " [5] ,M4 IRQ[5] status bit" "No interrupt,Interrupt" bitfld.long 0x10 4. " [4] ,M4 IRQ[4] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 3. " [3] ,M4 IRQ[3] status bit" "No interrupt,Interrupt" bitfld.long 0x10 2. " [2] ,M4 IRQ[2] status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 1. " [1] ,M4 IRQ[1] status bit" "No interrupt,Interrupt" bitfld.long 0x10 0. " [0] ,M4 IRQ[0] status bit" "No interrupt,Interrupt" line.long 0x14 "ISR2_M4,IRQ Status Register 2 Of M4" bitfld.long 0x14 31. " ISR2_M4[63] ,M4 IRQ[63] status bit" "No interrupt,Interrupt" bitfld.long 0x14 30. " [62] ,M4 IRQ[62] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 29. " [61] ,M4 IRQ[61] status bit" "No interrupt,Interrupt" bitfld.long 0x14 28. " [60] ,M4 IRQ[60] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 27. " [59] ,M4 IRQ[59] status bit" "No interrupt,Interrupt" bitfld.long 0x14 26. " [58] ,M4 IRQ[58] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 25. " [57] ,M4 IRQ[57] status bit" "No interrupt,Interrupt" bitfld.long 0x14 24. " [56] ,M4 IRQ[56] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 23. " [55] ,M4 IRQ[55] status bit" "No interrupt,Interrupt" bitfld.long 0x14 22. " [54] ,M4 IRQ[54] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 21. " [53] ,M4 IRQ[53] status bit" "No interrupt,Interrupt" bitfld.long 0x14 20. " [52] ,M4 IRQ[52] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 19. " [51] ,M4 IRQ[51] status bit" "No interrupt,Interrupt" bitfld.long 0x14 18. " [50] ,M4 IRQ[50] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 17. " [49] ,M4 IRQ[49] status bit" "No interrupt,Interrupt" bitfld.long 0x14 16. " [48] ,M4 IRQ[48] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " [47] ,M4 IRQ[47] status bit" "No interrupt,Interrupt" bitfld.long 0x14 14. " [46] ,M4 IRQ[46] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 13. " [45] ,M4 IRQ[45] status bit" "No interrupt,Interrupt" bitfld.long 0x14 12. " [44] ,M4 IRQ[44] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " [43] ,M4 IRQ[43] status bit" "No interrupt,Interrupt" bitfld.long 0x14 10. " [42] ,M4 IRQ[42] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 9. " [41] ,M4 IRQ[41] status bit" "No interrupt,Interrupt" bitfld.long 0x14 8. " [40] ,M4 IRQ[40] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 7. " [39] ,M4 IRQ[39] status bit" "No interrupt,Interrupt" bitfld.long 0x14 6. " [38] ,M4 IRQ[38] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 5. " [37] ,M4 IRQ[37] status bit" "No interrupt,Interrupt" bitfld.long 0x14 4. " [36] ,M4 IRQ[36] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 3. " [35] ,M4 IRQ[35] status bit" "No interrupt,Interrupt" bitfld.long 0x14 2. " [34] ,M4 IRQ[34] status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 1. " [33] ,M4 IRQ[33] status bit" "No interrupt,Interrupt" bitfld.long 0x14 0. " [32] ,M4 IRQ[32] status bit" "No interrupt,Interrupt" line.long 0x18 "ISR3_M4,IRQ Status Register 3 Of M4" bitfld.long 0x18 31. " ISR3_M4[95] ,M4 IRQ[95] status bit" "No interrupt,Interrupt" bitfld.long 0x18 30. " [94] ,M4 IRQ[94] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 29. " [93] ,M4 IRQ[93] status bit" "No interrupt,Interrupt" bitfld.long 0x18 28. " [92] ,M4 IRQ[92] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 27. " [91] ,M4 IRQ[91] status bit" "No interrupt,Interrupt" bitfld.long 0x18 26. " [90] ,M4 IRQ[90] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 25. " [89] ,M4 IRQ[89] status bit" "No interrupt,Interrupt" bitfld.long 0x18 24. " [88] ,M4 IRQ[88] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 23. " [87] ,M4 IRQ[87] status bit" "No interrupt,Interrupt" bitfld.long 0x18 22. " [86] ,M4 IRQ[86] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 21. " [85] ,M4 IRQ[85] status bit" "No interrupt,Interrupt" bitfld.long 0x18 20. " [84] ,M4 IRQ[84] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 19. " [83] ,M4 IRQ[83] status bit" "No interrupt,Interrupt" bitfld.long 0x18 18. " [82] ,M4 IRQ[82] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 17. " [81] ,M4 IRQ[81] status bit" "No interrupt,Interrupt" bitfld.long 0x18 16. " [80] ,M4 IRQ[80] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 15. " [79] ,M4 IRQ[79] status bit" "No interrupt,Interrupt" bitfld.long 0x18 14. " [78] ,M4 IRQ[78] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 13. " [77] ,M4 IRQ[77] status bit" "No interrupt,Interrupt" bitfld.long 0x18 12. " [76] ,M4 IRQ[76] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 11. " [75] ,M4 IRQ[75] status bit" "No interrupt,Interrupt" bitfld.long 0x18 10. " [74] ,M4 IRQ[74] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 9. " [73] ,M4 IRQ[73] status bit" "No interrupt,Interrupt" bitfld.long 0x18 8. " [72] ,M4 IRQ[72] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 7. " [71] ,M4 IRQ[71] status bit" "No interrupt,Interrupt" bitfld.long 0x18 6. " [70] ,M4 IRQ[70] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 5. " [69] ,M4 IRQ[69] status bit" "No interrupt,Interrupt" bitfld.long 0x18 4. " [68] ,M4 IRQ[68] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 3. " [67] ,M4 IRQ[67] status bit" "No interrupt,Interrupt" bitfld.long 0x18 2. " [66] ,M4 IRQ[66] status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 1. " [65] ,M4 IRQ[65] status bit" "No interrupt,Interrupt" bitfld.long 0x18 0. " [64] ,M4 IRQ[64] status bit" "No interrupt,Interrupt" line.long 0x1C "ISR4_M4,IRQ Status Register 4 Of M4" bitfld.long 0x1C 31. " ISR4_M4[127] ,M4 IRQ[127] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 30. " [126] ,M4 IRQ[126] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 29. " [125] ,M4 IRQ[125] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 28. " [124] ,M4 IRQ[124] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 27. " [123] ,M4 IRQ[123] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 26. " [122] ,M4 IRQ[122] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 25. " [121] ,M4 IRQ[121] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 24. " [120] ,M4 IRQ[120] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 23. " [119] ,M4 IRQ[119] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 22. " [118] ,M4 IRQ[118] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 21. " [117] ,M4 IRQ[117] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 20. " [116] ,M4 IRQ[116] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 19. " [115] ,M4 IRQ[115] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 18. " [114] ,M4 IRQ[114] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 17. " [113] ,M4 IRQ[113] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 16. " [112] ,M4 IRQ[112] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 15. " [111] ,M4 IRQ[111] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 14. " [110] ,M4 IRQ[110] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 13. " [109] ,M4 IRQ[109] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 12. " [108] ,M4 IRQ[108] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 11. " [107] ,M4 IRQ[107] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 10. " [106] ,M4 IRQ[106] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 9. " [105] ,M4 IRQ[105] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 8. " [104] ,M4 IRQ[104] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 7. " [103] ,M4 IRQ[103] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 6. " [102] ,M4 IRQ[102] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 5. " [101] ,M4 IRQ[101] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 4. " [100] ,M4 IRQ[100] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 3. " [99] ,M4 IRQ[99] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 2. " [98] ,M4 IRQ[98] status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 1. " [97] ,M4 IRQ[97] status bit" "No interrupt,Interrupt" bitfld.long 0x1C 0. " [96] ,M4 IRQ[96] status bit" "No interrupt,Interrupt" group.long 0xB0++0x03 line.long 0x00 "SLT0_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xB4++0x03 line.long 0x00 "SLT1_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xB8++0x03 line.long 0x00 "SLT2_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xBC++0x03 line.long 0x00 "SLT3_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xC0++0x03 line.long 0x00 "SLT4_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xC4++0x03 line.long 0x00 "SLT5_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xC8++0x03 line.long 0x00 "SLT6_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xCC++0x03 line.long 0x00 "SLT7_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xD0++0x03 line.long 0x00 "SLT8_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xD4++0x03 line.long 0x00 "SLT9_CFG,Slot Configure Register" bitfld.long 0x00 19. " M4_VIRTUAL_PUP_SLOT_CONTROL ,M4_VIRTUAL Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 18. " M4_VIRTUAL_PDN_SLOT_CONTROL ,M4_VIRTUAL Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 17. " USB_HSIC_PUP_SLOT_CONTROL ,USB_HSIC Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 16. " USB_HSIC_PDN_SLOT_CONTROL ,USB_HSIC Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 15. " USB_OTG2_PUP_SLOT_CONTROL ,USB_OTG2 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 14. " USB_OTG2_PDN_SLOT_CONTROL ,USB_OTG2 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 13. " USB_OTG1_PUP_SLOT_CONTROL ,USB_OTG1 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 12. " USB_OTG1_PDN_SLOT_CONTROL ,USB_OTG1 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 11. " PCIE_PHY_PUP_SLOT_CONTROL ,PCIE_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 10. " PCIE_PHY_PDN_SLOT_CONTROL ,PCIE_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 9. " MIPI_PHY_PUP_SLOT_CONTROL ,MIPI_PHY Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 8. " MIPI_PHY_PDN_SLOT_CONTROL ,MIPI_PHY Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 7. " FASTMEGA_PUP_SLOT_CONTROL ,FASTMEGA Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 6. " FASTMEGA_PDN_SLOT_CONTROL ,FASTMEGA Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 5. " SCU_PUP_SLOT_CONTROL ,SCU Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 4. " SCU_PDN_SLOT_CONTROL ,SCU Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 3. " CORE1_A7_PUP_SLOT_CONTROL ,CORE1 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 2. " CORE1_A7_PDN_SLOT_CONTROL ,CORE1 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" newline bitfld.long 0x00 1. " CORE0_A7_PUP_SLOT_CONTROL ,CORE0 A7 Power-up slot control on hardware power-up request" "Not powered-up,Powered-up" bitfld.long 0x00 0. " CORE0_A7_PDN_SLOT_CONTROL ,CORE0 A7 Power-down slot control on hardware power-down request" "Not powered-down,Powered-down" group.long 0xEC++0x07 line.long 0x00 "PGC_CPU_MAPPING,PGC CPU Mapping" bitfld.long 0x00 14. " USB_HSIC_PHY_M4_DOMAIN ,USB_HSIC_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 13. " USB_OTG2_PHY_M4_DOMAIN ,USB_OTG2_PHY mapping" "Not mapped,Mapped" newline bitfld.long 0x00 12. " USB_OTG1_PHY_M4_DOMAIN ,USB_OTG1_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 11. " PCIE_PHY_M4_DOMAIN ,PCIE_PHY mapping" "Not mapped,Mapped" newline bitfld.long 0x00 10. " MIPI_PHY_M4_DOMAIN ,MIPI_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 8. " FASTMEGA_M4_DOMAIN ,FAST/MEGA mapping" "Not mapped,Mapped" newline bitfld.long 0x00 6. " USB_HSIC_PHY_A7_DOMAIN ,USB_HSIC_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 5. " USB_OTG2_PHY_A7_DOMAIN ,USB_OTG2_PHY mapping" "Not mapped,Mapped" newline bitfld.long 0x00 4. " USB_OTG1_PHY_A7_DOMAIN ,USB_OTG1_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 3. " PCIE_PHY_A7_DOMAIN ,PCIE_PHY mapping" "Not mapped,Mapped" newline bitfld.long 0x00 2. " MIPI_PHY_A7_DOMAIN ,MIPI_PHY mapping" "Not mapped,Mapped" bitfld.long 0x00 0. " FASTMEGA_A7_DOMAIN ,FAST/MEGA mapping" "Not mapped,Mapped" line.long 0x04 "CPU_PGC_SW_PUP_REQ,CPU PGC Software Up Trigger" bitfld.long 0x04 2. " SCU_A7_SW_PUP_REQ ,Software power up trigger for SCU A7" "No effect,Trigger" bitfld.long 0x04 1. " CORE1_A7_SW_PUP_REQ ,Software power up trigger for core1 A7 PGC" "No effect,Trigger" newline bitfld.long 0x04 0. " CORE0_A7_SW_PUP_REQ ,Software power up trigger for core0 A7 PGC" "No effect,Trigger" group.long 0xF8++0x07 line.long 0x00 "PU_PGC_SW_PUP_REQ,PU PGC Software Up Trigger" bitfld.long 0x00 4. " USB_HSIC_PHY_SW_PUP_REQ ,Software power up trigger for USB_HSIC_PHY" "No effect,Trigger" bitfld.long 0x00 3. " USB_OTG2_PHY_SW_PUP_REQ ,Software power up trigger for USB_OTG2_PHY" "No effect,Trigger" newline bitfld.long 0x00 2. " USB_OTG1_PHY_SW_PUP_REQ ,Software power up trigger for USB_OTG1_PHY" "No effect,Trigger" bitfld.long 0x00 1. " PCIE_PHY_SW_PUP_REQ ,Software power up trigger for PCIE_PHY" "No effect,Trigger" newline bitfld.long 0x00 0. " MIPI_PHY_SW_PUP_REQ ,Software power up trigger for MIPI_PHY" "No effect,Trigger" line.long 0x04 "CPU_PGC_SW_PDN_REQ,CPU PGC Software Down Trigger" bitfld.long 0x04 2. " SCU_A7_SW_PDN_REQ ,Software power down trigger for SCU A7" "No effect,Trigger" bitfld.long 0x04 1. " CORE1_A7_SW_PDN_REQ ,Software power down trigger for core1 A7 PGC" "No effect,Trigger" newline bitfld.long 0x04 0. " CORE0_A7_SW_PDN_REQ ,Software power down trigger for core0 A7 PGC" "No effect,Trigger" group.long 0x104++0x03 line.long 0x00 "PU_PGC_SW_PDN_REQ,PU PGC Software Down Trigger" bitfld.long 0x00 4. " USB_HSIC_PHY_SW_PDN_REQ ,Software power down trigger for USB_HSIC_PHY" "No effect,Trigger" bitfld.long 0x00 3. " USB_OTG2_PHY_SW_PDN_REQ ,Software power down trigger for USB_OTG2_PHY" "No effect,Trigger" newline bitfld.long 0x00 2. " USB_OTG1_PHY_SW_PDN_REQ ,Software power down trigger for USB_OTG1_PHY" "No effect,Trigger" bitfld.long 0x00 1. " PCIE_PHY_SW_PDN_REQ ,Software power down trigger for PCIE_PHY" "No effect,Trigger" newline bitfld.long 0x00 0. " MIPI_PHY_SW_PDN_REQ ,Software power down trigger for MIPI_PHY" "No effect,Trigger" rgroup.long 0x110++0x07 line.long 0x00 "LPS_A7,Low Power Status Of A7 Platform" bitfld.long 0x00 28.--30. " LPM_CURRENT_STATE_A7 ,LPM_CURRENT_STATE_A7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--27. " SHD_CURRENT_STATE_A7 ,SHD_CURRENT_STATE_A7" "0,1,2,3" newline bitfld.long 0x00 25. " LPG_STOP ,LPG_STOP" "Not stopped,Stopped" bitfld.long 0x00 24. " LPG_WAIT ,LPG_WAIT" "No wait,Wait" newline bitfld.long 0x00 19. " GPC_CA7_L2_SWITCH_B ,GPC_CA7_L2_SWITCH_B" "Not switched,Switched" bitfld.long 0x00 18. " GPC_CA7_L2STDISABLE ,GPC_CA7_L2STDISABLE" "No,Yes" newline bitfld.long 0x00 17. " GPC_CA7_L2RETENTION ,GPC_CA7_L2RETENTION" "No retention,Retention" bitfld.long 0x00 16. " GPC_CA7_ACINACTM ,GPC_CA7_ACINACTM" "0,1" newline bitfld.long 0x00 15. " GPC_CA7_SCU_SWITCH_B ,GPC_CA7_SCU_SWITCH_B" "Not switched,Switched" bitfld.long 0x00 14. " GPC_CA7_SCU_ISO ,GPC_CA7_SCU_ISO" "0,1" newline bitfld.long 0x00 13. " START_SCU_RESET ,START_SCU_RESET" "Not reset,Reset" bitfld.long 0x00 12. " GPC_DAP_PUP_REQ ,GPC_DAP_PUP_REQ" "Not required,Required" newline bitfld.long 0x00 11. " SRC_A7_PLATFORM_SW_RESET_DONE ,SRC_A7_PLATFORM_SW_RESET_DONE" "Not done,Done" bitfld.long 0x00 10. " SRC_CA7_L2_RESET_N ,SRC_CA7_L2_RESET_N" "Not reset,Reset" newline bitfld.long 0x00 9. " GPC_CA7_C1_SWITCH_B ,GPC_CA7_C1_SWITCH_B" "Not switched,Switched" bitfld.long 0x00 8. " GPC_CA7_C0_SWITCH_B ,GPC_CA7_C0_SWITCH_B" "Not switched,Switched" newline bitfld.long 0x00 7. " GPC_CA7_C1_ISO ,GPC_CA7_C1_ISO" "0,1" bitfld.long 0x00 6. " GPC_CA7_C0_ISO ,GPC_CA7_C0_ISO" "0,1" newline bitfld.long 0x00 5. " A7_START_ARM_RESET2 ,A7_START_ARM_RESET2" "Not started,Started" bitfld.long 0x00 4. " A7_START_ARM_RESET0 ,A7_START_ARM_RESET0" "Not started,Started" newline bitfld.long 0x00 3. " SRC_GPC_ARM_CPU1_RST_SYS_N ,SRC_GPC_ARM_CPU1_RST_SYS_N" "0,1" bitfld.long 0x00 2. " SRC_GPC_ARM_CPU0_RST_SYS_N ,SRC_GPC_ARM_CPU0_RST_SYS_N" "0,1" newline bitfld.long 0x00 1. " SRC_A7_CORES_SW_RESET_DONE1 ,SRC_A7_CORES_SW_RESET_DONE1" "Not done,Done" bitfld.long 0x00 0. " SRC_A7_CORES_SW_RESET_DONE0 ,SRC_A7_CORES_SW_RESET_DONE0" "Not done,Done" line.long 0x04 "LPS_M4,Low Power Status Of M4 Platform" bitfld.long 0x04 28.--30. " LPM_CURRENT_STATE_M4 ,LPM_CURRENT_STATE_M4" "0,1,2,3,4,5,6,7" bitfld.long 0x04 26.--27. " SHD_CURRENT_STATE_M4 ,SHD_CURRENT_STATE_M4" "0,1,2,3" newline bitfld.long 0x04 25. " LPG_STOP ,LPG_STOP" "Not stopped,Stopped" bitfld.long 0x04 24. " LPG_WAIT ,LPG_WAIT" "No wait,Wait" newline bitfld.long 0x04 8. " M4_CORE_RESET_B ,M4_CORE_RESET_B" "Not reset,Reset" bitfld.long 0x04 7. " M4_PLATFORM_RESET_B ,M4_PLATFORM_RESET_B" "Not reset,Reset" newline bitfld.long 0x04 6. " CM4_HALTED ,CM4_HALTED" "Not halted,Halted" bitfld.long 0x04 5. " CM4_LOCKUP ,CM4_LOCKUP" "Not locked-up,Locked-up" newline bitfld.long 0x04 4. " CM4_SLEEP ,CM4_SLEEP" "No sleep,Sleep" bitfld.long 0x04 3. " CM4_SLEEP_DEEP ,CM4_SLEEP_DEEP" "No sleep deep,Sleep deep" newline bitfld.long 0x04 2. " CM4_GATE_HCLK ,CM4_GATE_HCLK" "Not gated,Gated" bitfld.long 0x04 1. " CM4_SLEEP_HOLD_ACK_B ,CM4_SLEEP_HOLD_ACK_B" "Sleep not held,Sleep held`" newline bitfld.long 0x04 0. " LOW_POWER_CTRL_M4 ,LOW_POWER_CTRL_M4" "0,1" group.long 0x120++0x07 line.long 0x00 "GPC_GPR,GPC General Purpose Register" bitfld.long 0x00 16. " A7_CORE_DBG_RST_MSK_PG ,A7_CORE_DBG_RST_MSK_PG" "Not masked,Masked" line.long 0x04 "GTOR,GPC Testing Observe Register" bitfld.long 0x04 31. " OBS_EN ,Observe signals enable" "Disabled,Enabled" bitfld.long 0x04 16.--20. " OBS_OUTPUT_2_SEL ,Observability output 2 select" ",,,,Lpm_current_state_a7[2],?..." newline bitfld.long 0x04 8.--12. " OBS_OUTPUT_1_SEL ,Observability output 1 select" "Ipg_wait[1],Ipg_wait[1],Cpu_in_wait_mode[1],Cpu_in_stop_mode[1],Lpm_current_state_a7[1],Hndsk_current_state_a7[1],Shd_current_state_a7[1],Lpm_current_state_m4[1],Hndsk_current_state_m4[1],Shd_current_state_m4[1],Pll_clock_ready[1],Dpllen_req_cpu0_reg_b,Pgc_hw_pup_req[1],Pgc_hw_pup_req[4],Pgc_hw_pup_req[7],Pgc_hw_pdn_req[1],Pgc_hw_pdn_req[4],Pgc_hw_pdn_req[7],Pgc_hw_pup_ack[1],Pgc_hw_pup_ack[4],Pgc_hw_pup_ack[7],Pgc_hw_pdn_ack[1],Pgc_hw_pdn_ack[4],Pgc_hw_pdn_ack[7],Enable_clocks[1],Mem_dsn_ret1n,Pmic_stby_req,Dplls_locked,Other,Other,Other,Other" bitfld.long 0x04 0.--4. " OBS_OUTPUT_0_SEL ,Observability output 0 select" "Ipg_wait[0],Ipg_wait[0],Cpu_in_wait_mode[0],Cpu_in_stop_mode[0],Lpm_current_state_a7[0],Hndsk_current_state_a7[0],Shd_current_state_a7[0],Lpm_current_state_m4[0],Hndsk_current_state_m4[0],Shd_current_state_m4[0],Pll_clock_ready[0],Dpllen_req_cpu0_reg_b,Pgc_hw_pup_req[0],Pgc_hw_pup_req[3],Pgc_hw_pup_req[6],Pgc_hw_pdn_req[0],Pgc_hw_pdn_req[3],Pgc_hw_pdn_req[6],Pgc_hw_pup_ack[0],Pgc_hw_pup_ack[3],Pgc_hw_pup_ack[6],Pgc_hw_pdn_ack[0],Pgc_hw_pdn_ack[3],Pgc_hw_pdn_ack[6],Enable_clocks[0],Mem_ds_pgen,Cosc_pwrdown,Ana_reg_bypass,Other,Other,Other,Other" rgroup.long 0x128++0x03 line.long 0x00 "DEBUG_ADDR1,DEBUG ADDR1" bitfld.long 0x00 23. " NIRQ3 ,Nirq3" "No interrupt,Interrupt" bitfld.long 0x00 22. " NIRQ2 ,Nirq2" "No interrupt,Interrupt" newline bitfld.long 0x00 21. " NIRQ1 ,Nirq1" "No interrupt,Interrupt" bitfld.long 0x00 20. " NIRQ0 ,Nirq0" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " NFIQ3 ,Nfiq3" "No interrupt,Interrupt" bitfld.long 0x00 18. " NFIQ2 ,Nfiq2" "No interrupt,Interrupt" newline bitfld.long 0x00 17. " NFIQ1 ,Nfiq1" "No interrupt,Interrupt" bitfld.long 0x00 16. " NFIQ0 ,Nfiq0" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " WFI_M4 ,WFI_M4" "No wait,Wait" bitfld.long 0x00 6. " WFI_A7_SCU ,WFI_A7_SCU" "No wait,Wait" newline bitfld.long 0x00 5. " WFI_A7_CORE1 ,WFI_A7_CORE1" "No wait,Wait" bitfld.long 0x00 4. " WFI_A7_CORE0 ,WFI_A7_CORE00" "No wait,Wait" newline bitfld.long 0x00 0. " GPC_INT ,GPC_INT" "No interrupt,Interrupt" group.long 0x12C++0x03 line.long 0x00 "DEBUG_ADDR2,DEBUG ADDR2" rbitfld.long 0x00 27.--31. " GPC_PU_RESET_B ,GPC_PU_RESET_B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 22.--26. " GPC_PU_SWITCH_B ,GPC_PU_SWITCH_B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 17.--21. " GPC_PU_ISO ,GPC_PU_ISO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 12.--16. " PU_RESET_PENETRATED ,PU_RESET_PENETRATED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8. " GPC_MIX_RDY ,GPC_MIX_RDY" "Not ready,Ready" rbitfld.long 0x00 7. " SRC_EN_MIX_CLK ,SRC_EN_MIX_CLK" "Disabled,Enabled" newline bitfld.long 0x00 6. " GPC_MIX_RESET_B ,GPC_MIX_RESET_B" "Not reset,Reset" rbitfld.long 0x00 5. " GPC_MIX_SCALL ,GPC_MIX_SCALL" "0,1" newline rbitfld.long 0x00 4. " GPC_MIX_SCALL_OUT1 ,GPC_MIX_SCALL_OUT1" "0,1" rbitfld.long 0x00 3. " GPC_MIX_SCALL_OUT0 ,GPC_MIX_SCALL_OUT0" "0,1" newline rbitfld.long 0x00 2. " GPC_MIX_SWITCH_B ,GPC_MIX_SWITCH_B" "Not switched,Switched" rbitfld.long 0x00 1. " GPC_MIX_ISO ,GPC_MIX isolation control signal" "No signal,Signal" newline rbitfld.long 0x00 0. " MIX_RESET_PENETRATED ,MIX_RESET_PENETRATED" "Not penetrated,Penetrated" rgroup.long 0x130++0x03 line.long 0x00 "CPU_PGC_PUP_STATUS1,CPU PGC Software Up Trigger Status1" bitfld.long 0x00 2. " SCU_A7_PUP_STATUS ,Results for power up software trigger for SCU A7" "Succeeded,Failed" bitfld.long 0x00 1. " CORE1_A7_PUP_STATUS ,Results for power up software trigger for CORE1 A7" "Succeeded,Failed" newline bitfld.long 0x00 0. " CORE0_A7_PUP_STATUS ,Results for power up software trigger for CORE0 A7" "Succeeded,Failed" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rgroup.long 0x134++0x03 line.long 0x00 "A7_MIX_PGC_PUP_STATUS0,A7 MIX Software Up Trigger Status Register 0" bitfld.long 0x00 0. " A7_MIX_PGC_PUP_STATUS ,A7_MIX_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x138++0x03 line.long 0x00 "A7_MIX_PGC_PUP_STATUS1,A7 MIX Software Up Trigger Status Register 1" bitfld.long 0x00 0. " A7_MIX_PGC_PUP_STATUS ,A7_MIX_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x13C++0x03 line.long 0x00 "A7_MIX_PGC_PUP_STATUS2,A7 MIX Software Up Trigger Status Register 2" bitfld.long 0x00 0. " A7_MIX_PGC_PUP_STATUS ,A7_MIX_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x140++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS0,M4 MIX PGC Software Up Trigger Status Register 0" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4_MIX_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x144++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS1,M4 MIX PGC Software Up Trigger Status Register 1" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4_MIX_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x148++0x03 line.long 0x00 "M4_MIX_PGC_PUP_STATUS2,M4 MIX PGC Software Up Trigger Status Register 2" bitfld.long 0x00 0. " M4_MIX_PGC_PUP_STATUS ,M4_MIX_PGC_PUP_STATUS" "Succeeded,Failed" else rgroup.long 0x134++0x03 line.long 0x00 "A7_PU_PGC_PUP_STATUS0,A7 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PUP_STATUS ,A7_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PUP_STATUS , A7_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PUP_STATUS ,A7_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PUP_STATUS ,A7_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PUP_STATUS ,A7_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x138++0x03 line.long 0x00 "A7_PU_PGC_PUP_STATUS1,A7 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PUP_STATUS ,A7_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PUP_STATUS , A7_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PUP_STATUS ,A7_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PUP_STATUS ,A7_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PUP_STATUS ,A7_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x13C++0x03 line.long 0x00 "A7_PU_PGC_PUP_STATUS2,A7 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PUP_STATUS ,A7_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PUP_STATUS , A7_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PUP_STATUS ,A7_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PUP_STATUS ,A7_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PUP_STATUS ,A7_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x140++0x03 line.long 0x00 "M4_PU_PGC_PUP_STATUS0,M4 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " M4_USB_HSIC_PHY_PGC_PUP_STATUS ,M4_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PHY_PGC_PUP_STATUS , M4_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " M4_USB_OTG1_PHY_PGC_PUP_STATUS ,M4_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PHY_PGC_PUP_STATUS ,M4_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " M4_MIPI_PHY_PGC_PUP_STATUS ,M4_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x144++0x03 line.long 0x00 "M4_PU_PGC_PUP_STATUS1,M4 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " M4_USB_HSIC_PHY_PGC_PUP_STATUS ,M4_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PHY_PGC_PUP_STATUS , M4_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " M4_USB_OTG1_PHY_PGC_PUP_STATUS ,M4_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PHY_PGC_PUP_STATUS ,M4_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " M4_MIPI_PHY_PGC_PUP_STATUS ,M4_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" rgroup.long 0x148++0x03 line.long 0x00 "M4_PU_PGC_PUP_STATUS2,M4 PU Software Up Trigger Domain Control Condition Status Register" bitfld.long 0x00 4. " M4_USB_HSIC_PHY_PGC_PUP_STATUS ,M4_USB_HSIC_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " M4_USB_OTG2_PHY_PGC_PUP_STATUS , M4_USB_OTG2_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " M4_USB_OTG1_PHY_PGC_PUP_STATUS ,M4_USB_OTG1_PHY_PGC_PUP_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " M4_PCIE_PHY_PGC_PUP_STATUS ,M4_PCIE_PHY_PGC_PUP_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " M4_MIPI_PHY_PGC_PUP_STATUS ,M4_MIPI_PHY_PGC_PUP_STATUS" "Succeeded,Failed" endif rgroup.long 0x170++0x03 line.long 0x00 "CPU_PGC_PDN_STATUS1,CPU PGC Software Dn Trigger Relevant PGC Process Status1" bitfld.long 0x00 2. " SCU_A7_PDN_STATUS ,SCU_A7_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " CORE1_A7_PDN_STATUS ,CORE1_A7_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " CORE0_A7_PDN_STATUS ,CORE0_A7_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x18C++0x03 line.long 0x00 "A7_PU_PGC_PDN_STATUS1,A7 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 2. " SCU_A7_PDN_STATUS ,SCU_A7_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " CORE1_A7_PDN_STATUS ,CORE1_A7_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " CORE0_A7_PDN_STATUS ,CORE0_A7_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x190++0x03 line.long 0x00 "A7_PU_PGC_PDN_STATUS1,A7 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 2. " SCU_A7_PDN_STATUS ,SCU_A7_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " CORE1_A7_PDN_STATUS ,CORE1_A7_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " CORE0_A7_PDN_STATUS ,CORE0_A7_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x194++0x03 line.long 0x00 "A7_PU_PGC_PDN_STATUS1,A7 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 2. " SCU_A7_PDN_STATUS ,SCU_A7_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " CORE1_A7_PDN_STATUS ,CORE1_A7_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " CORE0_A7_PDN_STATUS ,CORE0_A7_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x198++0x03 line.long 0x00 "M4_PU_PGC_PDN_STATUS0,M4 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PDN_STATUS ,A7_USB_HSIC_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PDN_STATUS ,A7_USB_OTG2_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PDN_STATUS ,A7_USB_OTG1_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PDN_STATUS ,A7_PCIE_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PDN_STATUS ,A7_MIPI_PHY_PGC_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x19C++0x03 line.long 0x00 "M4_PU_PGC_PDN_STATUS1,M4 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PDN_STATUS ,A7_USB_HSIC_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PDN_STATUS ,A7_USB_OTG2_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PDN_STATUS ,A7_USB_OTG1_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PDN_STATUS ,A7_PCIE_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PDN_STATUS ,A7_MIPI_PHY_PGC_PDN_STATUS" "Succeeded,Failed" rgroup.long 0x1A0++0x03 line.long 0x00 "M4_PU_PGC_PDN_STATUS2,M4 PU PGC Software Down Trigger Domain Control Condition Status" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PDN_STATUS ,A7_USB_HSIC_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PDN_STATUS ,A7_USB_OTG2_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PDN_STATUS ,A7_USB_OTG1_PHY_PGC_PDN_STATUS" "Succeeded,Failed" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PDN_STATUS ,A7_PCIE_PHY_PGC_PDN_STATUS" "Succeeded,Failed" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PDN_STATUS ,A7_MIPI_PHY_PGC_PDN_STATUS" "Succeeded,Failed" group.long 0x1B0++0x03 line.long 0x00 "A7_MIX_PDN_FLG,A7 MIX PDN FLG" bitfld.long 0x00 0. " A7_MIX_PDN_FLAG ,A7 MIX power-down flag" "Not powered-down,Powered-down" rgroup.long 0x1B4++0x03 line.long 0x00 "A7_PU_PDN_FLG,A7 PU PDN FLG" bitfld.long 0x00 4. " A7_USB_HSIC_PHY_PGC_PDN_FLG ,USB_HSIC PGC power-down flag" "Not powered-down,Powered-down" bitfld.long 0x00 3. " A7_USB_OTG2_PHY_PGC_PDN_FLG ,USB_OTG2 PGC power-down flag" "Not powered-down,Powered-down" newline bitfld.long 0x00 2. " A7_USB_OTG1_PHY_PGC_PDN_FLG ,USB_OTG1 PGC power-down flag" "Not powered-down,Powered-down" bitfld.long 0x00 1. " A7_PCIE_PHY_PGC_PDN_FLG ,PCIE_PHY PGC power-down flag" "Not powered-down,Powered-down" newline bitfld.long 0x00 0. " A7_MIPI_PHY_PGC_PDN_FLG ,MIPI_PHY PGC power-down flag" "Not powered-down,Powered-down" group.long 0x1B8++0x03 line.long 0x00 "M4_MIX_PDN_FLG,M4 MIX PDN FLG" bitfld.long 0x00 0. " M4_MIX_PDN_FLAG ,M4_MIX power-down flag" "Not powered-down,Powered-down" rgroup.long 0x1BC++0x03 line.long 0x00 "M4_PU_PDN_FLG,M4 PU PDN FLG" bitfld.long 0x00 4. " M4_USB_HSIC_PHY_PGC_PDN_FLG ,USB_HSIC PGC power-down flag" "Not powered-down,Powered-down" bitfld.long 0x00 3. " M4_USB_OTG2_PHY_PGC_PDN_FLG ,USB_OTG2 PGC power-down flag" "Not powered-down,Powered-down" newline bitfld.long 0x00 2. " M4_USB_OTG1_PHY_PGC_PDN_FLG ,USB_OTG1 PGC power-down flag" "Not powered-down,Powered-down" bitfld.long 0x00 1. " M4_PCIE_PHY_PGC_PDN_FLG ,PCIE_PHY PGC power-down flag" "Not powered-down,Powered-down" newline bitfld.long 0x00 0. " M4_MIPI_PHY_PGC_PDN_FLG ,MIPI_PHY PGC power-down flag" "Not powered-down,Powered-down" width 0x0B tree.end tree "GPC_PGC" base ad:0x303A0000 width 16. group.long 0x800++0x0F line.long 0x00 "A7CORE0_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "A7CORE0_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "A7CORE0_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "A7CORE0_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x840++0x0F line.long 0x00 "A7CORE1_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "A7CORE1_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "A7CORE1_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "A7CORE1_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x880++0x0F line.long 0x00 "A7SCU_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "A7SCU_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "A7SCU_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "A7SCU_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x8C0++0x0F line.long 0x00 "MIX_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "MIX_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MIX_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MIX_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x900++0x0F line.long 0x00 "MIPI_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "MIPI_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MIPI_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MIPI_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x940++0x0F line.long 0x00 "PCIE_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1, it will be clear automatically once any of A7 core0/core1 is wakeup" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "PCIE_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b0 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PCIE_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PDN_SCALL_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PDN_WAIT_SCALL_OUT ,Wait handshake signal SCALL_OUT" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "PCIE_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") rgroup.long 0x890++0x03 line.long 0x00 "SCU_AUXSW,GPC PGC Auxiliary Power Switch Control Register For SCU Type GPC" hexmask.long.word 0x00 20.--29. 1. " MEMPWR_TRC1_TMC ,After scu start pup reset count this value to assert A7 mempwr to 1b1" hexmask.long.word 0x00 10.--19. 1. " L2RETN_TRC1_TMC_TMR ,After scu start pup reset count this value to assert A7 l2retn to 1b1" hexmask.long.word 0x00 0.--9. 1. " DFTRAM_TRC1_TMC_TMR_TCD2 ,After scu start pup reset count this value to assert A7 dftram to 1b1" else rgroup.long 0x890++0x03 line.long 0x00 "SCU_AUXSW,GPC PGC Auxiliary Power Switch SCU Control Register" hexmask.long.word 0x00 20.--29. 1. " MEMPWR_TRC1_TMC ,After scu start pup reset count this value to assert A7 mempwr to 1b1" hexmask.long.word 0x00 10.--19. 1. " L2RETN_TRC1_TMC_TMR ,After scu start pup reset count this value to assert A7 l2retn to 1b1" hexmask.long.word 0x00 0.--9. 1. " DFTRAM_TRC1_TMC_TMR_TCD2 ,After scu start pup reset count this value to assert A7 dftram to 1b1" endif group.long 0xC10++0x03 line.long 0x00 "MIPI_AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x00 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x00 8.--13. " ISO2SW2 ,Waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW2 ,Waits a number of clocks equal to the value of SW2 before asserting switch2_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC50++0x03 line.long 0x00 "PCIE_AUXSW,GPC PGC Auxiliary Power Switch Control Register" bitfld.long 0x00 16.--19. " PDN_CLK_DIV_SEL ,Clock divider select for the clock of power down counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x00 8.--13. " ISO2SW2 ,Waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SW2 ,Waits a number of clocks equal to the value of SW2 before asserting switch2_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD00++0x0F line.long 0x00 "HSIC_CTRL,GPC PGC Control Register" bitfld.long 0x00 24.--29. " MEMPWR_TCD1_TDR_TRM ,After scu pdn_req count this value to assert A7 mempwr to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " L2RETN_TCD1_TDR ,After scu pdn_req count this value to assert A7 l2retn to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DFTRAM_TCD1 ,After scu pdn_req count this value to assert A7 dftram to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1.--6. " L2RSTDIS ,After scu pdn_req count this value to assert A7 l2rstdis to 1b1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PCR ,Power control" "Not off,Off" line.long 0x04 "HSIC_PUPSCR,GPC PGC Up Sequence Control Register" hexmask.long.word 0x04 23.--31. 1. " PUP_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power up" hexmask.long.word 0x04 7.--22. 1. " SW2ISO ,Waits a number of clocks equal to the value of SW2ISO before negating isolation" newline bitfld.long 0x04 6. " PUP_WAIT_SCALL_OUT ,Waits handshake signal SCALL_OUT to return to 1b1" "0,1" bitfld.long 0x04 0.--5. " SW ,Waits a number of clocks equal to the value of SW before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "HSIC_PDNSCR,GPC PGC Down Sequence Control Register" hexmask.long.byte 0x08 24.--31. 1. " PUP_SCPRE_SCALL_CNT ,After SCPRE asserting to 1b1 count this value to assert SCALL to 1b1" hexmask.long.byte 0x08 16.--23. 1. " PUP_SCALLOUT_CNT ,After SCALL asserting to 1b1 count this value to complete switch power down" bitfld.long 0x08 8.--13. " ISO2SW ,Waits a number of clocks equal to the value of ISO2SW before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 7. " PUP_WAIT_SCALL_OUT ,Waits handshake signal SCALL_OUT to return to 1b1" "0,1" bitfld.long 0x08 0.--5. " ISO ,After a power-down request (Pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "HSIC_SR,GPC PGC Status Register" hexmask.long.word 0x0C 8.--17. 1. " L2RSTDIS_DEASSERT_CNT ,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up" bitfld.long 0x0C 3.--6. " PUP_CLK_DIV_SEL ,Clock divider select for the clock of power up counter" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512,1/1024,1/2056,1/4096,1/8192,1/16384,1/32768" rbitfld.long 0x0C 2. " ALLOFF_FLAG ,All-off flag" "Not woken-up,Woken-up" newline rbitfld.long 0x0C 1. " L2RETN_FLAG ,L2 retention flag" "Not woken-up,Woken-up" rbitfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" width 0x0B tree.end tree.end tree "SNVS (Secure Non-Volatile Storage)" base ad:0x30370000 width 12. group.long 0x00++0x07 line.long 0x00 "HPLR,HP Lock Register" bitfld.long 0x00 28. " AT5_SL ,Active tamper 5 soft lock" "Not locked,Locked" bitfld.long 0x00 27. " AT4_SL ,Active tamper 4 soft lock" "Not locked,Locked" bitfld.long 0x00 26. " AT3_SL ,Active tamper 3 soft lock" "Not locked,Locked" bitfld.long 0x00 25. " AT2_SL ,Active tamper 2 soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 24. " AT1_SL ,Active tamper 1 soft lock" "Not locked,Locked" bitfld.long 0x00 18. " HAC_L ,High assurance configuration lock" "Not locked,Locked" bitfld.long 0x00 17. " HPSICR_L ,HP security interrupt control register lock" "Not locked,Locked" bitfld.long 0x00 16. " HPSVCR_L ,HP security violation control register lock" "Not locked,Locked" textline " " bitfld.long 0x00 9. " MKS_SL ,Master key select soft lock" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_SL ,LP tamper detectors configuration register soft lock" "Not locked,Locked" bitfld.long 0x00 7. " LPTGFCR_SL ,LP tamper glitch filter configuration register soft lock" "Not locked,Locked" bitfld.long 0x00 6. " LPSVCR_SL ,LP security violation control register soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 5. " GPR_SL ,General purpose register soft lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_SL ,Monotonic counter soft lock" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_SL ,LP calibration soft lock" "Not locked,Locked" bitfld.long 0x00 2. " SRTC_SL ,Secure real time counter soft lock" "Not locked,Locked" textline " " bitfld.long 0x00 1. " ZMK_RSL ,Zeroizable master key read soft lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WSL ,Zeroizable master key write soft lock" "Not locked,Locked" line.long 0x04 "HPCOMR,HP Command Register" bitfld.long 0x04 31. " NPSWA_EN ,Non-Privileged software access enable" "Disabled,Enabled" bitfld.long 0x04 19. " HAC_STOP ,High assurance counter stop" "Not stopped,Stopped" bitfld.long 0x04 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x04 17. " HAC_LOAD ,High assurance counter load" "No effect,Loaded" textline " " bitfld.long 0x04 16. " HAC_EN ,High assurance configuration enable" "Disabled,Enabled" bitfld.long 0x04 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" bitfld.long 0x04 12. " PROG_ZMK ,Program zeroizable master key" "No effect,Activated" bitfld.long 0x04 10. " SW_LPSV ,LP software security violation" "Not violated,Violated" textline " " bitfld.long 0x04 9. " SW_FSV ,Software fatal security violation" "Not violated,Violated" bitfld.long 0x04 8. " SW_SV ,Software security violation" "Not violated,Violated" bitfld.long 0x04 5. " LP_SWR_DIS ,LP software reset disable" "No,Yes" bitfld.long 0x04 4. " LP_SWR ,LP software reset" "No effect,Reset" textline " " bitfld.long 0x04 2. " SSM_SFNS_DIS ,SSM soft fail to Non-Secure state transition disable" "No,Yes" bitfld.long 0x04 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x04 0. " SSM_ST ,SSM state transition" "No effect,Transition" if (((per.l(ad:0x30370000+0x08))&0x100)==0x00) group.long 0x08++0x03 line.long 0x00 "HPCR,HP Control Register" bitfld.long 0x00 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--26. " BTN_CONFIG ,Button configuration" "Low,High,Rising edge,Falling edge,Both edges,?..." bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "Not updated,Updated" bitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" textline " " bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,Number of bit responsible for generating periodic interrupt during its transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "HPCR,HP Control Register" bitfld.long 0x00 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--26. " BTN_CONFIG ,Button configuration" "Low,High,Rising edge,Falling edge,Both edges,?..." bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "Not updated,Updated" rbitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" textline " " bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,Number of bit responsible for generating periodic interrupt during its transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" endif group.long 0x0C++0x07 line.long 0x00 "HPSICR,Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SVI_EN5 ,Security violation interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4 ,Security violation interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SVI_EN3 ,Security violation interrupt 3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SVI_EN2 ,Security violation interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SVI_EN1 ,Security violation interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SVI_EN0 ,Security violation interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "HPSVCR,Security Violation Control Register" bitfld.long 0x04 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x04 5.--6. " SV_CFG5 ,Security violation input 5 configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x04 4. " SV_CFG4 ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x04 3. " SV_CFG3 ,Security violation input 3 configuration" "Non-fatal,Fatal" textline " " bitfld.long 0x04 2. " SV_CFG2 ,Security violation input 2 configuration" "Non-fatal,Fatal" bitfld.long 0x04 1. " SV_CFG1 ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x04 0. " SV_CFG0 ,Security violation input 0 configuration" "Non-fatal,Fatal" group.long 0x14++0x0B line.long 0x00 "HPSR,HP Status Register" rbitfld.long 0x00 31. " ZMK_ZERO ,Zeroizable master key is equal to zero" "Not zero,Zero" rbitfld.long 0x00 27. " OTPMK_ZERO ,One time programmable master key is equal to zero" "Not zero,Zero" hexmask.long.word 0x00 16.--24. 1. " OTPMK_SYNDROME ,One time programmable master key syndrome" rbitfld.long 0x00 15. " SYS_SECURE_BOOT ,System secure boot" "Normal,ROM" textline " " sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") rbitfld.long 0x00 12.--14. " SYS_SECURITY_CFG ,System security configuration" "Fab,Open,,Closed,,,,Field return" rbitfld.long 0x00 8.--11. " SSM_STATE ,System security monitor state" "Init,Hard fail,,Soft fail,,,,,Init intermediate,Check,,Non-secure,,Trusted,,Secure" textline " " else rbitfld.long 0x00 12.--14. " SYS_SECURITY_CFG ,System security configuration" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--11. " SSM_STATE ,System security monitor state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " endif eventfld.long 0x00 7. " BI ,Button interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 6. " BTN ,BTN input state" "Not pressed,Pressed" textline " " eventfld.long 0x00 1. " PI ,Periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " HPTA ,HP time alarm" "No interrupt,Interrupt" line.long 0x04 "HPSVSR,HP Security Violation Status" rbitfld.long 0x04 31. " LP_SEC_VIO ,LP security violation" "Not detected,Detected" eventfld.long 0x04 27. " ZMK_ECC_FAIL ,Zeroizable master key error correcting code check failure" "Not failed,Failed" hexmask.long.word 0x04 16.--24. 1. " ZMK_SYNDROME ,Zeroizable master key syndrome" rbitfld.long 0x04 15. " SW_LPSV ,LP software security violation" "Not violated,Violated" textline " " rbitfld.long 0x04 14. " SW_FSV ,Software fatal security violation" "Not violated,Violated" rbitfld.long 0x04 13. " SW_SV ,Software security violation" "Not violated,Violated" eventfld.long 0x04 5. " SEC_VIO5 ,Security volation on input 5 was detected" "Not detected,Detected" eventfld.long 0x04 4. " SEC_VIO4 ,Security volation on input 4 was detected" "Not detected,Detected" textline " " eventfld.long 0x04 3. " SEC_VIO3 ,Security volation on input 3 was detected" "Not detected,Detected" eventfld.long 0x04 2. " SEC_VIO2 ,Security volation on input 2 was detected" "Not detected,Detected" eventfld.long 0x04 1. " SEC_VIO1 ,Security volation on input 1 was detected" "Not detected,Detected" eventfld.long 0x04 0. " SEC_VIO0 ,Security volation on input 0 was detected" "Not detected,Detected" textline " " line.long 0x08 "HPHACIVR,HP High Assurance Counter IV" rgroup.long 0x20++0x03 line.long 0x00 "HPHACR,HP High Assurance Counter" if (((per.l(ad:0x30370000+0x08))&0x01)==0x01) rgroup.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" else group.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" endif if (((per.l(ad:0x30370000+0x08)&0x02)==0x02)) rgroup.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" else group.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" endif group.long 0x34++0x03 line.long 0x00 "LPLR,LP Lock Register" bitfld.long 0x00 28. " AT5_HL ,Active tamper 5 hard lock" "Not locked,Locked" bitfld.long 0x00 27. " AT4_HL ,Active tamper 4 hard lock" "Not locked,Locked" bitfld.long 0x00 26. " AT3_HL ,Active tamper 3 hard lock" "Not locked,Locked" bitfld.long 0x00 25. " AT2_HL ,Active tamper 2 hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 24. " AT1_HL ,Active tamper 1 hard lock" "Not locked,Locked" bitfld.long 0x00 9. " MKS_HL ,Master key select hard lock" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_HL ,LP tamper detectors configuration register hard lock" "Not locked,Locked" bitfld.long 0x00 7. " LPTGFCR_HL ,LP tamper glitch filter configuration register hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 6. " LPSVCR_HL ,LP security violation control register hard lock" "Not locked,Locked" bitfld.long 0x00 5. " GPR_HL ,General purpose register hard lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_HL ,Monotonic counter hard lock" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_HL ,LP calibration hard lock" "Not locked,Locked" textline " " bitfld.long 0x00 2. " SRTC_HL ,Secure real time counter hard lock" "Not locked,Locked" bitfld.long 0x00 1. " ZMK_RHL ,Zeroizable master key read hard lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WHL ,Zeroizable master key write hard lock" "Not locked,Locked" if ((per.l(ad:0x30370000+0x38)&0x20)==0x20) group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 24. " GPR_Z_DIS ,General purpose registers zeroization disable" "No,Yes" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the socpower" "500 msec,50 msec,100 msec,0 msec" textline " " bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 msec,100 msec,500 msec,0 msec" bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 sec,10 sec,15 sec,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" bitfld.long 0x00 6. " TOP ,Turn off system power" "Power on,Power off" bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 4. " SRTC_INV_EN ,SRTC stops counting and the SRTC is invalidated" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LPWUI_EN ,LP Wake-Up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" bitfld.long 0x00 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRTC_ENV ,Secure real time counter enabled and valid" "Disabled,Enabled" else group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 24. " GPR_Z_DIS ,General purpose registers zeroization disable" "No,Yes" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the socpower" "500 msec,50 msec,100 msec,0 msec" textline " " bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 msec,100 msec,500 msec,0 msec" bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 sec,10 sec,15 sec,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 4. " SRTC_INV_EN ,SRTC stops counting and the SRTC is invalidated" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LPWUI_EN ,LP Wake-Up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" bitfld.long 0x00 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRTC_ENV ,Secure real time counter enabled and valid" "Disabled,Enabled" endif if (((per.l(ad:0x30370000)&0x01)==0x00)&&((per.l(ad:0x30370000+0x34)&0x01)==0x00)&&((per.l(ad:0x30370000)&0x200)==0x00)&&((per.l(ad:0x30370000+0x34)&0x200)==0x00)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" elif (((per.l(ad:0x30370000)&0x01)==0x00)&&((per.l(ad:0x30370000+0x34)&0x01)==0x00))&&(((per.l(ad:0x30370000)&0x200)==0x200)||((per.l(ad:0x30370000+0x34)&0x200)==0x200)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " rbitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" elif (((per.l(ad:0x30370000)&0x01)==0x01)||((per.l(ad:0x30370000+0x34)&0x01)==0x01))&&(((per.l(ad:0x30370000)&0x200)==0x00)&&((per.l(ad:0x30370000+0x34)&0x200)==0x00)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" rbitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" rbitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" rbitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" else rgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "0,1" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key hardware programming mode" "Software,Hardware" textline " " bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "0,1,Zeroizable,Hardware" endif if (((per.l(ad:0x30370000)&0x40)==0x00)&&((per.l(ad:0x30370000+0x34)&0x40)==0x00)) group.long 0x40++0x03 line.long 0x00 "LPSVCR,LP Security Violation Control" bitfld.long 0x00 5. " SV_EN5 ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV_EN4 ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV_EN3 ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV_EN2 ,Security violation 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SV_EN1 ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV_EN0 ,Security violation 0 enable" "Disabled,Enabled" else rgroup.long 0x40++0x03 line.long 0x00 "LPSVCR,LP Security Violation Control" bitfld.long 0x00 5. " SV_EN5 ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV_EN4 ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV_EN3 ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV_EN2 ,Security violation 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SV_EN1 ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV_EN0 ,Security violation 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x30370000)&0x80)==0x00)&&((per.l(ad:0x30370000+0x34)&0x80)==0x00)) group.long 0x44++0x03 line.long 0x00 "LPTGFCR,LP Tamper Glitch Filters Configuration" bitfld.long 0x00 31. " ETGF2_EN ,External tamper glitch filter 2 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF2 ,External tamper glitch filter 2" bitfld.long 0x00 23. " ETGF1_EN ,External tamper glitch filter 1 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF1 ,External tamper glitch filter 1" textline " " bitfld.long 0x00 7. " WMTGF_EN ,Wire-Mesh tamper glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WMTGF ,Wire-Mesh tamper glitch filter" "1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63" else rgroup.long 0x44++0x03 line.long 0x00 "LPTGFCR,LP Tamper Glitch Filters Configuration" bitfld.long 0x00 31. " ETGF2_EN ,External tamper glitch filter 2 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF2 ,External tamper glitch filter 2" bitfld.long 0x00 23. " ETGF1_EN ,External tamper glitch filter 1 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF1 ,External tamper glitch filter 1" textline " " bitfld.long 0x00 7. " WMTGF_EN ,Wire-Mesh tamper glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WMTGF ,Wire-Mesh tamper glitch filter" "1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63" endif if (((per.l(ad:0x30370000)&0x100)==0x00)&&((per.l(ad:0x30370000+0x34)&0x100)==0x00)) group.long 0x48++0x03 line.long 0x00 "LPTDCR,LP Tamper Detectors Configuration" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not asserted,Asserted" bitfld.long 0x00 24.--26. " VRC ,Voltage reference configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " HTDC ,High temperature detect configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " LTDC ,Low temp detect configuration" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (Por) observability flop" "Not detected,Detected" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (Pfd) observability flop" "Not detected,Detected" bitfld.long 0x00 12. " ET2P ,External tampering 2 polarity" "0,1" bitfld.long 0x00 11. " ET1P ,External tampering 1 polarity" "0,1" textline " " bitfld.long 0x00 10. " ET2_EN ,External tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " WMT2_EN ,Wire-Mesh tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 7. " WMT1_EN ,Wire-Mesh tampering 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VT_EN ,Voltage tamper enable" "Disabled,Enabled" bitfld.long 0x00 5. " TT_EN ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 4. " CT_EN ,Clock tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "LPTDCR,LP Tamper Detectors Configuration" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not asserted,Asserted" bitfld.long 0x00 24.--26. " VRC ,Voltage reference configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " HTDC ,High temperature detect configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " LTDC ,Low temp detect configuration" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (Por) observability flop" "Not detected,Detected" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (Pfd) observability flop" "Not detected,Detected" bitfld.long 0x00 12. " ET2P ,External tampering 2 polarity" "0,1" bitfld.long 0x00 11. " ET1P ,External tampering 1 polarity" "0,1" textline " " bitfld.long 0x00 10. " ET2_EN ,External tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " WMT2_EN ,Wire-Mesh tampering 2 enable" "Disabled,Enabled" bitfld.long 0x00 7. " WMT1_EN ,Wire-Mesh tampering 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VT_EN ,Voltage tamper enable" "Disabled,Enabled" bitfld.long 0x00 5. " TT_EN ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 4. " CT_EN ,Clock tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" endif group.long 0x4C++0x03 line.long 0x00 "LPSR,LP Status Register" rbitfld.long 0x00 31. " LPS ,LP section is secured" "Not secured,Secured" rbitfld.long 0x00 30. " LPNS ,LP section is Non-Secured" "No,Yes" eventfld.long 0x00 20. " SED ,Scan exit detected" "Not detected,Detected" eventfld.long 0x00 18. " SPO ,Set power off" "No effect,Clear" textline " " eventfld.long 0x00 17. " EO ,Power off request" "Not requested,Requested" eventfld.long 0x00 16. " ESVD ,External security violation detected" "Not detected,Detected" eventfld.long 0x00 10. " ET2D ,External tampering 2 detected" "Not detected,Detected" eventfld.long 0x00 9. " ET1D ,External tampering 1 detected" "Not detected,Detected" textline " " eventfld.long 0x00 8. " WMT2D ,Wire-Mesh tampering 2 detected" "Not detected,Detected" eventfld.long 0x00 7. " WMT1D ,Wire-Mesh tampering 1 detected" "Not detected,Detected" eventfld.long 0x00 6. " VTD ,Voltage tampering detected" "Not detected,Detected" eventfld.long 0x00 5. " TTD ,Temperature tamper detected" "Not detected,Detected" textline " " eventfld.long 0x00 4. " CTD ,Clock tampering detected" "Not detected,Detected" eventfld.long 0x00 3. " PGD ,Power supply glitch detected" "Not detected,Detected" eventfld.long 0x00 2. " MCR ,Monotonic counter rollover" "No rollover,Rollover" eventfld.long 0x00 1. " SRTCR ,Monotonic counter rollover" "No rollover,Rollover" textline " " eventfld.long 0x00 0. " LPTA ,LP time alarm" "No interrupt,Interrupt" if (((per.l(ad:0x30370000)&0x04)==0x00)&&((per.l(ad:0x30370000+0x34)&0x04)==0x00)&&((per.l(ad:0x30370000+0x38)&0x01)==0x00)) group.long 0x50++0x07 line.long 0x00 "LPSRTCMR,LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter" line.long 0x04 "LPSRTCLR,LP Secure Real Time Counter LSB Register" else rgroup.long 0x50++0x07 line.long 0x00 "LPSRTCMR,LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter" line.long 0x04 "LPSRTCLR,LP Secure Real Time Counter LSB Register" endif if ((per.l(ad:0x30370000+0x38)&0x02)==0x00) group.long 0x58++0x03 line.long 0x00 "LPTAR,LP Time Alarm Register" else rgroup.long 0x58++0x03 line.long 0x00 "LPTAR,LP Time Alarm Register" endif rgroup.long 0x5C++0x07 line.long 0x00 "LPSMCMR,LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic counter era bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic counter most-significant 16 bits" line.long 0x04 "LPSMCLR,LP Secure Monotonic Counter LSB Register" group.long 0x64++0x03 line.long 0x00 "LPPGDR,LP Power Glitch Detector Register" if (((per.l(ad:0x30370000)&0x20)==0x00)&&((per.l(ad:0x30370000+0x34)&0x20)==0x00)) group.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register" else rgroup.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register" endif sif cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4") if (((per.l(ad:0x30370000+0x3C)&0x04)==0x00)&&((per.l(ad:0x30370000)&0x02)==0x00)&&((per.l(ad:0x30370000+0x34)&0x02)==0x00)) group.byte 0x6C++0x03 line.byte 0x00 "LPZMKR0,LP Zeroizable Master Key Register 0" group.byte 0x70++0x03 line.byte 0x00 "LPZMKR1,LP Zeroizable Master Key Register 1" group.byte 0x74++0x03 line.byte 0x00 "LPZMKR2,LP Zeroizable Master Key Register 2" group.byte 0x78++0x03 line.byte 0x00 "LPZMKR3,LP Zeroizable Master Key Register 3" group.byte 0x7C++0x03 line.byte 0x00 "LPZMKR4,LP Zeroizable Master Key Register 4" group.byte 0x80++0x03 line.byte 0x00 "LPZMKR5,LP Zeroizable Master Key Register 5" group.byte 0x84++0x03 line.byte 0x00 "LPZMKR6,LP Zeroizable Master Key Register 6" group.byte 0x88++0x03 line.byte 0x00 "LPZMKR7,LP Zeroizable Master Key Register 7" else rgroup.byte 0x6C++0x03 line.byte 0x00 "LPZMKR0,LP Zeroizable Master Key Register 0" rgroup.byte 0x70++0x03 line.byte 0x00 "LPZMKR1,LP Zeroizable Master Key Register 1" rgroup.byte 0x74++0x03 line.byte 0x00 "LPZMKR2,LP Zeroizable Master Key Register 2" rgroup.byte 0x78++0x03 line.byte 0x00 "LPZMKR3,LP Zeroizable Master Key Register 3" rgroup.byte 0x7C++0x03 line.byte 0x00 "LPZMKR4,LP Zeroizable Master Key Register 4" rgroup.byte 0x80++0x03 line.byte 0x00 "LPZMKR5,LP Zeroizable Master Key Register 5" rgroup.byte 0x84++0x03 line.byte 0x00 "LPZMKR6,LP Zeroizable Master Key Register 6" rgroup.byte 0x88++0x03 line.byte 0x00 "LPZMKR7,LP Zeroizable Master Key Register 7" endif else if (((per.l(ad:0x30370000+0x3C)&0x04)==0x00)&&((per.l(ad:0x30370000)&0x02)==0x00)&&((per.l(ad:0x30370000+0x34)&0x02)==0x00)) group.byte 0x6C++0x31 line.byte 0x0 "LPZMKR0,LP Zeroizable Master Key Register 0" line.byte 0x1 "LPZMKR1,LP Zeroizable Master Key Register 1" line.byte 0x2 "LPZMKR2,LP Zeroizable Master Key Register 2" line.byte 0x3 "LPZMKR3,LP Zeroizable Master Key Register 3" line.byte 0x4 "LPZMKR4,LP Zeroizable Master Key Register 4" line.byte 0x5 "LPZMKR5,LP Zeroizable Master Key Register 5" line.byte 0x6 "LPZMKR6,LP Zeroizable Master Key Register 6" line.byte 0x7 "LPZMKR7,LP Zeroizable Master Key Register 7" line.byte 0x8 "LPZMKR8,LP Zeroizable Master Key Register 8" line.byte 0x9 "LPZMKR9,LP Zeroizable Master Key Register 9" line.byte 0xA "LPZMKR10,LP Zeroizable Master Key Register 10" line.byte 0xB "LPZMKR11,LP Zeroizable Master Key Register 11" line.byte 0xC "LPZMKR12,LP Zeroizable Master Key Register 12" line.byte 0xD "LPZMKR13,LP Zeroizable Master Key Register 13" line.byte 0xE "LPZMKR14,LP Zeroizable Master Key Register 14" line.byte 0xF "LPZMKR15,LP Zeroizable Master Key Register 15" line.byte 0x10 "LPZMKR16,LP Zeroizable Master Key Register 16" line.byte 0x11 "LPZMKR17,LP Zeroizable Master Key Register 17" line.byte 0x12 "LPZMKR18,LP Zeroizable Master Key Register 18" line.byte 0x13 "LPZMKR19,LP Zeroizable Master Key Register 19" line.byte 0x14 "LPZMKR20,LP Zeroizable Master Key Register 20" line.byte 0x15 "LPZMKR21,LP Zeroizable Master Key Register 21" line.byte 0x16 "LPZMKR22,LP Zeroizable Master Key Register 22" line.byte 0x17 "LPZMKR23,LP Zeroizable Master Key Register 23" line.byte 0x18 "LPZMKR24,LP Zeroizable Master Key Register 24" line.byte 0x19 "LPZMKR25,LP Zeroizable Master Key Register 25" line.byte 0x1A "LPZMKR26,LP Zeroizable Master Key Register 26" line.byte 0x1B "LPZMKR27,LP Zeroizable Master Key Register 27" line.byte 0x1C "LPZMKR28,LP Zeroizable Master Key Register 28" line.byte 0x1D "LPZMKR29,LP Zeroizable Master Key Register 29" line.byte 0x1E "LPZMKR30,LP Zeroizable Master Key Register 30" line.byte 0x1F "LPZMKR31,LP Zeroizable Master Key Register 31" else rgroup.byte 0x6C++0x31 line.byte 0x0 "LPZMKR0,LP Zeroizable Master Key Register 0" line.byte 0x1 "LPZMKR1,LP Zeroizable Master Key Register 1" line.byte 0x2 "LPZMKR2,LP Zeroizable Master Key Register 2" line.byte 0x3 "LPZMKR3,LP Zeroizable Master Key Register 3" line.byte 0x4 "LPZMKR4,LP Zeroizable Master Key Register 4" line.byte 0x5 "LPZMKR5,LP Zeroizable Master Key Register 5" line.byte 0x6 "LPZMKR6,LP Zeroizable Master Key Register 6" line.byte 0x7 "LPZMKR7,LP Zeroizable Master Key Register 7" line.byte 0x8 "LPZMKR8,LP Zeroizable Master Key Register 8" line.byte 0x9 "LPZMKR9,LP Zeroizable Master Key Register 9" line.byte 0xA "LPZMKR10,LP Zeroizable Master Key Register 10" line.byte 0xB "LPZMKR11,LP Zeroizable Master Key Register 11" line.byte 0xC "LPZMKR12,LP Zeroizable Master Key Register 12" line.byte 0xD "LPZMKR13,LP Zeroizable Master Key Register 13" line.byte 0xE "LPZMKR14,LP Zeroizable Master Key Register 14" line.byte 0xF "LPZMKR15,LP Zeroizable Master Key Register 15" line.byte 0x10 "LPZMKR16,LP Zeroizable Master Key Register 16" line.byte 0x11 "LPZMKR17,LP Zeroizable Master Key Register 17" line.byte 0x12 "LPZMKR18,LP Zeroizable Master Key Register 18" line.byte 0x13 "LPZMKR19,LP Zeroizable Master Key Register 19" line.byte 0x14 "LPZMKR20,LP Zeroizable Master Key Register 20" line.byte 0x15 "LPZMKR21,LP Zeroizable Master Key Register 21" line.byte 0x16 "LPZMKR22,LP Zeroizable Master Key Register 22" line.byte 0x17 "LPZMKR23,LP Zeroizable Master Key Register 23" line.byte 0x18 "LPZMKR24,LP Zeroizable Master Key Register 24" line.byte 0x19 "LPZMKR25,LP Zeroizable Master Key Register 25" line.byte 0x1A "LPZMKR26,LP Zeroizable Master Key Register 26" line.byte 0x1B "LPZMKR27,LP Zeroizable Master Key Register 27" line.byte 0x1C "LPZMKR28,LP Zeroizable Master Key Register 28" line.byte 0x1D "LPZMKR29,LP Zeroizable Master Key Register 29" line.byte 0x1E "LPZMKR30,LP Zeroizable Master Key Register 30" line.byte 0x1F "LPZMKR31,LP Zeroizable Master Key Register 31" endif endif if (((per.l(ad:0x30370000)&0x20)==0x00)&&((per.l(ad:0x30370000+0x34)&0x20)==0x00)) group.long 0x90++0x03 line.long 0x00 "LPGPR0_30,SNVS_LP General Purposes 0" group.long 0x94++0x03 line.long 0x00 "LPGPR0_31,SNVS_LP General Purposes 1" group.long 0x98++0x03 line.long 0x00 "LPGPR0_32,SNVS_LP General Purposes 2" group.long 0x9C++0x03 line.long 0x00 "LPGPR0_33,SNVS_LP General Purposes 3" else rgroup.long 0x90++0x03 line.long 0x00 "LPGPR0_30,SNVS_LP General Purposes 0" rgroup.long 0x94++0x03 line.long 0x00 "LPGPR0_31,SNVS_LP General Purposes 1" rgroup.long 0x98++0x03 line.long 0x00 "LPGPR0_32,SNVS_LP General Purposes 2" rgroup.long 0x9C++0x03 line.long 0x00 "LPGPR0_33,SNVS_LP General Purposes 3" endif if (((per.l(ad:0x30370000)&0x100)==0x00)&&((per.l(ad:0x30370000+0x34)&0x100)==0x00)) group.long 0xA0++0x03 line.long 0x00 "LPTDC2R,LP Tamper Detectors Config 2" bitfld.long 0x00 23. " ET10P ,External tampering 10 polarity" "Low,High" bitfld.long 0x00 22. " ET9P ,External tampering 9 polarity" "Low,High" bitfld.long 0x00 21. " ET8P ,External tampering 8 polarity" "Low,High" bitfld.long 0x00 20. " ET7P ,External tampering 7 polarity" "Low,High" textline " " bitfld.long 0x00 19. " ET6P ,External tampering 6 polarity" "Low,High" bitfld.long 0x00 18. " ET5P ,External tampering 5 polarity" "Low,High" bitfld.long 0x00 17. " ET4P ,External tampering 4 polarity" "Low,High" bitfld.long 0x00 16. " ET3P ,External tampering 3 polarity" "Low,High" textline " " bitfld.long 0x00 7. " ET10_EN ,External tampering 10 enable" "Disabled,Enabled" bitfld.long 0x00 6. " ET9_EN ,External tampering 9 enable" "Disabled,Enabled" bitfld.long 0x00 5. " ET8_EN ,External tampering 8 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ET7_EN ,External tampering 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ET6_EN ,External tampering 6 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ET5_EN ,External tampering 5 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ET4_EN ,External tampering 4 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ET3_EN ,External tampering 3 enable" "Disabled,Enabled" else rgroup.long 0xA0++0x03 line.long 0x00 "LPTDC2R,LP Tamper Detectors Config 2" bitfld.long 0x00 23. " ET10P ,External tampering 10 polarity" "Low,High" bitfld.long 0x00 22. " ET9P ,External tampering 9 polarity" "Low,High" bitfld.long 0x00 21. " ET8P ,External tampering 8 polarity" "Low,High" bitfld.long 0x00 20. " ET7P ,External tampering 7 polarity" "Low,High" textline " " bitfld.long 0x00 19. " ET6P ,External tampering 6 polarity" "Low,High" bitfld.long 0x00 18. " ET5P ,External tampering 5 polarity" "Low,High" bitfld.long 0x00 17. " ET4P ,External tampering 4 polarity" "Low,High" bitfld.long 0x00 16. " ET3P ,External tampering 3 polarity" "Low,High" textline " " bitfld.long 0x00 7. " ET10_EN ,External tampering 10 enable" "Disabled,Enabled" bitfld.long 0x00 6. " ET9_EN ,External tampering 9 enable" "Disabled,Enabled" bitfld.long 0x00 5. " ET8_EN ,External tampering 8 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ET7_EN ,External tampering 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ET6_EN ,External tampering 6 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ET5_EN ,External tampering 5 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ET4_EN ,External tampering 4 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ET3_EN ,External tampering 3 enable" "Disabled,Enabled" endif group.long 0xA4++0x03 line.long 0x00 "LPTDSR,LP Tamper Detectors Status" eventfld.long 0x00 7. " ET10D ,External tampering 10 detected" "Not detected,Detected" eventfld.long 0x00 6. " ET9D ,External tampering 9 detected" "Not detected,Detected" eventfld.long 0x00 5. " ET8D ,External tampering 8 detected" "Not detected,Detected" eventfld.long 0x00 4. " ET7D ,External tampering 7 detected" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ET6D ,External tampering 6 detected" "Not detected,Detected" eventfld.long 0x00 2. " ET5D ,External tampering 5 detected" "Not detected,Detected" eventfld.long 0x00 1. " ET4D ,External tampering 4 detected" "Not detected,Detected" eventfld.long 0x00 0. " ET3D ,External tampering 3 detected" "Not detected,Detected" if (((per.l(ad:0x30370000)&0x80)==0x00)&&((per.l(ad:0x30370000+0x34)&0x80)==0x00)) group.long 0xA8++0x07 line.long 0x00 "LPTGF1CR,LP Tamper Glitch Filter 1 Configuration" bitfld.long 0x00 31. " ETGF6_EN ,External tamper glitch filter 6 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF6 ,External tamper glitch filter 6" bitfld.long 0x00 23. " ETGF5_EN ,External tamper glitch filter 5 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF5 ,External tamper glitch filter 5" textline " " bitfld.long 0x00 15. " ETGF4_EN ,External tamper glitch filter 4 enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ETGF4 ,External tamper glitch filter 4" bitfld.long 0x00 7. " ETGF3_EN ,External tamper glitch filter 3 enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " ETGF3 ,External tamper glitch filter 3" line.long 0x04 "LPTGF2CR,LP Tamper Glitch Filter 2 Configuration" bitfld.long 0x04 31. " ETGF10_EN ,External tamper glitch filter 10 enable" "Disabled,Enabled" hexmask.long.byte 0x04 24.--30. 1. " ETGF10 ,External tamper glitch filter 10" bitfld.long 0x04 23. " ETGF9_EN ,External tamper glitch filter 9 enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--22. 1. " ETGF9 ,External tamper glitch filter 9" textline " " bitfld.long 0x04 15. " ETGF8_EN ,External tamper glitch filter 8 enable" "Disabled,Enabled" hexmask.long.byte 0x04 8.--14. 1. " ETGF8 ,External tamper glitch filter 8" bitfld.long 0x04 7. " ETGF7_EN ,External tamper glitch filter 7 enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--6. 1. " ETGF7 ,External tamper glitch filter 7" else rgroup.long 0xA8++0x07 line.long 0x00 "LPTGF1CR,LP Tamper Glitch Filter 1 Configuration" bitfld.long 0x00 31. " ETGF6_EN ,External tamper glitch filter 6 enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " ETGF6 ,External tamper glitch filter 6" bitfld.long 0x00 23. " ETGF5_EN ,External tamper glitch filter 5 enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--22. 1. " ETGF5 ,External tamper glitch filter 5" textline " " bitfld.long 0x00 15. " ETGF4_EN ,External tamper glitch filter 4 enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ETGF4 ,External tamper glitch filter 4" bitfld.long 0x00 7. " ETGF3_EN ,External tamper glitch filter 3 enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " ETGF3 ,External tamper glitch filter 3" line.long 0x04 "LPTGF2CR,LP Tamper Glitch Filter 2 Configuration" bitfld.long 0x04 31. " ETGF10_EN ,External tamper glitch filter 10 enable" "Disabled,Enabled" hexmask.long.byte 0x04 24.--30. 1. " ETGF10 ,External tamper glitch filter 10" bitfld.long 0x04 23. " ETGF9_EN ,External tamper glitch filter 9 enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--22. 1. " ETGF9 ,External tamper glitch filter 9" textline " " bitfld.long 0x04 15. " ETGF8_EN ,External tamper glitch filter 8 enable" "Disabled,Enabled" hexmask.long.byte 0x04 8.--14. 1. " ETGF8 ,External tamper glitch filter 8" bitfld.long 0x04 7. " ETGF7_EN ,External tamper glitch filter 7 enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--6. 1. " ETGF7 ,External tamper glitch filter 7" endif if ((per.l(ad:0x30370000+0x38)&0x02)==0x00) wgroup.long 0xC0++0x13 line.long 0x0 "LPAT1CR,LP Active Tamper 1 Configuration" hexmask.long.word 0x0 16.--31. 1. " POLYNOMIAL ,Active tamper 1 polynomial" hexmask.long.word 0x0 0.--15. 1. " SEED ,Active tamper 1 initial seed" line.long 0x4 "LPAT2CR,LP Active Tamper 2 Configuration" hexmask.long.word 0x4 16.--31. 1. " POLYNOMIAL ,Active tamper 2 polynomial" hexmask.long.word 0x4 0.--15. 1. " SEED ,Active tamper 2 initial seed" line.long 0x8 "LPAT3CR,LP Active Tamper 3 Configuration" hexmask.long.word 0x8 16.--31. 1. " POLYNOMIAL ,Active tamper 3 polynomial" hexmask.long.word 0x8 0.--15. 1. " SEED ,Active tamper 3 initial seed" line.long 0xC "LPAT4CR,LP Active Tamper 4 Configuration" hexmask.long.word 0xC 16.--31. 1. " POLYNOMIAL ,Active tamper 4 polynomial" hexmask.long.word 0xC 0.--15. 1. " SEED ,Active tamper 4 initial seed" line.long 0x10 "LPAT5CR,LP Active Tamper 5 Configuration" hexmask.long.word 0x10 16.--31. 1. " POLYNOMIAL ,Active tamper 5 polynomial" hexmask.long.word 0x10 0.--15. 1. " SEED ,Active tamper 5 initial seed" else rgroup.long 0xC0++0x13 line.long 0x0 "LPAT1CR,LP Active Tamper 1 Configuration" hexmask.long.word 0x0 16.--31. 1. " POLYNOMIAL ,Active tamper 1 polynomial" hexmask.long.word 0x0 0.--15. 1. " SEED ,Active tamper 1 initial seed" line.long 0x4 "LPAT2CR,LP Active Tamper 2 Configuration" hexmask.long.word 0x4 16.--31. 1. " POLYNOMIAL ,Active tamper 2 polynomial" hexmask.long.word 0x4 0.--15. 1. " SEED ,Active tamper 2 initial seed" line.long 0x8 "LPAT3CR,LP Active Tamper 3 Configuration" hexmask.long.word 0x8 16.--31. 1. " POLYNOMIAL ,Active tamper 3 polynomial" hexmask.long.word 0x8 0.--15. 1. " SEED ,Active tamper 3 initial seed" line.long 0xC "LPAT4CR,LP Active Tamper 4 Configuration" hexmask.long.word 0xC 16.--31. 1. " POLYNOMIAL ,Active tamper 4 polynomial" hexmask.long.word 0xC 0.--15. 1. " SEED ,Active tamper 4 initial seed" line.long 0x10 "LPAT5CR,LP Active Tamper 5 Configuration" hexmask.long.word 0x10 16.--31. 1. " POLYNOMIAL ,Active tamper 5 polynomial" hexmask.long.word 0x10 0.--15. 1. " SEED ,Active tamper 5 initial seed" endif group.long 0xE0++0x0F line.long 0x00 "LPATCTLR,LP Active Tamper Control" bitfld.long 0x00 20. " AT5_PAD_EN ,Active tamper 5 pad out enable" "Disabled,Enabled" bitfld.long 0x00 19. " AT4_PAD_EN ,Active tamper 4 pad out enable" "Disabled,Enabled" bitfld.long 0x00 18. " AT3_PAD_EN ,Active tamper 3 pad out enable" "Disabled,Enabled" bitfld.long 0x00 17. " AT2_PAD_EN ,Active tamper 2 pad out enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " AT1_PAD_EN ,Active tamper 1 pad out enable" "Disabled,Enabled" bitfld.long 0x00 4. " AT5_EN ,Active tamper 5 enable" "Disabled,Enabled" bitfld.long 0x00 3. " AT5_EN ,Active tamper 4 enable" "Disabled,Enabled" bitfld.long 0x00 2. " AT5_EN ,Active tamper 3 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " AT5_EN ,Active tamper 2 enable" "Disabled,Enabled" bitfld.long 0x00 0. " AT5_EN ,Active tamper 1 enable" "Disabled,Enabled" line.long 0x04 "LPATCLKR,LP Active Tamper Clock Control" bitfld.long 0x04 16.--17. " AT5_CLK_CTL ,Active tamper 5 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 12.--13. " AT4_CLK_CTL ,Active tamper 4 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 8.--9. " AT3_CLK_CTL ,Active tamper 3 clock control" "16hz,8hz,4hz,2hz" bitfld.long 0x04 4.--5. " AT2_CLK_CTL ,Active tamper 2 clock control" "16hz,8hz,4hz,2hz" textline " " bitfld.long 0x04 0.--1. " AT1_CLK_CTL ,Active tamper 1 clock control" "16hz,8hz,4hz,2hz" line.long 0x08 "LPATRC1R,LP Active Tamper Routing Control 1" bitfld.long 0x08 28.--30. " ET8RCTL ,External tamper 8 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 24.--26. " ET7RCTL ,External tamper 7 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 20.--22. " ET6RCTL ,External tamper 6 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 16.--18. " ET5RCTL ,External tamper 5 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." textline " " bitfld.long 0x08 12.--14. " ET4RCTL ,External tamper 4 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 8.--10. " ET3RCTL ,External tamper 3 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 4.--6. " ET2RCTL ,External tamper 2 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x08 0.--2. " ET1RCTL ,External tamper 1 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." line.long 0x0C "LPATRC2R,LP Active Tamper Routing Control 2" bitfld.long 0x0C 4.--6. " ET10RCTL ,External tamper 10 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." bitfld.long 0x0C 0.--2. " ET9RCTL ,External tamper 9 routing control" "Passive input,Active tamper 1,Active tamper 2,Active tamper 3,Active tamper 4,Active tamper 5,?..." rgroup.long 0xBF8++0x07 line.long 0x00 "HPVIDR1,HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,SNVS block ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,SNVS block major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,SNVS block minor version number" line.long 0x04 "HPVIDR2,HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,Era of the IP design" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,SNVS integration option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,SNVS ECO revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,SNVS configuration option" width 0x0B tree.end tree "SRC (System Reset Controller)" base ad:0x30390000 width 14. if ((per.l(ad:0x30390000)&0xC0000000)==0xC0000000) group.long 0x00++0x03 line.long 0x00 "SCR,SRC Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." elif ((per.l(ad:0x30390000)&0xC0000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "SCR,SRC Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." elif ((per.l(ad:0x30390000)&0xC0000000)==0x40000000) group.long 0x00++0x0F line.long 0x00 "SCR,SRC Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." else group.long 0x00++0x0F line.long 0x00 "SCR,SRC Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 4.--7. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" ",,,,,Masked,,,,,Not masked,?..." endif if (((per.l(ad:0x30390000+0x04)&0xC0000000)==0xC0000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x02)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 13. " A7_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 9. " A7_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" textline " " bitfld.long 0x00 5. " A7_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 1. " A7_CORE_POR_RESET1 ,POR reset for A7 core1 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0xC0000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x00)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0x80000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x02)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 13. " A7_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 9. " A7_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" textline " " bitfld.long 0x00 5. " A7_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 1. " A7_CORE_POR_RESET1 ,POR reset for A7 core1 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0x80000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x00)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0x40000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x02)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 13. " A7_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 9. " A7_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" textline " " bitfld.long 0x00 5. " A7_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 1. " A7_CORE_POR_RESET1 ,POR reset for A7 core1 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0x40000000)&&((per.l(ad:0x30390000+0x08)&0x02)==0x02)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" elif (((per.l(ad:0x30390000+0x04)&0xC0000000)==0x00)&&((per.l(ad:0x30390000+0x08)&0x02)==0x02)) group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 13. " A7_ETM_RESET1 ,Software reset for core1 ETM only" "No reset,Reset" bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 9. " A7_DBG_RESET1 ,Software reset for core1 debug only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" textline " " bitfld.long 0x00 5. " A7_CORE_RESET1 ,Software reset for core1 only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 1. " A7_CORE_POR_RESET1 ,POR reset for A7 core1 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" else group.long 0x04++0x03 line.long 0x00 "A7RCR0,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " A7_L2RESET ,Software reset for A7 snoop control unit" "No reset,Reset" bitfld.long 0x00 20. " A7_SOC_DBG_RESET ,Software reset for system level debug reset" "No reset,Reset" bitfld.long 0x00 16.--19. " MASK_WDOG1_RST ,Mask wdog1_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 12. " A7_ETM_RESET0 ,Software reset for core0 ETM only" "No reset,Reset" bitfld.long 0x00 8. " A7_DBG_RESET0 ,Software reset for core0 debug only" "No reset,Reset" bitfld.long 0x00 4. " A7_CORE_RESET0 ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 0. " A7_CORE_POR_RESET0 ,POR reset for A7 core0 only" "No reset,Reset" endif textline " " if ((per.l(ad:0x30390000+0x08)&0xC0000000)==0xC0000000) group.long 0x08++0x03 line.long 0x00 "A7RCR1,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 1. " A7_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" elif ((per.l(ad:0x30390000+0x08)&0xC0000000)==0x80000000) group.long 0x08++0x03 line.long 0x00 "A7RCR1,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 1. " A7_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" elif ((per.l(ad:0x30390000+0x08)&0xC0000000)==0x40000000) group.long 0x08++0x03 line.long 0x00 "A7RCR1,A7 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 1. " A7_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "A7RCR1,A7 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 1. " A7_CORE1_ENABLE ,Core 1 enable" "Disabled,Enabled" endif if ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0xC0000200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0xC0000000) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0x80000200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0x80000000) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0x40000200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0x40000000) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" elif ((per.l(ad:0x30390000+0x0C)&0xC0000200)==0x200) group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 8. " WDOG3_RST_OPTION_M4 ,Wdog3_rst_b option for M4" "M4 core reset,M4 core and platform reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" else group.long 0x0C++0x03 line.long 0x00 "M4RCR,M4 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " WDOG3_RST_OPTION ,Wdog3_rst_b option" "M4 reset,Global reset" bitfld.long 0x00 4.--7. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." textline " " bitfld.long 0x00 3. " ENABLE_M4 ,Enable M4" "Disabled,Enabled" bitfld.long 0x00 2. " SW_M4P_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 1. " SW_M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x14)&0xC0000000)==0xC0000000) group.long 0x14++0x03 line.long 0x00 "ERCR,EIM Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 0. " EIM_RST ,EIM controller reset" "Reset,No reset" elif ((per.l(ad:0x30390000+0x14)&0xC0000000)==0x80000000) group.long 0x14++0x03 line.long 0x00 "ERCR,EIM Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 0. " EIM_RST ,EIM controller reset" "Reset,No reset" elif ((per.l(ad:0x30390000+0x14)&0xC0000000)==0x40000000) group.long 0x14++0x03 line.long 0x00 "ERCR,EIM Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 0. " EIM_RST ,EIM controller reset" "Reset,No reset" else group.long 0x14++0x03 line.long 0x00 "ERCR,EIM Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 0. " EIM_RST ,EIM controller reset" "Reset,No reset" endif if ((per.l(ad:0x30390000+0x1C)&0xC0000000)==0xC0000000) group.long 0x1C++0x13 line.long 0x00 "HSICPHY_RCR,HSIC PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 1. " HSICPHY_PORT_RST ,HSIC PHY port reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x1C)&0xC0000000)==0x80000000) group.long 0x1C++0x13 line.long 0x00 "HSICPHY_RCR,HSIC PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" bitfld.long 0x00 1. " HSICPHY_PORT_RST ,HSIC PHY port reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x1C)&0xC0000000)==0x40000000) group.long 0x1C++0x13 line.long 0x00 "HSICPHY_RCR,HSIC PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 1. " HSICPHY_PORT_RST ,HSIC PHY port reset" "No reset,Reset" else group.long 0x1C++0x13 line.long 0x00 "HSICPHY_RCR,HSIC PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 1. " HSICPHY_PORT_RST ,HSIC PHY port reset" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x20)&0xC0000000)==0xC0000000) group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " USBPHY1_PORT_RST ,USB OTG PHY1 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY1_POR ,USB OTG PHY 1 POR" "No reset,Reset" elif ((per.l(ad:0x30390000+0x20)&0xC0000000)==0x80000000) group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " USBPHY1_PORT_RST ,USB OTG PHY1 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY1_POR ,USB OTG PHY 1 POR" "No reset,Reset" elif ((per.l(ad:0x30390000+0x20)&0xC0000000)==0x40000000) group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " USBPHY1_PORT_RST ,USB OTG PHY1 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY1_POR ,USB OTG PHY 1 POR" "No reset,Reset" else group.long 0x20++0x03 line.long 0x00 "USBOPHY1_RCR,USB OTG PHY1 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " USBPHY1_PORT_RST ,USB OTG PHY1 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY1_POR ,USB OTG PHY 1 POR" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x24)&0xC0000000)==0xC0000000) group.long 0x24++0x03 line.long 0x00 "USBOPHY2_RCR,USB OTG PHY2 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " USBPHY2_PORT_RST ,USB OTG PHY2 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY2_POR ,USB OTG PHY 2 POR" "No reset,Reset" elif ((per.l(ad:0x30390000+0x24)&0xC0000000)==0x80000000) group.long 0x24++0x03 line.long 0x00 "USBOPHY2_RCR,USB OTG PHY2 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " USBPHY2_PORT_RST ,USB OTG PHY2 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY2_POR ,USB OTG PHY 2 POR" "No reset,Reset" elif ((per.l(ad:0x30390000+0x24)&0xC0000000)==0x40000000) group.long 0x24++0x03 line.long 0x00 "USBOPHY2_RCR,USB OTG PHY2 Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " USBPHY2_PORT_RST ,USB OTG PHY2 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY2_POR ,USB OTG PHY 2 POR" "No reset,Reset" else group.long 0x24++0x03 line.long 0x00 "USBOPHY2_RCR,USB OTG PHY2 Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " USBPHY2_PORT_RST ,USB OTG PHY2 port reset" "No reset,Reset" bitfld.long 0x00 0. " USBPHY2_POR ,USB OTG PHY 2 POR" "No reset,Reset" endif if ((per.l(ad:0x30390000+0x28)&0xC0000000)==0xC0000000) group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_PHY_SRST ,MIPI PHY slave reset" "No reset,Reset" bitfld.long 0x00 1. " MIPI_PHY_MRST ,MIPI PHY master reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x28)&0xC0000000)==0x80000000) group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 2. " MIPI_PHY_SRST ,MIPI PHY slave reset" "No reset,Reset" bitfld.long 0x00 1. " MIPI_PHY_MRST ,MIPI PHY master reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x28)&0xC0000000)==0x40000000) group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 2. " MIPI_PHY_SRST ,MIPI PHY slave reset" "No reset,Reset" bitfld.long 0x00 1. " MIPI_PHY_MRST ,MIPI PHY master reset" "No reset,Reset" else group.long 0x28++0x03 line.long 0x00 "MIPIPHY_RCR,MIPI PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 2. " MIPI_PHY_SRST ,MIPI PHY slave reset" "No reset,Reset" bitfld.long 0x00 1. " MIPI_PHY_MRST ,MIPI PHY master reset" "No reset,Reset" endif textline " " if ((per.l(ad:0x30390000+0x2C)&0xC0000000)==0xC0000000) group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" bitfld.long 0x00 13. " PCIE_CTRL_CFG_L1_MAC ,Pcie_ctrl_cfg_l1_mac_powerdown_override_to_p2_en" "Disabled,Enabled" bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" textline " " bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" textline " " bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x2C)&0xC0000000)==0x80000000) group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" bitfld.long 0x00 13. " PCIE_CTRL_CFG_L1_MAC ,Pcie_ctrl_cfg_l1_mac_powerdown_override_to_p2_en" "Disabled,Enabled" bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" textline " " bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" textline " " bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x2C)&0xC0000000)==0x40000000) group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" bitfld.long 0x00 13. " PCIE_CTRL_CFG_L1_MAC ,Pcie_ctrl_cfg_l1_mac_powerdown_override_to_p2_en" "Disabled,Enabled" bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" textline " " bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" textline " " bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" else group.long 0x2C++0x03 line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 14. " PCIE_CTRL_SYS_INT ,PCIE_CTRL_SYS_INT" "0,1" bitfld.long 0x00 13. " PCIE_CTRL_CFG_L1_MAC ,Pcie_ctrl_cfg_l1_mac_powerdown_override_to_p2_en" "Disabled,Enabled" bitfld.long 0x00 12. " PCIE_CTRL_CFG_L1_AUX ,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCIE_CTRL_APPS_TURNOFF ,Pcie_ctrl_apps_pm_xmt_turnoff" "Turned on,Turned off" bitfld.long 0x00 10. " PCIE_CTRL_APPS_PME ,Pcie_ctrl_apps_pm_xmt_pme" "0,1" bitfld.long 0x00 9. " PCIE_CTRL_APPS_EXIT ,Pcie_ctrl_app_req_exit_l1" "0,1" textline " " bitfld.long 0x00 8. " PCIE_CTRL_APPS_ENTER ,Pcie_ctrl_app_req_entr_l1" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_CTRL_APPS_READY ,Pcie_ctrl_app_ready_entr_l23" "Not ready,Ready" bitfld.long 0x00 6. " PCIE_CTRL_APPS_EN ,Pcie_ctrl_app_ltssm_enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PCIE_CTRL_APPS_RST ,Pcie_ctrl_app_init_rst" "No reset,Reset" bitfld.long 0x00 4. " PCIE_CTRL_APPS_CLK_REQ ,Pcie_ctrl_app_clk_req_n" "Not requested,Requested" bitfld.long 0x00 3. " PCIEPHY_PERST ,Pciephy_perst" "0,1" textline " " bitfld.long 0x00 2. " PCIEPHY_BTN ,PCIE PHY button" "0,1" bitfld.long 0x00 1. " PCIEPHY_G_RST ,PCIE PHY global reset" "No reset,Reset" endif rgroup.long 0x58++0x03 line.long 0x00 "SBMR1,SRC Boot Mode Register 1" hexmask.long.byte 0x00 24.--31. 1. " BOOT_CFG4 ,BOOT_CFG4" hexmask.long.byte 0x00 16.--23. 1. " BOOT_CFG3 ,BOOT_CFG3" textline " " hexmask.long.byte 0x00 8.--15. 1. " BOOT_CFG2 ,BOOT_CFG2" hexmask.long.byte 0x00 0.--7. 1. " BOOT_CFG1 ,BOOT_CFG1" group.long 0x5C++0x03 line.long 0x00 "SRSR,SRC Reset Status Register" bitfld.long 0x00 9. " TEMPSENSE_RST_B ,Temper sensor software reset" "No reset,Reset" eventfld.long 0x00 8. " WDOG4_RST_B ,IC watchdog4 Time-out reset" "No reset,Reset" eventfld.long 0x00 7. " WDOG3_RST_B ,IC watchdog3 Time-out reset" "No reset,Reset" textline " " eventfld.long 0x00 6. " JTAG_SW_RST ,JTAG software reset" "No reset,Reset" eventfld.long 0x00 5. " JTAG-_RST_B ,HIGH - Z JTAG reset" "No reset,Reset" eventfld.long 0x00 4. " WDOG1_RST_B ,IC watchdog1 Time-out reset" "No reset,Reset" textline " " eventfld.long 0x00 3. " IPP_USER_RESET_B ,Ipp_user_reset_b qualified reset" "No reset,Reset" eventfld.long 0x00 2. " CSU_RESET_B ,Csu_reset_b input" "No reset,Reset" eventfld.long 0x00 0. " IPP_RESET_B ,Ipp_reset_b pin" "No reset,Reset" rgroup.long 0x68++0x07 line.long 0x00 "SISR,SRC Interrupt Status Register" bitfld.long 0x00 9. " M4P_PASSED_RESET ,Interrupt generated to indicate that m4 platform passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 8. " M4C_PASSED_RESET ,Interrupt generated to indicate that m4 core passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 4. " MIPIPHY_PASSED_RESET ,Interrupt generated to indicate that MIPI PHY passed software reset and is ready to be used" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " OTGPHY2_PASSED_RESET ,Interrupt generated to indicate that OTG PHY2 passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 2. " OTGPHY1_PASSED_RESET ,Interrupt generated to indicate that OTG PHY1 passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 1. " HSICPHY_PASSED_RESET ,Interrupt generated to indicate that HSIC PHY passed software reset and is ready to be used" "No interrupt,Interrupt" line.long 0x04 "SIMR,SRC Interrupt Mask Register" bitfld.long 0x04 9. " MASK_M4P_PASSED_RESET ,Mask interrupt generation due to m4 platform passed reset" "Not masked,Masked" bitfld.long 0x04 8. " MASK_M4C_PASSED_RESET ,Mask interrupt generation due to m4 core passed reset" "Not masked,Masked" bitfld.long 0x04 4. " MASK_MIPIPHY_PASSED_RESET ,Mask interrupt generation due to MIPI PHY passed reset" "Not masked,Masked" textline " " bitfld.long 0x04 3. " MASK_OTGPHY2_PASSED_RESET ,Mask interrupt generation due to OTG PHY2 passed reset" "Not masked,Masked" bitfld.long 0x04 2. " MASK_OTGPHY1_PASSED_RESET ,Mask interrupt generation due to OTG PHY1 passed reset" "Not masked,Masked" bitfld.long 0x04 1. " MASK_HSICPHY_PASSED_RESET ,Mask interrupt generation due to HSIC PHY passed reset" "Not masked,Masked" if ((per.l(ad:0x30390000+0x70)&0x3000000)==0x2000000) group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 4. " BT_FUSE_SEL ,Determines whether using fuses for boot configuration or gpio/serial loader" "Serial loader,Fuses" bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "No,Yes" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" elif ((per.l(ad:0x30390000+0x70)&0x3000000)==0x00) group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 4. " BT_FUSE_SEL ,Determines whether using fuses for boot configuration or GPIO /serial loader" "Gpios,Fuses" bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "No,Yes" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" else group.long 0x70++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B" "Boot from fuses,Serial downloader,Internal boot,?..." bitfld.long 0x00 3. " DIR_BT_DIS ,Direct external memory boot disable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " SEC_CONFIG ,Security configuration" "FAB (Open),Open,Closed,Closed" endif group.long 0x74++0x1F line.long 0x00 "GPR1,SRC General Purpose Register 1" line.long 0x04 "GPR2,SRC General Purpose Register 2" line.long 0x08 "GPR3,SRC General Purpose Register 3" line.long 0x0C "GPR4,SRC General Purpose Register 4" line.long 0x10 "GPR5,SRC General Purpose Register 5" line.long 0x14 "GPR6,SRC General Purpose Register 6" line.long 0x18 "GPR7,SRC General Purpose Register 7" line.long 0x1C "GPR8,SRC General Purpose Register 8" group.long 0x98++0x03 line.long 0x00 "GPR10,SRC General Purpose Register 10" textline " " if ((per.l(ad:0x30390000+0x1000)&0xC0000000)==0xC0000000) group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " rbitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" rbitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " DDRC_CORE_RST ,DDR controller core_ddrc_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 0. " DDRC_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x1000)&0xC0000000)==0x80000000) group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " DOMAIN3 ,Domain3 assignment control" "Not assigned,Assigned" bitfld.long 0x00 26. " DOMAIN2 ,Domain2 assignment control" "Not assigned,Assigned" bitfld.long 0x00 25. " DOMAIN1 ,Domain1 assignment control" "Not assigned,Assigned" bitfld.long 0x00 24. " DOMAIN0 ,Domain0 assignment control" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " DDRC_CORE_RST ,DDR controller core_ddrc_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 0. " DDRC_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" elif ((per.l(ad:0x30390000+0x1000)&0xC0000000)==0x40000000) group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" rbitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" rbitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " DDRC_CORE_RST ,DDR controller core_ddrc_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 0. " DDRC_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register" bitfld.long 0x00 31. " DOM_EN ,Domain control enable for this register" "Disabled,Enabled" bitfld.long 0x00 30. " LOCK ,Domain control bits lock" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " DDRC_CORE_RST ,DDR controller core_ddrc_rstn and aresetn" "No reset,Reset" bitfld.long 0x00 0. " DDRC_PRST ,DDR controller preset and DDR PHY reset" "No reset,Reset" endif width 0x0B tree.end tree "OCOTP_CTRL (On-Chip OTP Controller)" base ad:0x30350000 width 18. group.long 0x00++0x13 line.long 0x00 "CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,Write 0x3e77 to enable OTP write accesses" bitfld.long 0x00 12. " CRC_FAIL ,Set by controller when calculated CRC value is not equal to appointed CRC fuse word" "Not failed,Failed" bitfld.long 0x00 11. " CRC_TEST ,Calculates CRC32 according to start address and end address in CRC_ADDR register" "Not calculated,Calculated" bitfld.long 0x00 10. " RELOAD_SHADOWS ,Forces re-loading all the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x00 9. " ERROR ,Set by the controller when an access to a locked region (Otp or shadow register) is requested" "No error,Error" rbitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" bitfld.long 0x00 0.--3. " ADDR ,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CTRL_SET,OTP Controller Control Set Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,Write 0x3e77 to enable OTP write accesses" bitfld.long 0x04 12. " CRC_FAIL ,Set by controller when calculated CRC value is not equal to appointed CRC fuse word" "Not failed,Failed" bitfld.long 0x04 11. " CRC_TEST ,Calculates CRC32 according to start address and end address in CRC_ADDR register" "Not calculated,Calculated" bitfld.long 0x04 10. " RELOAD_SHADOWS ,Forces re-loading all the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x04 9. " ERROR ,Set by the controller when an access to a locked region (Otp or shadow register) is requested" "No error,Error" rbitfld.long 0x04 8. " BUSY ,OTP controller status bit" "Not busy,Busy" bitfld.long 0x04 0.--3. " ADDR ,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CTRL_CLR,OTP Controller Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,Write 0x3e77 to enable OTP write accesses" bitfld.long 0x08 12. " CRC_FAIL ,Set by controller when calculated CRC value is not equal to appointed CRC fuse word" "Not failed,Failed" bitfld.long 0x08 11. " CRC_TEST ,Calculates CRC32 according to start address and end address in CRC_ADDR register" "Not calculated,Calculated" bitfld.long 0x08 10. " RELOAD_SHADOWS ,Forces re-loading all the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x08 9. " ERROR ,Set by the controller when an access to a locked region (Otp or shadow register) is requested" "No error,Error" rbitfld.long 0x08 8. " BUSY ,OTP controller status bit" "Not busy,Busy" bitfld.long 0x08 0.--3. " ADDR ,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CTRL_TOG,OTP Controller Control Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " WR_UNLOCK ,Write 0x3e77 to enable OTP write accesses" bitfld.long 0x0C 12. " CRC_FAIL ,Set by controller when calculated CRC value is not equal to appointed CRC fuse word" "Not failed,Failed" bitfld.long 0x0C 11. " CRC_TEST ,Calculates CRC32 according to start address and end address in CRC_ADDR register" "Not calculated,Calculated" bitfld.long 0x0C 10. " RELOAD_SHADOWS ,Forces re-loading all the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x0C 9. " ERROR ,Set by the controller when an access to a locked region (Otp or shadow register) is requested" "No error,Error" rbitfld.long 0x0C 8. " BUSY ,OTP controller status bit" "Not busy,Busy" bitfld.long 0x0C 0.--3. " ADDR ,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "TIMING,OTP Controller Timing Register" hexmask.long.byte 0x10 12.--19. 1. " FSOURCE ,This count value specifies FSOURCE to PROG setup / hold time" hexmask.long.word 0x10 0.--11. 1. " PROG ,This count value specifies the strobe period in one time write" group.long 0x20++0x03 line.long 0x00 "DATA0,OTP Controller Write Data Register" group.long 0x30++0x03 line.long 0x00 "DATA1,OTP Controller Write Data Register" group.long 0x40++0x03 line.long 0x00 "DATA2,OTP Controller Write Data Register" group.long 0x50++0x03 line.long 0x00 "DATA3,OTP Controller Write Data Register" group.long 0x60++0x03 line.long 0x00 "READ_CTRL,OTP Controller Write Data Register" bitfld.long 0x00 0. " READ_FUSE ,Used to initiate a read to OTP" "Not initiated,Initiated" group.long 0x70++0x03 line.long 0x00 "READ_FUSE_DATA0,OTP Controller Read Data Register" group.long 0x80++0x03 line.long 0x00 "READ_FUSE_DATA1,OTP Controller Read Data Register" group.long 0x90++0x03 line.long 0x00 "READ_FUSE_DATA2,OTP Controller Read Data Register" group.long 0xA0++0x03 line.long 0x00 "READ_FUSE_DATA3,OTP Controller Read Data Register" group.long 0xB0++0x03 line.long 0x00 "SW_STICKY,Sticky Bit Register" bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Shadow register write and OTP write lock for FIELD_RETURN region" "Unlocked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,Shadow register write and OTP write lock for SRK_REVOKE region" "Unlocked,Locked" group.long 0xC0++0x13 line.long 0x00 "SCS,Software Controllable Signals Register" bitfld.long 0x00 31. " LOCK ,When set all of the bits in this register are locked and cannot be changed during SW programming" "Unlocked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,Unallocated read / write bits of implementation for specific software use" bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" line.long 0x04 "SCS_SET,Software Controllable Signals Set Register" bitfld.long 0x04 31. " LOCK ,When set all of the bits in this register are locked and cannot be changed during SW programming" "Unlocked,Locked" hexmask.long 0x04 1.--30. 1. " SPARE ,Unallocated read / write bits of implementation for specific software use" bitfld.long 0x04 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" line.long 0x08 "SCS_CLR,Software Controllable Signals Clear Register" bitfld.long 0x08 31. " LOCK ,When set all of the bits in this register are locked and cannot be changed during SW programming" "Unlocked,Locked" hexmask.long 0x08 1.--30. 1. " SPARE ,Unallocated read / write bits of implementation for specific software use" bitfld.long 0x08 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" line.long 0x0C "SCS_TOG,Software Controllable Signals Toggle Register" bitfld.long 0x0C 31. " LOCK ,When set all of the bits in this register are locked and cannot be changed during SW programming" "Unlocked,Locked" hexmask.long 0x0C 1.--30. 1. " SPARE ,Unallocated read / write bits of implementation for specific software use" bitfld.long 0x0C 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" line.long 0x10 "CRC_ADDR,OTP Controller CRC Test Address Register" bitfld.long 0x10 16.--17. " CRC_ADDR ,Address of 32-bit CRC result is for comparing" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. " DATA_END_ADDR ,End address of fuse word location is for CRC calculation" hexmask.long.byte 0x10 0.--7. 1. " DATA_START_ADDR ,Start address of fuse word location is for CRC calculation" group.long 0xE0++0x03 line.long 0x00 "CRC_VALUE,OTP Controller CRC Value Register" rgroup.long 0xF0++0x03 line.long 0x00 "VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only values reflect the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only values reflect the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only values reflect the stepping of the RTL version" textline " " rgroup.long 0x400++0x03 line.long 0x00 "LOCK,Value Of OTP Bank0 Word0 (Lock Controls)" bitfld.long 0x00 30.--31. " CRC_GP2 ,Status of shadow register write and read, OTP write and read lock for CRC_GP2 region" "Full access,Writing blocked,Both blocked,Both blocked" bitfld.long 0x00 28.--29. " CRC_GP1 ,Status of shadow register write and read, OTP write and read lock for CRC_GP1 region" "Full access,Writing blocked,Both blocked,Both blocked" bitfld.long 0x00 22.--23. " GP2 ,Status of shadow register and OTP write lock for GP2 region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" textline " " bitfld.long 0x00 20.--21. " GP1 ,Status of shadow register and OTP write lock for GP1 region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" bitfld.long 0x00 17. " ROM_PATCH ,Status of shadow register and OTP write lock for ROM_PATCH region" "Not blocked,Blocked" bitfld.long 0x00 16. " MAU_KEY ,Status of shadow register read and write, OTP read and write lock for MANUFACTURE_KEY region" "Not blocked,Blocked" textline " " bitfld.long 0x00 14.--15. " MAC_ADDR ,Status of shadow register and OTP write lock for MAC_ADDR region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" bitfld.long 0x00 12.--13. " USB_ID ,Status of shadow register and OTP write lock for USB_ID region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" bitfld.long 0x00 10. " SJC_RESP ,Status of shadow register read and write, OTP read and write lock for SJC_RESP region" "Not blocked,Blocked" textline " " bitfld.long 0x00 9. " SRK ,Status of shadow register and OTP write lock for SRK region" "Not blocked,Blocked" bitfld.long 0x00 8. " OTPMK ,Status of shadow register read and write, OTP read and write lock for OTPMK region" "Not blocked,Blocked" bitfld.long 0x00 6.--7. " ANALOG ,Status of shadow register and OTP write lock for analog region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" textline " " bitfld.long 0x00 4.--5. " MEM_TRIM ,Status of shadow register and OTP write lock for MEM_TRIM region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" bitfld.long 0x00 2.--3. " BOOT_CFG ,Status of shadow register and OTP write lock for BOOT_CFG region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" bitfld.long 0x00 0.--1. " TESTER ,Status of shadow register and OTP write lock for tester region" "Full access,Otp's writing blocked,Shadow register's writing blocked,Both blocked" if (((per.l(ad:0x30350000+0x400))&0x03)==(0x02||0x03)) rgroup.long 0x410++0x03 line.long 0x00 "TESTER(0),Value Of OTP Bank0 Word1 (Tester Information)" rgroup.long 0x420++0x03 line.long 0x00 "TESTER(1),Value Of OTP Bank0 Word2 (Tester Information)" rgroup.long 0x430++0x03 line.long 0x00 "TESTER(2),Value Of OTP Bank0 Word3 (Tester Information)" rgroup.long 0x440++0x03 line.long 0x00 "TESTER(3),Value Of OTP Bank1 Word0 (Tester Information)" rgroup.long 0x450++0x03 line.long 0x00 "TESTER(4),Value Of OTP Bank1 Word1 (Tester Information)" rgroup.long 0x460++0x03 line.long 0x00 "TESTER(5),Value Of OTP Bank1 Word2 (Tester Information)" else group.long 0x410++0x03 line.long 0x00 "TESTER(0),Value Of OTP Bank0 Word1 (Tester Information)" group.long 0x420++0x03 line.long 0x00 "TESTER(1),Value Of OTP Bank0 Word2 (Tester Information)" group.long 0x430++0x03 line.long 0x00 "TESTER(2),Value Of OTP Bank0 Word3 (Tester Information)" group.long 0x440++0x03 line.long 0x00 "TESTER(3),Value Of OTP Bank1 Word0 (Tester Information)" group.long 0x450++0x03 line.long 0x00 "TESTER(4),Value Of OTP Bank1 Word1 (Tester Information)" group.long 0x460++0x03 line.long 0x00 "TESTER(5),Value Of OTP Bank1 Word2 (Tester Information)" endif if (((per.l(ad:0x30350000+0x400))&0x0C)==(0x08||0x0C)) rgroup.long 0x470++0x03 line.long 0x00 "BOOT_CFG0,Value Of OTP Bank1 Word3 (Boot Configuration Information)" rgroup.long 0x480++0x03 line.long 0x00 "BOOT_CFG1,Value Of OTP Bank2 Word0 (Boot Configuration Information)" rgroup.long 0x490++0x03 line.long 0x00 "BOOT_CFG2,Value Of OTP Bank2 Word1 (Boot Configuration Information)" rgroup.long 0x4A0++0x03 line.long 0x00 "BOOT_CFG3,Value Of OTP Bank2 Word2 (Boot Configuration Information)" rgroup.long 0x4B0++0x03 line.long 0x00 "BOOT_CFG4,Value Of OTP Bank2 Word3 (Boot Configuration Information)" else group.long 0x470++0x03 line.long 0x00 "BOOT_CFG0,Value Of OTP Bank1 Word3 (Boot Configuration Information)" group.long 0x480++0x03 line.long 0x00 "BOOT_CFG1,Value Of OTP Bank2 Word0 (Boot Configuration Information)" group.long 0x490++0x03 line.long 0x00 "BOOT_CFG2,Value Of OTP Bank2 Word1 (Boot Configuration Information)" group.long 0x4A0++0x03 line.long 0x00 "BOOT_CFG3,Value Of OTP Bank2 Word2 (Boot Configuration Information)" group.long 0x4B0++0x03 line.long 0x00 "BOOT_CFG4,Value Of OTP Bank2 Word3 (Boot Configuration Information)" endif if (((per.l(ad:0x30350000+0x400))&0x30)==(0x20||0x30)) rgroup.long 0x4C0++0x03 line.long 0x00 "MEM_TRIM0,Value Of OTP Bank3 Word0 (Memory Related Information)" rgroup.long 0x4D0++0x03 line.long 0x00 "MEM_TRIM1,Value Of OTP Bank3 Word1 (Memory Related Information)" else group.long 0x4C0++0x03 line.long 0x00 "MEM_TRIM0,Value Of OTP Bank3 Word0 (Memory Related Information)" group.long 0x4D0++0x03 line.long 0x00 "MEM_TRIM1,Value Of OTP Bank3 Word1 (Memory Related Information)" endif if (((per.l(ad:0x30350000+0x400))&0xC0)==(0x80||0xC0)) rgroup.long 0x4E0++0x03 line.long 0x00 "ANA0,Value Of OTP Bank3 Word2 (Analog Information)" rgroup.long 0x4F0++0x03 line.long 0x00 "ANA1,Value Of OTP Bank3 Word3 (Analog Information)" else group.long 0x4E0++0x03 line.long 0x00 "ANA0,Value Of OTP Bank3 Word2 (Analog Information)" group.long 0x4F0++0x03 line.long 0x00 "ANA1,Value Of OTP Bank3 Word3 (Analog Information)" endif if ((per.l(ad:0x30350000+0x400)&0x100)==0x00) group.long 0x500++0x03 line.long 0x00 "OTPMK0,Shadow Register For OTP Bank4 Word0 (Otpmk Key)" group.long 0x510++0x03 line.long 0x00 "OTPMK1,Shadow Register For OTP Bank4 Word1 (Otpmk Key)" group.long 0x520++0x03 line.long 0x00 "OTPMK2,Shadow Register For OTP Bank4 Word2 (Otpmk Key)" group.long 0x530++0x03 line.long 0x00 "OTPMK3,Shadow Register For OTP Bank4 Word3 (Otpmk Key)" group.long 0x540++0x03 line.long 0x00 "OTPMK4,Shadow Register For OTP Bank5 Word0 (Otpmk Key)" group.long 0x550++0x03 line.long 0x00 "OTPMK5,Shadow Register For OTP Bank5 Word1 (Otpmk Key)" group.long 0x560++0x03 line.long 0x00 "OTPMK6,Shadow Register For OTP Bank5 Word2 (Otpmk Key)" group.long 0x570++0x03 line.long 0x00 "OTPMK7,Shadow Register For OTP Bank5 Word3 (Otpmk Key)" else hgroup.long 0x500++0x03 hide.long 0x00 "OTPMK0,Shadow Register For OTP Bank4 Word0 (Otpmk Key)" hgroup.long 0x510++0x03 hide.long 0x00 "OTPMK1,Shadow Register For OTP Bank4 Word1 (Otpmk Key)" hgroup.long 0x520++0x03 hide.long 0x00 "OTPMK2,Shadow Register For OTP Bank4 Word2 (Otpmk Key)" hgroup.long 0x530++0x03 hide.long 0x00 "OTPMK3,Shadow Register For OTP Bank4 Word3 (Otpmk Key)" hgroup.long 0x540++0x03 hide.long 0x00 "OTPMK4,Shadow Register For OTP Bank5 Word0 (Otpmk Key)" hgroup.long 0x550++0x03 hide.long 0x00 "OTPMK5,Shadow Register For OTP Bank5 Word1 (Otpmk Key)" hgroup.long 0x560++0x03 hide.long 0x00 "OTPMK6,Shadow Register For OTP Bank5 Word2 (Otpmk Key)" hgroup.long 0x570++0x03 hide.long 0x00 "OTPMK7,Shadow Register For OTP Bank5 Word3 (Otpmk Key)" endif if ((per.l(ad:0x30350000+0x400)&0x200)==0x200) rgroup.long 0x580++0x03 line.long 0x00 "SRK0,Shadow Register For OTP Bank6 Word0 (Srk Hash)" rgroup.long 0x590++0x03 line.long 0x00 "SRK1,Shadow Register For OTP Bank6 Word1 (Srk Hash)" rgroup.long 0x5A0++0x03 line.long 0x00 "SRK2,Shadow Register For OTP Bank6 Word2 (Srk Hash)" rgroup.long 0x5B0++0x03 line.long 0x00 "SRK3,Shadow Register For OTP Bank6 Word3 (Srk Hash)" rgroup.long 0x5C0++0x03 line.long 0x00 "SRK4,Shadow Register For OTP Bank7 Word0 (Srk Hash)" rgroup.long 0x5D0++0x03 line.long 0x00 "SRK5,Shadow Register For OTP Bank7 Word1 (Srk Hash)" rgroup.long 0x5E0++0x03 line.long 0x00 "SRK6,Shadow Register For OTP Bank7 Word2 (Srk Hash)" rgroup.long 0x5F0++0x03 line.long 0x00 "SRK7,Shadow Register For OTP Bank7 Word3 (Srk Hash)" else group.long 0x580++0x03 line.long 0x00 "SRK0,Shadow Register For OTP Bank6 Word0 (Srk Hash)" group.long 0x590++0x03 line.long 0x00 "SRK1,Shadow Register For OTP Bank6 Word1 (Srk Hash)" group.long 0x5A0++0x03 line.long 0x00 "SRK2,Shadow Register For OTP Bank6 Word2 (Srk Hash)" group.long 0x5B0++0x03 line.long 0x00 "SRK3,Shadow Register For OTP Bank6 Word3 (Srk Hash)" group.long 0x5C0++0x03 line.long 0x00 "SRK4,Shadow Register For OTP Bank7 Word0 (Srk Hash)" group.long 0x5D0++0x03 line.long 0x00 "SRK5,Shadow Register For OTP Bank7 Word1 (Srk Hash)" group.long 0x5E0++0x03 line.long 0x00 "SRK6,Shadow Register For OTP Bank7 Word2 (Srk Hash)" group.long 0x5F0++0x03 line.long 0x00 "SRK7,Shadow Register For OTP Bank7 Word3 (Srk Hash)" endif if ((per.l(ad:0x30350000+0x400)&0x400)==0x00) group.long 0x600++0x03 line.long 0x00 "SJC_RESP0,Value Of OTP Bank8 Word0 (Secure JTAG Response Field)" group.long 0x610++0x03 line.long 0x00 "SJC_RESP1,Value Of OTP Bank8 Word1 (Secure JTAG Response Field)" else hgroup.long 0x600++0x03 hide.long 0x00 "SJC_RESP0,Value Of OTP Bank8 Word0 (Secure JTAG Response Field)" hgroup.long 0x610++0x03 hide.long 0x00 "SJC_RESP1,Value Of OTP Bank8 Word1 (Secure JTAG Response Field)" endif group.long 0x620++0x03 line.long 0x00 "USB_ID,Value Of OTP Bank8 Word2 (Usb ID Info)" group.long 0x630++0x03 line.long 0x00 "FIELD_RETURN,Value Of OTP Bank8 Word3 (Field Return)" group.long 0x640++0x03 line.long 0x00 "MAC_ADDR0,Value Of OTP Bank9 Word0 (Mac Address)" group.long 0x650++0x03 line.long 0x00 "MAC_ADDR1,Value Of OTP Bank9 Word1 (Mac Address)" group.long 0x660++0x03 line.long 0x00 "MAC_ADDR2,Value Of OTP Bank9 Word2 (Mac Address)" group.long 0x670++0x03 line.long 0x00 "SRK_REVOKE,Value Of OTP Bank9 Word3 (Srk Revoke)" if ((per.l(ad:0x30350000+0x400)&0x10000)==0x00) group.long 0x680++0x03 line.long 0x00 "MAU_KEY0,Shadow Register For OTP Bank10 Word0 (Mau Key)" group.long 0x690++0x03 line.long 0x00 "MAU_KEY1,Shadow Register For OTP Bank10 Word1 (Mau Key)" group.long 0x6A0++0x03 line.long 0x00 "MAU_KEY2,Shadow Register For OTP Bank10 Word2 (Mau Key)" group.long 0x6B0++0x03 line.long 0x00 "MAU_KEY3,Shadow Register For OTP Bank10 Word3 (Mau Key)" group.long 0x6C0++0x03 line.long 0x00 "MAU_KEY4,Shadow Register For OTP Bank11 Word0 (Mau Key)" group.long 0x6D0++0x03 line.long 0x00 "MAU_KEY5,Shadow Register For OTP Bank11 Word1 (Mau Key)" group.long 0x6E0++0x03 line.long 0x00 "MAU_KEY6,Shadow Register For OTP Bank11 Word2 (Mau Key)" group.long 0x6F0++0x03 line.long 0x00 "MAU_KEY7,Shadow Register For OTP Bank11 Word3 (Mau Key)" else hgroup.long 0x680++0x03 hide.long 0x00 "MAU_KEY0,Shadow Register For OTP Bank10 Word0 (Mau Key)" hgroup.long 0x690++0x03 hide.long 0x00 "MAU_KEY1,Shadow Register For OTP Bank10 Word1 (Mau Key)" hgroup.long 0x6A0++0x03 hide.long 0x00 "MAU_KEY2,Shadow Register For OTP Bank10 Word2 (Mau Key)" hgroup.long 0x6B0++0x03 hide.long 0x00 "MAU_KEY3,Shadow Register For OTP Bank10 Word3 (Mau Key)" hgroup.long 0x6C0++0x03 hide.long 0x00 "MAU_KEY4,Shadow Register For OTP Bank11 Word0 (Mau Key)" hgroup.long 0x6D0++0x03 hide.long 0x00 "MAU_KEY5,Shadow Register For OTP Bank11 Word1 (Mau Key)" hgroup.long 0x6E0++0x03 hide.long 0x00 "MAU_KEY6,Shadow Register For OTP Bank11 Word2 (Mau Key)" hgroup.long 0x6F0++0x03 hide.long 0x00 "MAU_KEY7,Shadow Register For OTP Bank11 Word3 (Mau Key)" endif group.long 0x780++0x03 line.long 0x00 "GP10,Value Of OTP Bank14 Word0" group.long 0x790++0x03 line.long 0x00 "GP11,Value Of OTP Bank14 Word1" group.long 0x7A0++0x03 line.long 0x00 "GP20,Value Of OTP Bank14 Word2" group.long 0x7B0++0x03 line.long 0x00 "GP21,Value Of OTP Bank14 Word3" group.long 0x7C0++0x03 line.long 0x00 "CRC_GP10,Value Of OTP Bank15 Word0 (Crc Key)" group.long 0x7D0++0x03 line.long 0x00 "CRC_GP11,Value Of OTP Bank15 Word1 (Crc Key)" group.long 0x7E0++0x03 line.long 0x00 "CRC_GP20,Value Of OTP Bank15 Word2 (Crc Key)" group.long 0x7F0++0x03 line.long 0x00 "CRC_GP21,Value Of OTP Bank15 Word3 (Crc Key)" width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x30280000 width 13. group.word 0x0++0x03 line.word 0x00 "WDOG1_WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "No,Yes" bitfld.word 0x00 6. " SRE ,Software reset extension" "Normal reset,Extension reset" bitfld.word 0x00 5. " WDA ,WDOG_B assertion" "Asserted,Not asserted" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" textline " " bitfld.word 0x00 3. " WDT ,WDOG_B Time-out assertion" "No effect,Asserted" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Disabled,Enabled" line.word 0x02 "WDOG1_WSR,Watchdog Service Register" rgroup.word (0x0+0x04)++0x01 line.word 0x00 "WDOG1_WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Indicates whether the reset is the result of a power on reset" "No,Yes" bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG timeout" "No,Yes" bitfld.word 0x00 0. " SFTW ,Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit" "No,Yes" group.word (0x0+0x06)++0x03 line.word 0x00 "WDOG1_WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count Time-out" line.word 0x02 "WDOG1_WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable" "Disabled,Enabled" group.word 0x10000++0x03 line.word 0x00 "WDOG2_WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "No,Yes" bitfld.word 0x00 6. " SRE ,Software reset extension" "Normal reset,Extension reset" bitfld.word 0x00 5. " WDA ,WDOG_B assertion" "Asserted,Not asserted" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" textline " " bitfld.word 0x00 3. " WDT ,WDOG_B Time-out assertion" "No effect,Asserted" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Disabled,Enabled" line.word 0x02 "WDOG2_WSR,Watchdog Service Register" rgroup.word (0x10000+0x04)++0x01 line.word 0x00 "WDOG2_WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Indicates whether the reset is the result of a power on reset" "No,Yes" bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG timeout" "No,Yes" bitfld.word 0x00 0. " SFTW ,Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit" "No,Yes" group.word (0x10000+0x06)++0x03 line.word 0x00 "WDOG2_WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count Time-out" line.word 0x02 "WDOG2_WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable" "Disabled,Enabled" group.word 0x20000++0x03 line.word 0x00 "WDOG3_WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "No,Yes" bitfld.word 0x00 6. " SRE ,Software reset extension" "Normal reset,Extension reset" bitfld.word 0x00 5. " WDA ,WDOG_B assertion" "Asserted,Not asserted" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" textline " " bitfld.word 0x00 3. " WDT ,WDOG_B Time-out assertion" "No effect,Asserted" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Disabled,Enabled" line.word 0x02 "WDOG3_WSR,Watchdog Service Register" rgroup.word (0x20000+0x04)++0x01 line.word 0x00 "WDOG3_WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Indicates whether the reset is the result of a power on reset" "No,Yes" bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG timeout" "No,Yes" bitfld.word 0x00 0. " SFTW ,Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit" "No,Yes" group.word (0x20000+0x06)++0x03 line.word 0x00 "WDOG3_WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count Time-out" line.word 0x02 "WDOG3_WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable" "Disabled,Enabled" group.word 0x30000++0x03 line.word 0x00 "WDOG4_WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out field" bitfld.word 0x00 7. " WDW ,Watchdog disable for wait" "No,Yes" bitfld.word 0x00 6. " SRE ,Software reset extension" "Normal reset,Extension reset" bitfld.word 0x00 5. " WDA ,WDOG_B assertion" "Asserted,Not asserted" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" textline " " bitfld.word 0x00 3. " WDT ,WDOG_B Time-out assertion" "No effect,Asserted" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Disabled,Enabled" line.word 0x02 "WDOG4_WSR,Watchdog Service Register" rgroup.word (0x30000+0x04)++0x01 line.word 0x00 "WDOG4_WRSR,Watchdog Reset Status Register" bitfld.word 0x00 4. " POR ,Indicates whether the reset is the result of a power on reset" "No,Yes" bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG timeout" "No,Yes" bitfld.word 0x00 0. " SFTW ,Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit" "No,Yes" group.word (0x30000+0x06)++0x03 line.word 0x00 "WDOG4_WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count Time-out" line.word 0x02 "WDOG4_WMCR,Watchdog Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power down enable" "Disabled,Enabled" width 0x0B tree.end tree "SDMA (Smart Direct Memory Access Controller)" base ad:0x30BD0000 width 15. group.long 0x00++0x13 line.long 0x00 "MC0PTR,ARM Platform Channel 0 Pointer Register" line.long 0x04 "INTR,Channel Interrupts Register" eventfld.long 0x04 31. " HI[31] ,Channel interrupt 31" "No interrupt,Interrupt" eventfld.long 0x04 30. " [30] ,Channel interrupt 30" "No interrupt,Interrupt" eventfld.long 0x04 29. " [29] ,Channel interrupt 29" "No interrupt,Interrupt" eventfld.long 0x04 28. " [28] ,Channel interrupt 28" "No interrupt,Interrupt" textline " " eventfld.long 0x04 27. " [27] ,Channel interrupt 27" "No interrupt,Interrupt" eventfld.long 0x04 26. " [26] ,Channel interrupt 26" "No interrupt,Interrupt" eventfld.long 0x04 25. " [25] ,Channel interrupt 25" "No interrupt,Interrupt" eventfld.long 0x04 24. " [24] ,Channel interrupt 24" "No interrupt,Interrupt" textline " " eventfld.long 0x04 23. " [23] ,Channel interrupt 23" "No interrupt,Interrupt" eventfld.long 0x04 22. " [22] ,Channel interrupt 22" "No interrupt,Interrupt" eventfld.long 0x04 21. " [21] ,Channel interrupt 21" "No interrupt,Interrupt" eventfld.long 0x04 20. " [20] ,Channel interrupt 20" "No interrupt,Interrupt" textline " " eventfld.long 0x04 19. " [19] ,Channel interrupt 19" "No interrupt,Interrupt" eventfld.long 0x04 18. " [18] ,Channel interrupt 18" "No interrupt,Interrupt" eventfld.long 0x04 17. " [17] ,Channel interrupt 17" "No interrupt,Interrupt" eventfld.long 0x04 16. " [16] ,Channel interrupt 16" "No interrupt,Interrupt" textline " " eventfld.long 0x04 15. " [15] ,Channel interrupt 15" "No interrupt,Interrupt" eventfld.long 0x04 14. " [14] ,Channel interrupt 14" "No interrupt,Interrupt" eventfld.long 0x04 13. " [13] ,Channel interrupt 13" "No interrupt,Interrupt" eventfld.long 0x04 12. " [12] ,Channel interrupt 12" "No interrupt,Interrupt" textline " " eventfld.long 0x04 11. " [11] ,Channel interrupt 11" "No interrupt,Interrupt" eventfld.long 0x04 10. " [10] ,Channel interrupt 10" "No interrupt,Interrupt" eventfld.long 0x04 9. " [9] ,Channel interrupt 9" "No interrupt,Interrupt" eventfld.long 0x04 8. " [8] ,Channel interrupt 8" "No interrupt,Interrupt" textline " " eventfld.long 0x04 7. " [7] ,Channel interrupt 7" "No interrupt,Interrupt" eventfld.long 0x04 6. " [6] ,Channel interrupt 6" "No interrupt,Interrupt" eventfld.long 0x04 5. " [5] ,Channel interrupt 5" "No interrupt,Interrupt" eventfld.long 0x04 4. " [4] ,Channel interrupt 4" "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " [3] ,Channel interrupt 3" "No interrupt,Interrupt" eventfld.long 0x04 2. " [2] ,Channel interrupt 2" "No interrupt,Interrupt" eventfld.long 0x04 1. " [1] ,Channel interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 0. " [0] ,Channel interrupt 0" "No interrupt,Interrupt" line.long 0x08 "STOP_STAT,Channel Stop/channel Status Register" eventfld.long 0x08 31. " HE[31] ,Channel 31 stop/status" "No access,Access" eventfld.long 0x08 30. " [30] ,Channel 30 stop/status" "No access,Access" eventfld.long 0x08 29. " [29] ,Channel 29 stop/status" "No access,Access" eventfld.long 0x08 28. " [28] ,Channel 28 stop/status" "No access,Access" textline " " eventfld.long 0x08 27. " [27] ,Channel 27 stop/status" "No access,Access" eventfld.long 0x08 26. " [26] ,Channel 26 stop/status" "No access,Access" eventfld.long 0x08 25. " [25] ,Channel 25 stop/status" "No access,Access" eventfld.long 0x08 24. " [24] ,Channel 24 stop/status" "No access,Access" textline " " eventfld.long 0x08 23. " [23] ,Channel 23 stop/status" "No access,Access" eventfld.long 0x08 22. " [22] ,Channel 22 stop/status" "No access,Access" eventfld.long 0x08 21. " [21] ,Channel 21 stop/status" "No access,Access" eventfld.long 0x08 20. " [20] ,Channel 20 stop/status" "No access,Access" textline " " eventfld.long 0x08 19. " [19] ,Channel 19 stop/status" "No access,Access" eventfld.long 0x08 18. " [18] ,Channel 18 stop/status" "No access,Access" eventfld.long 0x08 17. " [17] ,Channel 17 stop/status" "No access,Access" eventfld.long 0x08 16. " [16] ,Channel 16 stop/status" "No access,Access" textline " " eventfld.long 0x08 15. " [15] ,Channel 15 stop/status" "No access,Access" eventfld.long 0x08 14. " [14] ,Channel 14 stop/status" "No access,Access" eventfld.long 0x08 13. " [13] ,Channel 13 stop/status" "No access,Access" eventfld.long 0x08 12. " [12] ,Channel 12 stop/status" "No access,Access" textline " " eventfld.long 0x08 11. " [11] ,Channel 11 stop/status" "No access,Access" eventfld.long 0x08 10. " [10] ,Channel 10 stop/status" "No access,Access" eventfld.long 0x08 9. " [9] ,Channel 9 stop/status" "No access,Access" eventfld.long 0x08 8. " [8] ,Channel 8 stop/status" "No access,Access" textline " " eventfld.long 0x08 7. " [7] ,Channel 7 stop/status" "No access,Access" eventfld.long 0x08 6. " [6] ,Channel 6 stop/status" "No access,Access" eventfld.long 0x08 5. " [5] ,Channel 5 stop/status" "No access,Access" eventfld.long 0x08 4. " [4] ,Channel 4 stop/status" "No access,Access" textline " " eventfld.long 0x08 3. " [3] ,Channel 3 stop/status" "No access,Access" eventfld.long 0x08 2. " [2] ,Channel 2 stop/status" "No access,Access" eventfld.long 0x08 1. " [1] ,Channel 1 stop/status" "No access,Access" eventfld.long 0x08 0. " [0] ,Channel 0 stop/status" "No access,Access" line.long 0x0C "HSTART,Channel Start Register" eventfld.long 0x0C 31. " HSTART[31] ,Channel 31 enable" "Disabled,Enabled" eventfld.long 0x0C 30. " [30] ,Channel 30 enable" "Disabled,Enabled" eventfld.long 0x0C 29. " [29] ,Channel 29 enable" "Disabled,Enabled" eventfld.long 0x0C 28. " [28] ,Channel 28 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 27. " [27] ,Channel 27 enable" "Disabled,Enabled" eventfld.long 0x0C 26. " [26] ,Channel 26 enable" "Disabled,Enabled" eventfld.long 0x0C 25. " [25] ,Channel 25 enable" "Disabled,Enabled" eventfld.long 0x0C 24. " [24] ,Channel 24 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 23. " [23] ,Channel 23 enable" "Disabled,Enabled" eventfld.long 0x0C 22. " [22] ,Channel 22 enable" "Disabled,Enabled" eventfld.long 0x0C 21. " [21] ,Channel 21 enable" "Disabled,Enabled" eventfld.long 0x0C 20. " [20] ,Channel 20 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 19. " [19] ,Channel 19 enable" "Disabled,Enabled" eventfld.long 0x0C 18. " [18] ,Channel 18 enable" "Disabled,Enabled" eventfld.long 0x0C 17. " [17] ,Channel 17 enable" "Disabled,Enabled" eventfld.long 0x0C 16. " [16] ,Channel 16 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 15. " [15] ,Channel 15 enable" "Disabled,Enabled" eventfld.long 0x0C 14. " [14] ,Channel 14 enable" "Disabled,Enabled" eventfld.long 0x0C 13. " [13] ,Channel 13 enable" "Disabled,Enabled" eventfld.long 0x0C 12. " [12] ,Channel 12 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 11. " [11] ,Channel 11 enable" "Disabled,Enabled" eventfld.long 0x0C 10. " [10] ,Channel 10 enable" "Disabled,Enabled" eventfld.long 0x0C 9. " [9] ,Channel 9 enable" "Disabled,Enabled" eventfld.long 0x0C 8. " [8] ,Channel 8 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 7. " [7] ,Channel 7 enable" "Disabled,Enabled" eventfld.long 0x0C 6. " [6] ,Channel 6 enable" "Disabled,Enabled" eventfld.long 0x0C 5. " [5] ,Channel 5 enable" "Disabled,Enabled" eventfld.long 0x0C 4. " [4] ,Channel 4 enable" "Disabled,Enabled" textline " " eventfld.long 0x0C 3. " [3] ,Channel 3 enable" "Disabled,Enabled" eventfld.long 0x0C 2. " [2] ,Channel 2 enable" "Disabled,Enabled" eventfld.long 0x0C 1. " [1] ,Channel 1 enable" "Disabled,Enabled" eventfld.long 0x0C 0. " [0] ,Channel 0 enable" "Disabled,Enabled" line.long 0x10 "EVTOVR,Channel Event Override Register" bitfld.long 0x10 31. " EO[31] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 30. " [30] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 29. " [29] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 28. " [28] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 27. " [27] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 26. " [26] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 25. " [25] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 24. " [24] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 23. " [23] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 22. " [22] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 21. " [21] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 20. " [20] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 19. " [19] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 18. " [18] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 17. " [17] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 16. " [16] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 15. " [15] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 14. " [14] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 13. " [13] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 12. " [12] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 11. " [11] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 10. " [10] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 9. " [9] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 8. " [8] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 7. " [7] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 6. " [6] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 5. " [5] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 4. " [4] ,DMA request ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x10 3. " [3] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 2. " [2] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 1. " [1] ,DMA request ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x10 0. " [0] ,DMA request ignored by SDMA" "Not ignored,Ignored" group.long 0x18++0x07 line.long 0x00 "HOSTOVR,Channel AP Override Register" bitfld.long 0x00 31. " HO[31] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 30. " [30] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 29. " [29] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 28. " [28] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 27. " [27] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 26. " [26] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 25. " [25] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 24. " [24] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 23. " [23] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 22. " [22] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 21. " [21] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 20. " [20] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 19. " [19] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 18. " [18] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 17. " [17] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 16. " [16] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 15. " [15] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 14. " [14] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 13. " [13] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 12. " [12] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 11. " [11] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 10. " [10] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 9. " [9] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 8. " [8] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 7. " [7] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 6. " [6] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 5. " [5] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 4. " [4] ,AP enable ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " [3] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 2. " [2] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 1. " [1] ,AP enable ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 0. " [0] ,AP enable ignored by SDMA" "Not ignored,Ignored" line.long 0x04 "EVTPEND,Channel Event Pending Register" eventfld.long 0x04 31. " EP[31] ,Channel 31 event pending" "Not pending,Pending" eventfld.long 0x04 30. " [30] ,Channel 30 event pending" "Not pending,Pending" eventfld.long 0x04 29. " [29] ,Channel 29 event pending" "Not pending,Pending" eventfld.long 0x04 28. " [28] ,Channel 28 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 27. " [27] ,Channel 27 event pending" "Not pending,Pending" eventfld.long 0x04 26. " [26] ,Channel 26 event pending" "Not pending,Pending" eventfld.long 0x04 25. " [25] ,Channel 25 event pending" "Not pending,Pending" eventfld.long 0x04 24. " [24] ,Channel 24 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 23. " [23] ,Channel 23 event pending" "Not pending,Pending" eventfld.long 0x04 22. " [22] ,Channel 22 event pending" "Not pending,Pending" eventfld.long 0x04 21. " [21] ,Channel 21 event pending" "Not pending,Pending" eventfld.long 0x04 20. " [20] ,Channel 20 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 19. " [19] ,Channel 19 event pending" "Not pending,Pending" eventfld.long 0x04 18. " [18] ,Channel 18 event pending" "Not pending,Pending" eventfld.long 0x04 17. " [17] ,Channel 17 event pending" "Not pending,Pending" eventfld.long 0x04 16. " [16] ,Channel 16 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 15. " [15] ,Channel 15 event pending" "Not pending,Pending" eventfld.long 0x04 14. " [14] ,Channel 14 event pending" "Not pending,Pending" eventfld.long 0x04 13. " [13] ,Channel 13 event pending" "Not pending,Pending" eventfld.long 0x04 12. " [12] ,Channel 12 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 11. " [11] ,Channel 11 event pending" "Not pending,Pending" eventfld.long 0x04 10. " [10] ,Channel 10 event pending" "Not pending,Pending" eventfld.long 0x04 9. " [9] ,Channel 9 event pending" "Not pending,Pending" eventfld.long 0x04 8. " [8] ,Channel 8 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 7. " [7] ,Channel 7 event pending" "Not pending,Pending" eventfld.long 0x04 6. " [6] ,Channel 6 event pending" "Not pending,Pending" eventfld.long 0x04 5. " [5] ,Channel 5 event pending" "Not pending,Pending" eventfld.long 0x04 4. " [4] ,Channel 4 event pending" "Not pending,Pending" textline " " eventfld.long 0x04 3. " [3] ,Channel 3 event pending" "Not pending,Pending" eventfld.long 0x04 2. " [2] ,Channel 2 event pending" "Not pending,Pending" eventfld.long 0x04 1. " [1] ,Channel 1 event pending" "Not pending,Pending" eventfld.long 0x04 0. " [0] ,Channel 0 event pending" "Not pending,Pending" rgroup.long 0x24++0x03 line.long 0x00 "RESET,Reset Register" bitfld.long 0x00 1. " RESCHED ,Forces the SDMA to reschedule as if a script had executed a done instruction" "Not forced,Forced" bitfld.long 0x00 0. " RESET ,Causes the SDMA to be held in a software reset" "No software reset,Software reset" hgroup.long 0x28++0x03 hide.long 0x00 "EVTERR,DMA Request Error Register" in group.long 0x2C++0x03 line.long 0x00 "INTRMASK,Channel ARM Platform Interrupt Mask Register" bitfld.long 0x00 31. " HIMASK[31] ,Interrupt generation mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Interrupt generation mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Interrupt generation mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Interrupt generation mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Interrupt generation mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Interrupt generation mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Interrupt generation mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Interrupt generation mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Interrupt generation mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Interrupt generation mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Interrupt generation mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Interrupt generation mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Interrupt generation mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Interrupt generation mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Interrupt generation mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Interrupt generation mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Interrupt generation mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Interrupt generation mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Interrupt generation mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Interrupt generation mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Interrupt generation mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Interrupt generation mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Interrupt generation mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Interrupt generation mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Interrupt generation mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Interrupt generation mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Interrupt generation mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Interrupt generation mask bit 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Interrupt generation mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Interrupt generation mask bit 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Interrupt generation mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Interrupt generation mask bit 0" "Not masked,Masked" rgroup.long 0x30++0x07 line.long 0x00 "PSW,Schedule Status" bitfld.long 0x00 13.--15. " NCP ,Gives the next pending channel priority" "No running channel,Active channel priority,?..." bitfld.long 0x00 8.--12. " NCR ,Indicates the number of the next scheduled pending channel with the highest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CCP ,Indicates the priority of the current active channel" "No running channel,Active channel priority,?..." bitfld.long 0x00 0.--3. " CCR ,The current channel register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVTERRDBG,DMA Request Error Register" bitfld.long 0x04 31. " CHNERR[31] ,Set when a DMA request that triggers channel 31 is received and the EP[31] bit is already set" "No error,Error" bitfld.long 0x04 30. " [30] ,Set when a DMA request that triggers channel 30 is received and the EP[30] bit is already set" "No error,Error" bitfld.long 0x04 29. " [29] ,Set when a DMA request that triggers channel 29 is received and the EP[29] bit is already set" "No error,Error" bitfld.long 0x04 28. " [28] ,Set when a DMA request that triggers channel 28 is received and the EP[28] bit is already set" "No error,Error" textline " " bitfld.long 0x04 27. " [27] ,Set when a DMA request that triggers channel 27 is received and the EP[27] bit is already set" "No error,Error" bitfld.long 0x04 26. " [26] ,Set when a DMA request that triggers channel 26 is received and the EP[26] bit is already set" "No error,Error" bitfld.long 0x04 25. " [25] ,Set when a DMA request that triggers channel 25 is received and the EP[25] bit is already set" "No error,Error" bitfld.long 0x04 24. " [24] ,Set when a DMA request that triggers channel 24 is received and the EP[24] bit is already set" "No error,Error" textline " " bitfld.long 0x04 23. " [23] ,Set when a DMA request that triggers channel 23 is received and the EP[23] bit is already set" "No error,Error" bitfld.long 0x04 22. " [22] ,Set when a DMA request that triggers channel 22 is received and the EP[22] bit is already set" "No error,Error" bitfld.long 0x04 21. " [21] ,Set when a DMA request that triggers channel 21 is received and the EP[21] bit is already set" "No error,Error" bitfld.long 0x04 20. " [20] ,Set when a DMA request that triggers channel 20 is received and the EP[20] bit is already set" "No error,Error" textline " " bitfld.long 0x04 19. " [19] ,Set when a DMA request that triggers channel 19 is received and the EP[19] bit is already set" "No error,Error" bitfld.long 0x04 18. " [18] ,Set when a DMA request that triggers channel 18 is received and the EP[18] bit is already set" "No error,Error" bitfld.long 0x04 17. " [17] ,Set when a DMA request that triggers channel 17 is received and the EP[17] bit is already set" "No error,Error" bitfld.long 0x04 16. " [16] ,Set when a DMA request that triggers channel 16 is received and the EP[16] bit is already set" "No error,Error" textline " " bitfld.long 0x04 15. " [15] ,Set when a DMA request that triggers channel 15 is received and the EP[15] bit is already set" "No error,Error" bitfld.long 0x04 14. " [14] ,Set when a DMA request that triggers channel 14 is received and the EP[14] bit is already set" "No error,Error" bitfld.long 0x04 13. " [13] ,Set when a DMA request that triggers channel 13 is received and the EP[13] bit is already set" "No error,Error" bitfld.long 0x04 12. " [12] ,Set when a DMA request that triggers channel 12 is received and the EP[12] bit is already set" "No error,Error" textline " " bitfld.long 0x04 11. " [11] ,Set when a DMA request that triggers channel 11 is received and the EP[11] bit is already set" "No error,Error" bitfld.long 0x04 10. " [10] ,Set when a DMA request that triggers channel 10 is received and the EP[10] bit is already set" "No error,Error" bitfld.long 0x04 9. " [9] ,Set when a DMA request that triggers channel 9 is received and the EP[9] bit is already set" "No error,Error" bitfld.long 0x04 8. " [8] ,Set when a DMA request that triggers channel 8 is received and the EP[8] bit is already set" "No error,Error" textline " " bitfld.long 0x04 7. " [7] ,Set when a DMA request that triggers channel 7 is received and the EP[7] bit is already set" "No error,Error" bitfld.long 0x04 6. " [6] ,Set when a DMA request that triggers channel 6 is received and the EP[6] bit is already set" "No error,Error" bitfld.long 0x04 5. " [5] ,Set when a DMA request that triggers channel 5 is received and the EP[5] bit is already set" "No error,Error" bitfld.long 0x04 4. " [4] ,Set when a DMA request that triggers channel 4 is received and the EP[4] bit is already set" "No error,Error" textline " " bitfld.long 0x04 3. " [3] ,Set when a DMA request that triggers channel 3 is received and the EP[3] bit is already set" "No error,Error" bitfld.long 0x04 2. " [2] ,Set when a DMA request that triggers channel 2 is received and the EP[2] bit is already set" "No error,Error" bitfld.long 0x04 1. " [1] ,Set when a DMA request that triggers channel 1 is received and the EP[1] bit is already set" "No error,Error" bitfld.long 0x04 0. " [0] ,Set when a DMA request that triggers channel 0 is received and the EP[0] bit is already set" "No error,Error" group.long 0x38++0x03 line.long 0x00 "CONFIG,Configuration Register" bitfld.long 0x00 11. " RTDOBS ,Indicates if Real-Time debug pins are used" "Disabled,Enabled" bitfld.long 0x00 4. " ACR ,Selects the clock ratio between ARM platform DMA interfaces and the internal SDMA core clock" "2x core freq,Core freq" bitfld.long 0x00 0.--1. " CSM ,Context switch mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic" if (((per.l(ad:0x30BD0000+0x3C))&0x01)==0x01) rgroup.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" else group.long 0x3C++0x07 line.long 0x00 "SDMA_LOCK,SDMA LOCK" bitfld.long 0x00 1. " SRESET_LOCK_CLR ,Determines if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "Not cleared,Cleared" bitfld.long 0x00 0. " LOCK ,Restricts access to update SDMA script memory through ROM channel zero scripts and through the once interface under ARM platform control" "Disengaged,Enabled" line.long 0x04 "ONCE_ENB,Once Enable" bitfld.long 0x04 0. " ENB ,Enables the ARM platform to access the ONCE_* as any other SDMA control register" "Disabled,Enabled" endif group.long 0x44++0x07 line.long 0x00 "ONCE_DATA,Once Data Register" line.long 0x04 "ONCE_INSTR,Once Instruction Register" hexmask.long.word 0x04 0.--15. 1. " INSTR ,Instruction register of the once JTAG controller" rgroup.long 0x4C++0x03 line.long 0x00 "ONCE_STAT,Once Status Register" bitfld.long 0x00 12.--15. " PST ,Processor status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore" bitfld.long 0x00 11. " RCV ,Write access to the real time buffer" "No write access,Write access" bitfld.long 0x00 10. " EDR ,SDMA has entered debug mode after an external debug request" "No,Yes" bitfld.long 0x00 9. " ODR ,SDMA has entered debug mode after a once debug request" "No,Yes" textline " " bitfld.long 0x00 8. " SWB ,SDMA has entered debug mode after a software breakpoint" "No,Yes" bitfld.long 0x00 7. " MST ,Once is controlled from the ARM platform peripheral interface" "JTAG,ARM" bitfld.long 0x00 0.--2. " ECDR ,Event cell debug request" "1 matched addra_cond,1 matched addrb_cond,1 matched data_cond,?..." group.long 0x50++0x03 line.long 0x00 "ONCE_CMD,Once Command Register" bitfld.long 0x00 0.--3. " CMD ,CMD" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,?..." if ((per.l(ad:0x30BD0000+0x3C)&0x01)==0x01) rgroup.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" else group.long 0x58++0x07 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 0x01 " ILLINSTADDR ,Illegal instruction trap address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch memory size" "24 words per context,32 words per context" hexmask.long.word 0x04 0.--13. 0x01 " CHN0ADDR ,Channel 0 boot address" endif rgroup.long 0x60++0x07 line.long 0x00 "EVT_MIRROR,DMA Requests Register" bitfld.long 0x00 31. " EVENTS[31] ,Reflects the DMA requests received by the SDMA for events 31" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Reflects the DMA requests received by the SDMA for events 30" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Reflects the DMA requests received by the SDMA for events 29" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Reflects the DMA requests received by the SDMA for events 28" "Not pending,Pending" textline " " bitfld.long 0x00 27. " [27] ,Reflects the DMA requests received by the SDMA for events 27" "Not pending,Pending" bitfld.long 0x00 26. " [26] ,Reflects the DMA requests received by the SDMA for events 26" "Not pending,Pending" bitfld.long 0x00 25. " [25] ,Reflects the DMA requests received by the SDMA for events 25" "Not pending,Pending" bitfld.long 0x00 24. " [24] ,Reflects the DMA requests received by the SDMA for events 24" "Not pending,Pending" textline " " bitfld.long 0x00 23. " [23] ,Reflects the DMA requests received by the SDMA for events 23" "Not pending,Pending" bitfld.long 0x00 22. " [22] ,Reflects the DMA requests received by the SDMA for events 22" "Not pending,Pending" bitfld.long 0x00 21. " [21] ,Reflects the DMA requests received by the SDMA for events 21" "Not pending,Pending" bitfld.long 0x00 20. " [20] ,Reflects the DMA requests received by the SDMA for events 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " [19] ,Reflects the DMA requests received by the SDMA for events 19" "Not pending,Pending" bitfld.long 0x00 18. " [18] ,Reflects the DMA requests received by the SDMA for events 18" "Not pending,Pending" bitfld.long 0x00 17. " [17] ,Reflects the DMA requests received by the SDMA for events 17" "Not pending,Pending" bitfld.long 0x00 16. " [16] ,Reflects the DMA requests received by the SDMA for events 16" "Not pending,Pending" textline " " bitfld.long 0x00 15. " [15] ,Reflects the DMA requests received by the SDMA for events 15" "Not pending,Pending" bitfld.long 0x00 14. " [14] ,Reflects the DMA requests received by the SDMA for events 14" "Not pending,Pending" bitfld.long 0x00 13. " [13] ,Reflects the DMA requests received by the SDMA for events 13" "Not pending,Pending" bitfld.long 0x00 12. " [12] ,Reflects the DMA requests received by the SDMA for events 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " [11] ,Reflects the DMA requests received by the SDMA for events 11" "Not pending,Pending" bitfld.long 0x00 10. " [10] ,Reflects the DMA requests received by the SDMA for events 10" "Not pending,Pending" bitfld.long 0x00 9. " [9] ,Reflects the DMA requests received by the SDMA for events 9" "Not pending,Pending" bitfld.long 0x00 8. " [8] ,Reflects the DMA requests received by the SDMA for events 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " [7] ,Reflects the DMA requests received by the SDMA for events 7" "Not pending,Pending" bitfld.long 0x00 6. " [6] ,Reflects the DMA requests received by the SDMA for events 6" "Not pending,Pending" bitfld.long 0x00 5. " [5] ,Reflects the DMA requests received by the SDMA for events 5" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Reflects the DMA requests received by the SDMA for events 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " [3] ,Reflects the DMA requests received by the SDMA for events 3" "Not pending,Pending" bitfld.long 0x00 2. " [2] ,Reflects the DMA requests received by the SDMA for events 2" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Reflects the DMA requests received by the SDMA for events 1" "Not pending,Pending" bitfld.long 0x00 0. " [0] ,Reflects the DMA requests received by the SDMA for events 0" "Not pending,Pending" line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register" bitfld.long 0x04 15. " EVENTS[47] ,Reflects the DMA requests received by the SDMA for events 47" "Not pending,Pending" bitfld.long 0x04 14. " [46] ,Reflects the DMA requests received by the SDMA for events 46" "Not pending,Pending" bitfld.long 0x04 13. " [45] ,Reflects the DMA requests received by the SDMA for events 45" "Not pending,Pending" bitfld.long 0x04 12. " [44] ,Reflects the DMA requests received by the SDMA for events 44" "Not pending,Pending" textline " " bitfld.long 0x04 11. " [43] ,Reflects the DMA requests received by the SDMA for events 43" "Not pending,Pending" bitfld.long 0x04 10. " [42] ,Reflects the DMA requests received by the SDMA for events 42" "Not pending,Pending" bitfld.long 0x04 9. " [41] ,Reflects the DMA requests received by the SDMA for events 41" "Not pending,Pending" bitfld.long 0x04 8. " [40] ,Reflects the DMA requests received by the SDMA for events 40" "Not pending,Pending" textline " " bitfld.long 0x04 7. " [39] ,Reflects the DMA requests received by the SDMA for events 39" "Not pending,Pending" bitfld.long 0x04 6. " [38] ,Reflects the DMA requests received by the SDMA for events 38" "Not pending,Pending" bitfld.long 0x04 5. " [37] ,Reflects the DMA requests received by the SDMA for events 37" "Not pending,Pending" bitfld.long 0x04 4. " [36] ,Reflects the DMA requests received by the SDMA for events 36" "Not pending,Pending" textline " " bitfld.long 0x04 3. " [35] ,Reflects the DMA requests received by the SDMA for events 35" "Not pending,Pending" bitfld.long 0x04 2. " [34] ,Reflects the DMA requests received by the SDMA for events 34" "Not pending,Pending" bitfld.long 0x04 1. " [33] ,Reflects the DMA requests received by the SDMA for events 33" "Not pending,Pending" bitfld.long 0x04 0. " [32] ,Reflects the DMA requests received by the SDMA for events 32" "Not pending,Pending" group.long 0x70++0x07 line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1" bitfld.long 0x00 30. " CNF3 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 24.--29. " NUM3 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " CNF2 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 16.--21. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 14. " CNF1 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 8.--13. " NUM2 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " CNF0 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x00 0.--5. " NUM0 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2" bitfld.long 0x04 30. " CNF7 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 24.--29. " NUM7 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 22. " CNF6 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 16.--21. " NUM6 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 14. " CNF5 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 8.--13. " NUM5 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6. " CNF4 ,It determines whether the event line pulse is generated by the reception of a DMA request or by the starting of a channel script execution" "Channel,DMA request" bitfld.long 0x04 0.--5. " NUM4 ,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 15. tree "Channel Priority Registers" group.long 0x100++0x03 line.long 0x00 "SDMA_CHNPRI0,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI0 ,Contains the priority of channel number 0 " ",1,2,3,4,5,6,7" group.long 0x104++0x03 line.long 0x00 "SDMA_CHNPRI1,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI1 ,Contains the priority of channel number 1 " ",1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "SDMA_CHNPRI2,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI2 ,Contains the priority of channel number 2 " ",1,2,3,4,5,6,7" group.long 0x10C++0x03 line.long 0x00 "SDMA_CHNPRI3,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI3 ,Contains the priority of channel number 3 " ",1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "SDMA_CHNPRI4,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI4 ,Contains the priority of channel number 4 " ",1,2,3,4,5,6,7" group.long 0x114++0x03 line.long 0x00 "SDMA_CHNPRI5,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI5 ,Contains the priority of channel number 5 " ",1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "SDMA_CHNPRI6,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI6 ,Contains the priority of channel number 6 " ",1,2,3,4,5,6,7" group.long 0x11C++0x03 line.long 0x00 "SDMA_CHNPRI7,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI7 ,Contains the priority of channel number 7 " ",1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "SDMA_CHNPRI8,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI8 ,Contains the priority of channel number 8 " ",1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "SDMA_CHNPRI9,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI9 ,Contains the priority of channel number 9 " ",1,2,3,4,5,6,7" group.long 0x128++0x03 line.long 0x00 "SDMA_CHNPRI10,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI10 ,Contains the priority of channel number 10" ",1,2,3,4,5,6,7" group.long 0x12C++0x03 line.long 0x00 "SDMA_CHNPRI11,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI11 ,Contains the priority of channel number 11" ",1,2,3,4,5,6,7" group.long 0x130++0x03 line.long 0x00 "SDMA_CHNPRI12,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI12 ,Contains the priority of channel number 12" ",1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "SDMA_CHNPRI13,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI13 ,Contains the priority of channel number 13" ",1,2,3,4,5,6,7" group.long 0x138++0x03 line.long 0x00 "SDMA_CHNPRI14,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI14 ,Contains the priority of channel number 14" ",1,2,3,4,5,6,7" group.long 0x13C++0x03 line.long 0x00 "SDMA_CHNPRI15,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI15 ,Contains the priority of channel number 15" ",1,2,3,4,5,6,7" group.long 0x140++0x03 line.long 0x00 "SDMA_CHNPRI16,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI16 ,Contains the priority of channel number 16" ",1,2,3,4,5,6,7" group.long 0x144++0x03 line.long 0x00 "SDMA_CHNPRI17,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI17 ,Contains the priority of channel number 17" ",1,2,3,4,5,6,7" group.long 0x148++0x03 line.long 0x00 "SDMA_CHNPRI18,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI18 ,Contains the priority of channel number 18" ",1,2,3,4,5,6,7" group.long 0x14C++0x03 line.long 0x00 "SDMA_CHNPRI19,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI19 ,Contains the priority of channel number 19" ",1,2,3,4,5,6,7" group.long 0x150++0x03 line.long 0x00 "SDMA_CHNPRI20,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI20 ,Contains the priority of channel number 20" ",1,2,3,4,5,6,7" group.long 0x154++0x03 line.long 0x00 "SDMA_CHNPRI21,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI21 ,Contains the priority of channel number 21" ",1,2,3,4,5,6,7" group.long 0x158++0x03 line.long 0x00 "SDMA_CHNPRI22,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI22 ,Contains the priority of channel number 22" ",1,2,3,4,5,6,7" group.long 0x15C++0x03 line.long 0x00 "SDMA_CHNPRI23,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI23 ,Contains the priority of channel number 23" ",1,2,3,4,5,6,7" group.long 0x160++0x03 line.long 0x00 "SDMA_CHNPRI24,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI24 ,Contains the priority of channel number 24" ",1,2,3,4,5,6,7" group.long 0x164++0x03 line.long 0x00 "SDMA_CHNPRI25,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI25 ,Contains the priority of channel number 25" ",1,2,3,4,5,6,7" group.long 0x168++0x03 line.long 0x00 "SDMA_CHNPRI26,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI26 ,Contains the priority of channel number 26" ",1,2,3,4,5,6,7" group.long 0x16C++0x03 line.long 0x00 "SDMA_CHNPRI27,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI27 ,Contains the priority of channel number 27" ",1,2,3,4,5,6,7" group.long 0x170++0x03 line.long 0x00 "SDMA_CHNPRI28,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI28 ,Contains the priority of channel number 28" ",1,2,3,4,5,6,7" group.long 0x174++0x03 line.long 0x00 "SDMA_CHNPRI29,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI29 ,Contains the priority of channel number 29" ",1,2,3,4,5,6,7" group.long 0x178++0x03 line.long 0x00 "SDMA_CHNPRI30,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI30 ,Contains the priority of channel number 30" ",1,2,3,4,5,6,7" group.long 0x17C++0x03 line.long 0x00 "SDMA_CHNPRI31,Channel Priority Register" bitfld.long 0x00 0.--2. " CHNPRI31 ,Contains the priority of channel number 31" ",1,2,3,4,5,6,7" tree.end width 11. tree "Channel Enable RAM Registers" group.long 0x200++0x03 line.long 0x00 "CHNENBL0,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 0 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 0 is received" "Disabled,Enabled" textline " " group.long 0x204++0x03 line.long 0x00 "CHNENBL1,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 1 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 1 is received" "Disabled,Enabled" textline " " group.long 0x208++0x03 line.long 0x00 "CHNENBL2,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 2 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 2 is received" "Disabled,Enabled" textline " " group.long 0x20C++0x03 line.long 0x00 "CHNENBL3,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 3 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 3 is received" "Disabled,Enabled" textline " " group.long 0x210++0x03 line.long 0x00 "CHNENBL4,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 4 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 4 is received" "Disabled,Enabled" textline " " group.long 0x214++0x03 line.long 0x00 "CHNENBL5,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 5 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 5 is received" "Disabled,Enabled" textline " " group.long 0x218++0x03 line.long 0x00 "CHNENBL6,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 6 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 6 is received" "Disabled,Enabled" textline " " group.long 0x21C++0x03 line.long 0x00 "CHNENBL7,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 7 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 7 is received" "Disabled,Enabled" textline " " group.long 0x220++0x03 line.long 0x00 "CHNENBL8,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 8 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 8 is received" "Disabled,Enabled" textline " " group.long 0x224++0x03 line.long 0x00 "CHNENBL9,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 9 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 9 is received" "Disabled,Enabled" textline " " group.long 0x228++0x03 line.long 0x00 "CHNENBL10,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 10 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 10 is received" "Disabled,Enabled" textline " " group.long 0x22C++0x03 line.long 0x00 "CHNENBL11,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 11 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 11 is received" "Disabled,Enabled" textline " " group.long 0x230++0x03 line.long 0x00 "CHNENBL12,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 12 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 12 is received" "Disabled,Enabled" textline " " group.long 0x234++0x03 line.long 0x00 "CHNENBL13,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 13 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 13 is received" "Disabled,Enabled" textline " " group.long 0x238++0x03 line.long 0x00 "CHNENBL14,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 14 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 14 is received" "Disabled,Enabled" textline " " group.long 0x23C++0x03 line.long 0x00 "CHNENBL15,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 15 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 15 is received" "Disabled,Enabled" textline " " group.long 0x240++0x03 line.long 0x00 "CHNENBL16,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 16 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 16 is received" "Disabled,Enabled" textline " " group.long 0x244++0x03 line.long 0x00 "CHNENBL17,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 17 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 17 is received" "Disabled,Enabled" textline " " group.long 0x248++0x03 line.long 0x00 "CHNENBL18,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 18 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 18 is received" "Disabled,Enabled" textline " " group.long 0x24C++0x03 line.long 0x00 "CHNENBL19,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 19 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 19 is received" "Disabled,Enabled" textline " " group.long 0x250++0x03 line.long 0x00 "CHNENBL20,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 20 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 20 is received" "Disabled,Enabled" textline " " group.long 0x254++0x03 line.long 0x00 "CHNENBL21,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 21 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 21 is received" "Disabled,Enabled" textline " " group.long 0x258++0x03 line.long 0x00 "CHNENBL22,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 22 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 22 is received" "Disabled,Enabled" textline " " group.long 0x25C++0x03 line.long 0x00 "CHNENBL23,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 23 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 23 is received" "Disabled,Enabled" textline " " group.long 0x260++0x03 line.long 0x00 "CHNENBL24,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 24 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 24 is received" "Disabled,Enabled" textline " " group.long 0x264++0x03 line.long 0x00 "CHNENBL25,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 25 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 25 is received" "Disabled,Enabled" textline " " group.long 0x268++0x03 line.long 0x00 "CHNENBL26,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 26 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 26 is received" "Disabled,Enabled" textline " " group.long 0x26C++0x03 line.long 0x00 "CHNENBL27,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 27 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 27 is received" "Disabled,Enabled" textline " " group.long 0x270++0x03 line.long 0x00 "CHNENBL28,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 28 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 28 is received" "Disabled,Enabled" textline " " group.long 0x274++0x03 line.long 0x00 "CHNENBL29,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 29 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 29 is received" "Disabled,Enabled" textline " " group.long 0x278++0x03 line.long 0x00 "CHNENBL30,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 30 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 30 is received" "Disabled,Enabled" textline " " group.long 0x27C++0x03 line.long 0x00 "CHNENBL31,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 31 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 31 is received" "Disabled,Enabled" textline " " group.long 0x280++0x03 line.long 0x00 "CHNENBL32,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 32 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 32 is received" "Disabled,Enabled" textline " " group.long 0x284++0x03 line.long 0x00 "CHNENBL33,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 33 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 33 is received" "Disabled,Enabled" textline " " group.long 0x288++0x03 line.long 0x00 "CHNENBL34,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 34 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 34 is received" "Disabled,Enabled" textline " " group.long 0x28C++0x03 line.long 0x00 "CHNENBL35,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 35 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 35 is received" "Disabled,Enabled" textline " " group.long 0x290++0x03 line.long 0x00 "CHNENBL36,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 36 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 36 is received" "Disabled,Enabled" textline " " group.long 0x294++0x03 line.long 0x00 "CHNENBL37,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 37 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 37 is received" "Disabled,Enabled" textline " " group.long 0x298++0x03 line.long 0x00 "CHNENBL38,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 38 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 38 is received" "Disabled,Enabled" textline " " group.long 0x29C++0x03 line.long 0x00 "CHNENBL39,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 39 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 39 is received" "Disabled,Enabled" textline " " group.long 0x2A0++0x03 line.long 0x00 "CHNENBL40,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 40 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 40 is received" "Disabled,Enabled" textline " " group.long 0x2A4++0x03 line.long 0x00 "CHNENBL41,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 41 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 41 is received" "Disabled,Enabled" textline " " group.long 0x2A8++0x03 line.long 0x00 "CHNENBL42,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 42 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 42 is received" "Disabled,Enabled" textline " " group.long 0x2AC++0x03 line.long 0x00 "CHNENBL43,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 43 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 43 is received" "Disabled,Enabled" textline " " group.long 0x2B0++0x03 line.long 0x00 "CHNENBL44,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 44 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 44 is received" "Disabled,Enabled" textline " " group.long 0x2B4++0x03 line.long 0x00 "CHNENBL45,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 45 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 45 is received" "Disabled,Enabled" textline " " group.long 0x2B8++0x03 line.long 0x00 "CHNENBL46,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 46 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 46 is received" "Disabled,Enabled" textline " " group.long 0x2BC++0x03 line.long 0x00 "CHNENBL47,Channel Enable RAM" bitfld.long 0x00 31. " ENBL[31] ,Indicates that bit EP[31] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Indicates that bit EP[30] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Indicates that bit EP[29] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Indicates that bit EP[28] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Indicates that bit EP[27] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Indicates that bit EP[26] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Indicates that bit EP[25] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Indicates that bit EP[24] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " [23] ,Indicates that bit EP[23] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Indicates that bit EP[22] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Indicates that bit EP[21] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Indicates that bit EP[20] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Indicates that bit EP[19] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Indicates that bit EP[18] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Indicates that bit EP[17] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Indicates that bit EP[16] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " [15] ,Indicates that bit EP[15] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Indicates that bit EP[14] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Indicates that bit EP[13] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Indicates that bit EP[12] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Indicates that bit EP[11] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Indicates that bit EP[10] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Indicates that bit EP[9] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Indicates that bit EP[8] will be set when the DMA request 47 is received" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Indicates that bit EP[7] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Indicates that bit EP[6] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Indicates that bit EP[5] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Indicates that bit EP[4] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Indicates that bit EP[3] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Indicates that bit EP[2] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Indicates that bit EP[1] will be set when the DMA request 47 is received" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Indicates that bit EP[0] will be set when the DMA request 47 is received" "Disabled,Enabled" tree.end width 0x0B tree.end tree.open "IOMUXC (IOMUX Controller)" tree "IOMUXC_GPR" base ad:0x30340000 width 7. sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) group.long 0x00++0x03 line.long 0x00 "GPR0,GPR0 General Purpose Register" bitfld.long 0x00 6. " DMAREQ_MUX_SEL6 ,Selects between two possible sources for SDMA_EVENT41" "GPT4 counter event,FTM2 8 channel DMA request" bitfld.long 0x00 5. " DMAREQ_MUX_SEL5 ,Selects between two possible sources for SDMA_EVENT40" "GPT3 counter event,FTM1 7 channel DMA request" newline bitfld.long 0x00 4. " DMAREQ_MUX_SEL4 ,Selects between two possible sources for SDMA_EVENT47" "ENET1 1588 event1 out,ENET2 1588 event1 out" bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Selects between two possible sources for SDMA_EVENT21" "I2C4 DMA event,SIM2 transmit DMA request" newline bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Selects between two possible sources for SDMA_EVENT20" "I2C3 DMA event,SIM1 receive DMA request" bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Selects between two possible sources for SDMA_EVENT19" "I2C2 DMA event,SIM1 transmit DMA request" newline bitfld.long 0x00 0. " DMAREQ_MUX_SEL0 ,Selects between two possible sources for SDMA_EVENT18" "I2C1 DMA event,SIM1 receive DMA request" else group.long 0x00++0x03 line.long 0x00 "GPR0,GPR0 General Purpose Register" bitfld.long 0x00 6. " DMAREQ_MUX_SEL6 ,Selects between two possible sources for SDMA_EVENT41" "GPT4 counter event,FTM2 8 channel DMA request" bitfld.long 0x00 5. " DMAREQ_MUX_SEL5 ,Selects between two possible sources for SDMA_EVENT40" "GPT3 counter event,FTM1 7 channel DMA request" newline bitfld.long 0x00 4. " DMAREQ_MUX_SEL4 ,Selects between two possible sources for SDMA_EVENT47" "ENET1 1588 event1 out," bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Selects between two possible sources for SDMA_EVENT21" "I2C4 DMA event,SIM2 transmit DMA request" newline bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Selects between two possible sources for SDMA_EVENT20" "I2C3 DMA event,SIM1 receive DMA request" bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Selects between two possible sources for SDMA_EVENT19" "I2C2 DMA event,SIM1 transmit DMA request" newline bitfld.long 0x00 0. " DMAREQ_MUX_SEL0 ,Selects between two possible sources for SDMA_EVENT18" "I2C1 DMA event,SIM1 receive DMA request" endif sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) group.long 0x04++0x03 line.long 0x00 "GPR1,GPR1 General Purpose Register" bitfld.long 0x00 30. " ENABLE_OCRAM_EPDC ,Enable On-chip RAM EPDC function" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DBG_ACK ,Debug acknowledge, used in sec_wrapper" "None of the two cores,CA7 platform when CA7 core0 by peripherals,CA7 platform when CA7 core1 by peripherals,CA7 platform when any CA7 cores by peripherals" newline bitfld.long 0x00 23. " TZASC1_SECURE_BOOT_LOCK ,TZASC-1 secure boot lock" "Disabled,Enabled" bitfld.long 0x00 22. " EXC_ERR_RESP_EN ,Enables an ERR response on the AXI vs an OK response for an exclusive access error" "Disabled,Enabled" newline bitfld.long 0x00 18. " ENET2_CLK_DIR ,ENET2_TX_CLK data direction control when ANATOP ENET_REF_CLK2 is selected" "Disabled,Enabled" bitfld.long 0x00 17. " ENET1_CLK_DIR ,ENET1_TX_CLK data direction control when ANATOP ENET_REF_CLK1 is selected" "Disabled,Enabled" newline bitfld.long 0x00 16. " PAD_ADD_DS ,Output driver of the SD3 pins' strength" "Around 10% stronger,Normal" bitfld.long 0x00 14. " ENET2_TX_CLK_SEL ,ENET2 reference clock mode select" "ENET2 TX reference clock,From ENET2_TX_CLK pin" newline bitfld.long 0x00 13. " ENET1_TX_CLK_SEL ,ENET1 reference clock mode select" "ENET1 TX reference clock,From ENET1_TX_CLK pin" bitfld.long 0x00 12. " IRQ ,Interrupt signal used to notify cores on exception condition while boot" "No interrupt,Interrupt" newline bitfld.long 0x00 10.--11. " WEIM_ADDRS3 ,WEIM address space 3" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 9. " WEIM_ACT_CS3 ,WEIM active chip select 3" "Inactive,Active" newline bitfld.long 0x00 7.--8. " WEIM_ADDRS2 ,WEIM address space 2" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 6. " WEIM_ACT_CS2 ,WEIM active chip select 2" "Inactive,Active" newline bitfld.long 0x00 4.--5. " WEIM_ADDRS1 ,WEIM address space 1" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 3. " WEIM_ACT_CS1 ,WEIM active chip select 1" "Inactive,Active" newline bitfld.long 0x00 1.--2. " WEIM_ADDRS0 ,WEIM address space 0" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 0. " WEIM_ACT_CS0 ,WEIM active chip select 0" "Inactive,Active" else group.long 0x04++0x03 line.long 0x00 "GPR1,GPR1 General Purpose Register" bitfld.long 0x00 30. " ENABLE_OCRAM_GP ,Enable On-chip RAM General Purpose" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DBG_ACK ,Debug acknowledge, used in sec_wrapper" "None of the two cores,CA7 platform when CA7 core0 by peripherals,CA7 platform when CA7 core1 by peripherals,CA7 platform when any CA7 cores by peripherals" newline bitfld.long 0x00 23. " TZASC1_SECURE_BOOT_LOCK ,TZASC-1 secure boot lock" "Disabled,Enabled" bitfld.long 0x00 22. " EXC_ERR_RESP_EN ,Enables an ERR response on the AXI vs an OK response for an exclusive access error" "Disabled,Enabled" newline bitfld.long 0x00 17. " ENET1_CLK_DIR ,ENET1_TX_CLK data direction control when ANATOP ENET_REF_CLK1 is selected" "Disabled,Enabled" newline bitfld.long 0x00 16. " PAD_ADD_DS ,Output driver of the SD3 pins' strength" "Around 10% stronger,Normal" newline bitfld.long 0x00 13. " ENET1_TX_CLK_SEL ,ENET1 reference clock mode select" "ENET1 TX reference clock,From ENET1_TX_CLK pin" bitfld.long 0x00 12. " IRQ ,Interrupt signal used to notify cores on exception condition while boot" "No interrupt,Interrupt" newline bitfld.long 0x00 10.--11. " WEIM_ADDRS3 ,WEIM address space 3" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 9. " WEIM_ACT_CS3 ,WEIM active chip select 3" "Inactive,Active" newline bitfld.long 0x00 7.--8. " WEIM_ADDRS2 ,WEIM address space 2" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 6. " WEIM_ACT_CS2 ,WEIM active chip select 2" "Inactive,Active" newline bitfld.long 0x00 4.--5. " WEIM_ADDRS1 ,WEIM address space 1" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 3. " WEIM_ACT_CS1 ,WEIM active chip select 1" "Inactive,Active" newline bitfld.long 0x00 1.--2. " WEIM_ADDRS0 ,WEIM address space 0" "128M&0M&0M&0M,64M&64M&0M&0M,64M&32M&32M&0M,32M&32M&32M&32M" bitfld.long 0x00 0. " WEIM_ACT_CS0 ,WEIM active chip select 0" "Inactive,Active" endif group.long 0x08++0x07 line.long 0x00 "GPR2,GPR2 General Purpose Register" bitfld.long 0x00 26. " MQS_OVERSAMPLE ,MQS PWM over-sampling rate option" "32,64" bitfld.long 0x00 25. " MQS_EN ,MQS enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " MQS_SW_RST ,MQS software reset" "No reset,Reset" hexmask.long.byte 0x00 16.--23. 1. " MQS_CLK_DIV ,MQS clock divider control" line.long 0x04 "GPR3,GPR3 General Purpose Register" rbitfld.long 0x04 31. " P_WADDR_PIPE_EN_PNDG ,PXP On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 30. " P_WDATA_PIPE_EN_PNDG ,PXP On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" newline rbitfld.long 0x04 29. " P_RADDR_PIPE_EN_PNDG ,PXP On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 28. " P_RDATA_WAIT_EN_PNDG ,PXP On-chip RAM read data wait state control update is pending" "Not pending,Pending" newline rbitfld.long 0x04 27. " E_WADDR_PIPE_EN_PNDG ,EPDC On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 26. " E_WDATA_PIPE_EN_PNDG ,EPDC On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" newline rbitfld.long 0x04 25. " E_RADDR_PIPE_EN_PNDG ,EPDC On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 24. " E_RDATA_WAIT_EN_PNDG ,EPDC On-chip RAM read data wait state control update is pending" "Not pending,Pending" newline rbitfld.long 0x04 23. " S_WADDR_PIPE_EN_PNDG ,State retention On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 22. " S_WDATA_PIPE_EN_PNDG ,State retention On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" newline rbitfld.long 0x04 21. " S_RADDR_PIPE_EN_PNDG ,State retention On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 20. " S_RDATA_WAIT_EN_PNDG ,State retention On-chip RAM read data wait state control update is pending" "Not pending,Pending" newline rbitfld.long 0x04 19. " WADDR_PIPE_EN_PNDG ,On-chip RAM write address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 18. " WDATA_PIPE_EN_PDG ,On-chip RAM write data pipeline enable update is pending" "Not pending,Pending" newline rbitfld.long 0x04 17. " RADDR_PIPE_EN_PDG ,On-chip RAM read address pipeline enable update is pending" "Not pending,Pending" rbitfld.long 0x04 16. " RDATA_WAIT_EN_PDG ,On-chip RAM read data wait state control update is pending" "Not pending,Pending" newline bitfld.long 0x04 15. " P_WADDR_PIPE_EN ,PXP On-chip RAM write address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 14. " P_WDATA_PIPE_EN ,PXP On-chip RAM write data pipeline enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " P_RADDR_PIPE_EN ,PXP On-chip RAM read address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 12. " P_RDATA_WAIT_EN ,PXP On-chip RAM read data wait state control" "Disabled,Enabled" newline bitfld.long 0x04 11. " E_WADDR_PIPE_EN ,EPDC On-chip RAM write address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 10. " E_WDATA_PIPE_EN ,EPDC On-chip RAM write data pipeline enable" "Disabled,Enabled" newline bitfld.long 0x04 9. " E_RADDR_PIPE_EN ,EPDC On-chip RAM read address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 8. " E_RDATA_WAIT_EN ,EPDC On-chip RAM read data wait state control" "Disabled,Enabled" newline bitfld.long 0x04 7. " S_WADDR_PIPE_EN ,State retention On-chip RAM write address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 6. " S_WDATA_PIPE_EN ,State retention On-chip RAM write data pipeline enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " S_RADDR_PIPE_EN ,State retention On-chip RAM read address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 4. " S_RDATA_WAIT_EN ,State retention On-chip RAM read data wait state control" "Disabled,Enabled" newline bitfld.long 0x04 3. " WADDR_PIPE_EN ,On-chip RAM write address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 2. " WDATA_PIPE_EN ,On-chip RAM write data pipeline enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " RADDR_PIPE_EN ,On-chip RAM read address pipeline enable" "Disabled,Enabled" bitfld.long 0x04 0. " RDATA_WAIT_EN ,On-chip RAM read data wait state control" "Disabled,Enabled" sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) group.long 0x10++0x07 line.long 0x00 "GPR4,GPR4 General Purpose Register" rbitfld.long 0x00 28. " CPU_STANDBYWFE[1] ,Status of CPU STANDBYWFE low power states of A7 core 1" "Normal,Low power" rbitfld.long 0x00 27. " CPU_STANDBYWFE[0] ,Status of CPU STANDBYWFE low power states of A7 core 0" "Normal,Low power" newline rbitfld.long 0x00 26. " CPU_STANDBYWFI[1] ,Status of CPU STANDBYWFI low power states of A7 core 1" "Normal,Low power" rbitfld.long 0x00 25. " CPU_STANDBYWFI[0] ,Status of CPU STANDBYWFI low power states of A7 core 0" "Normal,Low power" newline rbitfld.long 0x00 23. " SAI3_IPG_STOP_ACK ,SAI3 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 22. " SAI2_IPG_STOP_ACK ,SAI2 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 21. " SAI1_IPG_STOP_ACK ,SAI1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 20. " ENET2_IPG_STOP_ACK ,ENET2 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 19. " ENET1_IPG_STOP_ACK ,ENET1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 18. " CAN2_IPG_STOP_ACK ,CAN2 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 17. " CAN1_IPG_STOP_ACK ,CAN1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 16. " SDMA_IPG_STOP_ACK ,SDMA stop acknowledge" "Not asserted,Asserted" newline bitfld.long 0x00 7. " SAI3_IPG_STOP ,SAI3 stop request" "Off,On" bitfld.long 0x00 6. " SAI2_IPG_STOP ,SAI2 stop request" "Off,On" newline bitfld.long 0x00 5. " SAI1_IPG_STOP ,SAI1 stop request" "Off,On" bitfld.long 0x00 4. " ENET2_IPG_STOP ,ENET2 stop request" "Off,On" newline bitfld.long 0x00 3. " ENET1_IPG_STOP ,ENET1 stop request" "Off,On" bitfld.long 0x00 2. " CAN2_IPG_STOP ,CAN2 stop request" "Off,On" newline bitfld.long 0x00 1. " CAN1_IPG_STOP ,CAN1 stop request" "Off,On" bitfld.long 0x00 0. " SDMA_IPG_STOP ,SDMA stop request" "Off,On" line.long 0x04 "GPR5,GPR5 General Purpose Register" bitfld.long 0x04 31. " REF_1M_CLK_GPT4 ,Reference 1M clock GPT4" "CCM GPT clock,1MHz clock" bitfld.long 0x04 30. " REF_1M_CLK_GPT3 ,GPT3 1mhz clock source select" "CCM GPT clock,1MHz clock" newline bitfld.long 0x04 29. " REF_1M_CLK_GPT2 ,GPT2 1mhz clock source select" "CCM GPT clock,1MHz clock" bitfld.long 0x04 28. " REF_1M_CLK_GPT1 ,GPT1 1mhz clock source select" "CCM GPT clock,1MHz clock" newline bitfld.long 0x04 27. " ENET2_EVENT3IN_SEL ,ENET2 mac 0 1588 timer event 3 select" "PAD,GPT4 channel 2 compare output" bitfld.long 0x04 26. " ENET1_EVENT3IN_SEL ,ENET1 mac 0 1588 timer event 3 select" "PAD,GPT4 channel 1 compare output" newline bitfld.long 0x04 25. " GPT4_CAPIN2_SEL ,GPT4 capture channel 2 trigger signal select" "GPT4 CAPTURE2 signal from PAD,ENET2 1588 event 3" bitfld.long 0x04 24. " GPT4_CAPIN1_SEL ,GPT4 capture channel 1 trigger signal select" "GPT4 CAPTURE1 signal from PAD,ENET1 1588 event 3" newline bitfld.long 0x04 22. " WDOG4_MASK ,WDOG4 timeout mask" "Not masked,Masked" bitfld.long 0x04 20. " WDOG3_MASK ,WDOG3 timeout mask" "Not masked,Masked" newline bitfld.long 0x04 12. " LCDIF_HANDSHAKE ,LCDIF input handshake select" "CSI,PXP" bitfld.long 0x04 7. " WDOG2_MASK ,WDOG2 timeout mask" "Not masked,Masked" newline bitfld.long 0x04 6. " WDOG1_MASK ,WDOG1 timeout mask" "Not masked,Masked" bitfld.long 0x04 4. " CSI_MUX_CONTROL ,CSI input MUX control" "Parallel CSI,MIPI CSI" else group.long 0x10++0x07 line.long 0x00 "GPR4,GPR4 General Purpose Register" rbitfld.long 0x00 28. " CPU_STANDBYWFE[1] ,Status of CPU STANDBYWFE low power states of A7 core 1" "Normal,Low power" rbitfld.long 0x00 27. " CPU_STANDBYWFE[0] ,Status of CPU STANDBYWFE low power states of A7 core 0" "Normal,Low power" newline rbitfld.long 0x00 26. " CPU_STANDBYWFI[1] ,Status of CPU STANDBYWFI low power states of A7 core 1" "Normal,Low power" rbitfld.long 0x00 25. " CPU_STANDBYWFI[0] ,Status of CPU STANDBYWFI low power states of A7 core 0" "Normal,Low power" newline rbitfld.long 0x00 23. " SAI3_IPG_STOP_ACK ,SAI3 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 22. " SAI2_IPG_STOP_ACK ,SAI2 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 21. " SAI1_IPG_STOP_ACK ,SAI1 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 19. " ENET1_IPG_STOP_ACK ,ENET1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 18. " CAN2_IPG_STOP_ACK ,CAN2 stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x00 17. " CAN1_IPG_STOP_ACK ,CAN1 stop acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 16. " SDMA_IPG_STOP_ACK ,SDMA stop acknowledge" "Not asserted,Asserted" newline bitfld.long 0x00 7. " SAI3_IPG_STOP ,SAI3 stop request" "Off,On" bitfld.long 0x00 6. " SAI2_IPG_STOP ,SAI2 stop request" "Off,On" newline bitfld.long 0x00 5. " SAI1_IPG_STOP ,SAI1 stop request" "Off,On" newline bitfld.long 0x00 3. " ENET1_IPG_STOP ,ENET1 stop request" "Off,On" bitfld.long 0x00 2. " CAN2_IPG_STOP ,CAN2 stop request" "Off,On" newline bitfld.long 0x00 1. " CAN1_IPG_STOP ,CAN1 stop request" "Off,On" bitfld.long 0x00 0. " SDMA_IPG_STOP ,SDMA stop request" "Off,On" line.long 0x04 "GPR5,GPR5 General Purpose Register" bitfld.long 0x04 31. " REF_1M_CLK_GPT4 ,Reference 1M clock GPT4" "CCM GPT clock,1MHz clock" bitfld.long 0x04 30. " REF_1M_CLK_GPT3 ,GPT3 1mhz clock source select" "CCM GPT clock,1MHz clock" newline bitfld.long 0x04 29. " REF_1M_CLK_GPT2 ,GPT2 1mhz clock source select" "CCM GPT clock,1MHz clock" bitfld.long 0x04 28. " REF_1M_CLK_GPT1 ,GPT1 1mhz clock source select" "CCM GPT clock,1MHz clock" newline bitfld.long 0x04 26. " ENET1_EVENT3IN_SEL ,ENET1 mac 0 1588 timer event 3 select" "PAD,GPT4 channel 1 compare output" newline bitfld.long 0x04 25. " GPT4_CAPIN2_SEL ,GPT4 capture channel 2 trigger signal select" "GPT4 CAPTURE2 signal from PAD,ENET2 1588 event 3" bitfld.long 0x04 24. " GPT4_CAPIN1_SEL ,GPT4 capture channel 1 trigger signal select" "GPT4 CAPTURE1 signal from PAD,ENET1 1588 event 3" newline bitfld.long 0x04 22. " WDOG4_MASK ,WDOG4 timeout mask" "Not masked,Masked" bitfld.long 0x04 20. " WDOG3_MASK ,WDOG3 timeout mask" "Not masked,Masked" newline bitfld.long 0x04 12. " LCDIF_HANDSHAKE ,LCDIF input handshake select" "CSI,PXP" bitfld.long 0x04 7. " WDOG2_MASK ,WDOG2 timeout mask" "Not masked,Masked" newline bitfld.long 0x04 6. " WDOG1_MASK ,WDOG1 timeout mask" "Not masked,Masked" bitfld.long 0x04 4. " CSI_MUX_CONTROL ,CSI input MUX control" "Parallel CSI,MIPI CSI" endif group.long 0x18++0x03 line.long 0x00 "GPR6,GPR6 General Purpose Register" bitfld.long 0x00 3. " AWCACHE_PXP6_EN ,PXP secondary AXI master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 2. " ARCACHE_PXP6_EN ,PXP secondary AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " AWCACHE_PXP6 ,PXP secondary AXI master port AWCACHE override value" "0,1" bitfld.long 0x00 0. " ARCACHE_PXP6 ,PXP secondary AXI master port ARCACHE override value" "0,1" newline sif (CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x1C++0x03 line.long 0x00 "GPR7,GPR7 General Purpose Register" bitfld.long 0x00 3. " CHD1_EN_PWRUPLOAD ,Places a resistive load on the USB auxiliary charge detector 1 ldo_usb_1p0 output" "Disabled,Enabled" newline elif (CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7DUAL-CA7")) group.long 0x1C++0x03 line.long 0x00 "GPR7,GPR7 General Purpose Register" bitfld.long 0x00 9. " CHD2_EN_PWRUPLOAD_LDO_USB_1P0 ,CHD2 EN PWRUPLOAD LDO USB 1P0" "Disabled,Enabled" newline bitfld.long 0x00 3. " CHD1_EN_PWRUPLOAD ,Places a resistive load on the USB auxiliary charge detector 1 ldo_usb_1p0 output" "Disabled,Enabled" newline else group.long 0x1C++0x03 line.long 0x00 "GPR7,GPR7 General Purpose Register" bitfld.long 0x00 10.--11. " CHD2_TEST ,Test controls for USB auxiliary charger detector 2" "Normal,Ldo_usb_1p0 regulator overdrive test/characterization mode,POR local generator test/characterization mode,?..." bitfld.long 0x00 9. " CHD2_EN_PWRUPLOAD_LDO_USB_1P0 ,CHD2 EN PWRUPLOAD LDO USB 1P0" "Disabled,Enabled" newline bitfld.long 0x00 4.--5. " CHD1_TEST ,Test controls for USB auxiliary charger detector 1" "Normal,Ldo_usb_1p0 regulator overdrive test/characterization mode,POR local generator test/characterization mode,?..." bitfld.long 0x00 3. " CHD1_EN_PWRUPLOAD ,Places a resistive load on the USB auxiliary charge detector 1 ldo_usb_1p0 output" "Disabled,Enabled" newline endif group.long 0x20++0x0F line.long 0x00 "GPR8,GPR8 General Purpose Register" bitfld.long 0x00 8. " DDR_PHY_DFI_INIT_START ,Drives dfi_init_start input on DDR PHY" "0,1" bitfld.long 0x00 3.--7. " DDR_PHY_CTRL_WAKE_UP ,Drives ctrl_wake_up inputs on DDR PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "GPR9,GPR9 General Purpose Register" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x04 0. " TZASC1_MUX_CONTROL ,TrustZone address space controller select" "Bypassed,Passed" else bitfld.long 0x04 1.--5. " DDR_PHY_CTRL_PD ,Drives ctrl_pd inputs on DDR PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0. " TZASC1_MUX_CONTROL ,TrustZone address space controller select" "Bypassed,Passed" endif line.long 0x08 "GPR10,GPR10 General Purpose Register" hexmask.long.byte 0x08 18.--25. 1. " GPR10_LOCK ,Lock bits for bits [9:2]" bitfld.long 0x08 4.--9. " OCRAM_EPDC_TZ_ADDR ,EPDC OCRAM TrustZone start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 3. " OCRAM_EPDC_TZ_EN ,EPDC OCRAM TrustZone enable" "Disabled,Enabled" bitfld.long 0x08 2. " SEC_ERR_RESP_EN ,Security error response enable for all security gaskets" "Disabled,Enabled" line.long 0x0C "GPR11,GPR11 General Purpose Register" hexmask.long.word 0x0C 16.--29. 1. " GPR11_LOCK ,Bits [29:16] are lock bits for bits [13:0]" bitfld.long 0x0C 11.--13. " OCRAM_S_TZ_ADDR ,State retention OCRAM TrustZone start address" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10. " OCRAM_S_TZ_EN ,State retention OCRAM TrustZone enable" "Disabled,Enabled" bitfld.long 0x0C 7.--9. " OCRAM_PXP_TZ_ADDR ,PXP OCRAM TrustZone start address" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6. " OCRAM_PXP_TZ_EN ,PXP OCRAM TrustZone enable" "Disabled,Enabled" bitfld.long 0x0C 1.--5. " OCRAM_TZ_ADDR ,OCRAM TrustZone start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 0. " OCRAM_TZ_EN ,OCRAM TrustZone enable" "Disabled,Enabled" sif (!(CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4"))) group.long 0x30++0x03 line.long 0x00 "GPR12,GPR12 General Purpose Register" bitfld.long 0x00 21.--23. " PCIE_CTRL_DIAG_CTRL_BUS ,PCI express diagnostic control bus" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--20. " PCIE_CTRL_DIAG_STATUS_BUS_SELECT ,PCI express diagnostic status bus select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " PCIE_CTRL_DEVICE_TYPE ,PCI express device/port type" "PCI express endpoint,Legacy PCI express endpoint,,,Root port of PCI express root complex,?..." newline bitfld.long 0x00 5. " PCIE_PHY_REFCLK_SEL ,Internal Reference Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PCIE_PHY_CMN_REG_RST ,Reset of COMMON APB Function" "No reset,Reset" bitfld.long 0x00 3. " PCIE_PHY_SSC_EN ,Transmitter Spread Spectrum Clocking Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_PHY_TRSV_RST_CH0 ,Transceiver Block Reset Function" "No reset,Reset" bitfld.long 0x00 0. " PCIE_PHY_TRSV_REG_RST_CH0 ,Reset of TRANSCEIVER APB or I2C Function" "No reset,Reset" endif sif (CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x34++0x03 line.long 0x00 "GPR13,GPR13 General Purpose Register" bitfld.long 0x00 12. " ARCACHE_LCDIF_EN ,LCDIF AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " AWCACHE_PXP_EN ,PXP primary AXI master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 8. " ARCACHE_PXP_EN ,PXP primary AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " ARCACHE_LCDIF ,LCDIF AXI master port ARCACHE override value" "0,1" newline bitfld.long 0x00 3. " AWCACHE_PXP ,PXP primary AXI master port AWCACHE override value" "0,1" bitfld.long 0x00 2. " ARCACHE_PXP ,PXP primary AXI master port ARCACHE override value" "0,1" newline bitfld.long 0x00 1. " AWCACHE_USDHC ,USDHC 1-3 AXI master AWCACHE override value" "0,1" bitfld.long 0x00 0. " ARCACHE_USDHC ,USDHC 1-3 AXI master ARCACHE override value" "0,1" else group.long 0x34++0x03 line.long 0x00 "GPR13,GPR13 General Purpose Register" rbitfld.long 0x00 31. " PCIE_PHY_PCS_REFCLK_DISABLE ,Indicates whether PHY is ready for reference clock to be disabled" "No,Yes" rbitfld.long 0x00 30. " PCIE_PHY_CDR_VCO_MON_CH0 ,CDR VCO monitor channel 0" "0,1" newline rbitfld.long 0x00 29. " PCIE_PHY_PMA_RX_PRESENT_CH0 ,Receiver Detected Indication for PCIe Test" "Not detected,Detected" rbitfld.long 0x00 28. " PCIE_PHY_PMA_CDR_LOCKED_CH0 ,PLL Lock Indication for PCIe Test. CDR locking done" "No,Yes" newline rbitfld.long 0x00 24.--27. " PCIE_PHY_VCO_BAND ,Monitoring code of VCO calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " PCIE_PHY_AFC_CODE_OUT_CH0 ,Monitoring AFC code, channel 0" newline bitfld.long 0x00 15. " AWCACHE_EPDC_EN ,EPDC AXI master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 14. " AWCACHE_EPDC ,EPDC AXI master port AWCACHE override value" "0,1" newline bitfld.long 0x00 13. " ARCACHE_EPDC_EN ,EPDC AXI master port ARCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 12. " ARCACHE_LCDIF_EN ,LCDIF AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " AWCACHE_PCIE_EN ,PCIE AXI master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 10. " ARCACHE_PCIE_EN ,PCIE AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " AWCACHE_PXP_EN ,PXP primary AXI master port AWCACHE override enable" "Disabled,Enabled" bitfld.long 0x00 8. " ARCACHE_PXP_EN ,PXP primary AXI master port ARCACHE override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " ARCACHE_EPDC ,EPDC AXI master port ARCACHE override value" "0,1" bitfld.long 0x00 6. " ARCACHE_LCDIF ,LCDIF AXI master port ARCACHE override value" "0,1" newline bitfld.long 0x00 5. " AWCACHE_PCIE ,PCIE AXI master port AWCACHE override value" "0,1" bitfld.long 0x00 4. " ARCACHE_PCIE ,PCIE AXI master port ARCACHE override value" "0,1" newline bitfld.long 0x00 3. " AWCACHE_PXP ,PXP primary AXI master port AWCACHE override value" "0,1" bitfld.long 0x00 2. " ARCACHE_PXP ,PXP primary AXI master port ARCACHE override value" "0,1" newline bitfld.long 0x00 1. " AWCACHE_USDHC ,USDHC 1-3 AXI master AWCACHE override value" "0,1" bitfld.long 0x00 0. " ARCACHE_USDHC ,USDHC 1-3 AXI master ARCACHE override value" "0,1" endif group.long 0x38++0x03 line.long 0x00 "GPR14,GPR14 General Purpose Register" bitfld.long 0x00 1. " SIM2_SIMV2_EMV_SEL ,SIM2 EMV select" "SIMv2,EMV" bitfld.long 0x00 0. " SIM1_SIMV2_EMV_SEL ,SIM1 EMV select" "SIMv2,EMV" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") group.long 0x50++0x03 line.long 0x00 "GPR20,GPR20 General Purpose Register" bitfld.long 0x00 10.--11. " LVDS_M[11:10] ,OTG2 PHY charger detection disable" "No,,,Yes" bitfld.long 0x00 8.--9. " LVDS_M[9:8] ,OTG1 PHY charger detection disable" "No,,,Yes" endif sif (CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) rgroup.long 0x58++0x03 line.long 0x00 "GPR22,GPR22 General Purpose Register" bitfld.long 0x00 29. " CHD1_ISO_ENA_1 ,USB auxiliary charge detector 1 isolation control signal" "Low,High" newline bitfld.long 0x00 28. " CHD1_DVDD_STABLE ,Allows vdd_soc domain to monitor when dvdd_usb domain is valid" "Not stable,Stable" newline bitfld.long 0x00 25. " DFI_INIT_COMPLETE ,DDR PHY initialization complete" "Not complete,Complete" newline bitfld.long 0x00 24. " DDRC_MRR_VALID ,DDR controller mode register read data valid" "Invalid,Valid" hexmask.long.byte 0x00 16.--23. 1. " DDRC_MRR_DATA ,DDR controller mode register read data" else rgroup.long 0x58++0x03 line.long 0x00 "GPR22,GPR22 General Purpose Register" bitfld.long 0x00 31. " PCIE_PHY_PLL_LOCKED ,PLL lock indication" "Unlocked,Locked" bitfld.long 0x00 29. " CHD1_ISO_ENA_1 ,USB auxiliary charge detector 1 isolation control signal" "Low,High" newline bitfld.long 0x00 28. " CHD1_DVDD_STABLE ,Allows vdd_soc domain to monitor when dvdd_usb domain is valid" "Not stable,Stable" bitfld.long 0x00 27. " CHD2_ISO_ENA_1 ,USB auxiliary charge detector 2 isolation control signal" "Low,High" newline bitfld.long 0x00 26. " CHD2_DVDD_STABLE ,Allows vdd_soc domain to monitor when dvdd_usb domain is valid" "Not stable,Stable" bitfld.long 0x00 25. " DFI_INIT_COMPLETE ,DDR PHY initialization complete" "Not complete,Complete" newline bitfld.long 0x00 24. " DDRC_MRR_VALID ,DDR controller mode register read data valid" "Invalid,Valid" hexmask.long.byte 0x00 16.--23. 1. " DDRC_MRR_DATA ,DDR controller mode register read data" endif width 0x0B tree.end tree "IOMUXC_LPSR" base ad:0x302C0000 width 28. group.long 0x00++0x0B line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO00,SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO0,PWM4_OUT,WDOG1_WDOG_ANYWDOG1_WDOG_B,WDOG1_WDOG_RST_B_DEB,?..." line.long 0x04 "SW_MUX_CTL_PAD_GPIO1_IO01,SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO1,PWM1_OUT,CCM_ENET_REF_CLK3,SAI1_MCLK,REF_CLK_24M,?..." else bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO1,PWM1_OUT,CCM_ENET_REF_CLK3,SAI1_MCLK,?..." endif line.long 0x08 "SW_MUX_CTL_PAD_GPIO1_IO02,SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO2,PWM2_OUT,CCM_ENET_REF_CLK1,SAI2_MCLK,REF_CLK_32K,CCM_CLKO1,,USB_OTG1_ID" else bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO2,PWM2_OUT,CCM_ENET_REF_CLK1,SAI2_MCLK,,CCM_CLKO1,,USB_OTG1_ID" endif sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) group.long 0x0C++0x03 line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO03,SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO3,PWM3_OUT,CCM_ENET_REF_CLK2,SAI3_MCLK,,CCM_CLKO2,,USB_OTG2_ID" else group.long 0x0C++0x03 line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO03,SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO3,PWM3_OUT,CCM_ENET_REF_CLK2,SAI3_MCLK,,CCM_CLKO2,?..." endif group.long 0x10++0x0B line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO04,SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO4,USB_OTG1_OC,FLEXTIMER1_CH4,UART5_CTS_B,I2C1_SCL,?..." line.long 0x04 "SW_MUX_CTL_PAD_GPIO1_IO05,SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO5,USB_OTG1_PWR,FLEXTIMER1_CH5,UART5_RTS_B,I2C1_SDA,?..." line.long 0x08 "SW_MUX_CTL_PAD_GPIO1_IO06,SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO6,USB_OTG2_OC,FLEXTIMER1_CH6,UART5_RX_DATA,I2C2_SCL,CCM_WAIT,KPP_ROW4,?..." sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) group.long 0x1C++0x03 line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO07,SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO7,USB_OTG2_PWR,FLEXTIMER1_CH7,UART5_TX_DATA,I2C2_SDA,CCM_STOP,KPP_COL4,?..." else group.long 0x1C++0x03 line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO07,SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO7,,FLEXTIMER1_CH7,UART5_TX_DATA,I2C2_SDA,CCM_STOP,KPP_COL4,?..." endif group.long 0x20++0x03 line.long 0x00 "SW_PAD_CTL_PAD_TEST_MODE,SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" rbitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline rbitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x24++0x03 line.long 0x00 "SW_PAD_CTL_PAD_SRC_POR_B,SW_PAD_CTL_PAD_SRC_POR_B SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" rbitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline rbitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x28++0x03 line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE0,SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" rbitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline rbitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x2C++0x03 line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE1,SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" rbitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline rbitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x30++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO00,SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x34++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO01,SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x38++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO02,SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x3C++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO03,SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x40++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO04,SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x44++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO05,SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x48++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO06,SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" group.long 0x4C++0x03 line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO07,SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register" bitfld.long 0x00 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x00 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x00 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x00 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" width 0x0B tree.end tree "IOMUXC_LPSR_GPR" base ad:0x30270000 width 19. group.long 0x00++0x5B line.long 0x00 "IOMUXC_LPSR_GPR0,IOMUXC_LPSR General Purpose Register 0" line.long 0x04 "IOMUXC_LPSR_GPR1,IOMUXC_LPSR General Purpose Register 1" line.long 0x08 "IOMUXC_LPSR_GPR2,IOMUXC_LPSR General Purpose Register 2" line.long 0x0C "IOMUXC_LPSR_GPR3,IOMUXC_LPSR General Purpose Register 3" hexmask.long.word 0x0C 16.--31. 1. " RO ,Read only bits" hexmask.long.word 0x0C 0.--15. 1. " GP ,Common bits can be R/W freely" line.long 0x10 "IOMUXC_LPSR_GPR4,IOMUXC_LPSR General Purpose Register 4" hexmask.long.word 0x10 16.--31. 1. " RO ,Read only bits" hexmask.long.word 0x10 0.--15. 1. " GP ,Common bits can be R/W freely" line.long 0x14 "IOMUXC_LPSR_GPR5,IOMUXC_LPSR General Purpose Register 5" line.long 0x18 "IOMUXC_LPSR_GPR6,IOMUXC_LPSR General Purpose Register 6" line.long 0x1C "IOMUXC_LPSR_GPR7,IOMUXC_LPSR General Purpose Register 7" line.long 0x20 "IOMUXC_LPSR_GPR8,IOMUXC_LPSR General Purpose Register 8" line.long 0x24 "IOMUXC_LPSR_GPR9,IOMUXC_LPSR General Purpose Register 9" line.long 0x28 "IOMUXC_LPSR_GPR10,IOMUXC_LPSR General Purpose Register 10" hexmask.long.word 0x28 16.--31. 1. " STICKY ,Bits are lock bits for LOCK bits" hexmask.long.word 0x28 0.--15. 1. " LOCK ,Lock type bits" line.long 0x2C "IOMUXC_LPSR_GPR11,IOMUXC_LPSR General Purpose Register 11" hexmask.long.word 0x2C 16.--31. 1. " STICKY ,Bits are lock bits for LOCK bits" hexmask.long.word 0x2C 0.--15. 1. " LOCK ,Lock type bits" line.long 0x30 "IOMUXC_LPSR_GPR12,IOMUXC_LPSR General Purpose Register 12" line.long 0x34 "IOMUXC_LPSR_GPR13,IOMUXC_LPSR General Purpose Register 13" hexmask.long.word 0x34 16.--31. 1. " RO ,Read only bits" hexmask.long.word 0x34 0.--15. 1. " GP ,Common bits can be R/W freely" line.long 0x38 "IOMUXC_LPSR_GPR14,IOMUXC_LPSR General Purpose Register 14" line.long 0x3C "IOMUXC_LPSR_GPR15,IOMUXC_LPSR General Purpose Register 15" line.long 0x40 "IOMUXC_LPSR_GPR16,IOMUXC_LPSR General Purpose Register 16" line.long 0x44 "IOMUXC_LPSR_GPR17,IOMUXC_LPSR General Purpose Register 17" line.long 0x48 "IOMUXC_LPSR_GPR18,IOMUXC_LPSR General Purpose Register 18" line.long 0x4C "IOMUXC_LPSR_GPR19,IOMUXC_LPSR General Purpose Register 19" line.long 0x50 "IOMUXC_LPSR_GPR20,IOMUXC_LPSR General Purpose Register 20" bitfld.long 0x50 31. " GPIO1_IO11_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x50 29.--30. " GPIO1_IO11_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x50 28. " GPIO1_IO11_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x50 27. " GPIO1_IO11_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x50 26. " GPIO1_IO11_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x50 24.--25. " GPIO1_IO11_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x50 23. " GPIO1_IO10_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x50 21.--22. " GPIO1_IO10_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x50 20. " GPIO1_IO10_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x50 19. " GPIO1_IO10_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x50 18. " GPIO1_IO10_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x50 16.--17. " GPIO1_IO10_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x50 15. " GPIO1_IO09_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x50 13.--14. " GPIO1_IO1_9PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x50 12. " GPIO1_IO09_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x50 11. " GPIO1_IO09_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x50 10. " GPIO1_IO09_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x50 8.--9. " GPIO1_IO09_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x50 7. " GPIO1_IO08_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x50 5.--6. " GPIO1_IO08_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x50 4. " GPIO1_IO08_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x50 3. " GPIO1_IO08_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x50 2. " GPIO1_IO08_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x50 0.--1. " GPIO1_IO08_DSE ,Drive strength field" "X1,X2,X4,X6" line.long 0x54 "IOMUXC_LPSR_GPR21,IOMUXC_LPSR General Purpose Register 21" bitfld.long 0x54 31. " GPIO1_IO15_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x54 29.--30. " GPIO1_IO15_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x54 28. " GPIO1_IO15_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x54 27. " GPIO1_IO15_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x54 26. " GPIO1_IO15_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x54 24.--25. " GPIO1_IO15_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x54 23. " GPIO1_IO14_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x54 21.--22. " GPIO1_IO14_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x54 20. " GPIO1_IO14_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x54 19. " GPIO1_IO14_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x54 18. " GPIO1_IO14_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x54 16.--17. " GPIO1_IO14_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x54 15. " GPIO1_IO13_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x54 13.--14. " GPIO1_IO113PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x54 12. " GPIO1_IO13_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x54 11. " GPIO1_IO13_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x54 10. " GPIO1_IO13_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x54 8.--9. " GPIO1_IO13_DSE ,Drive strength field" "X1,X2,X4,X6" textline " " bitfld.long 0x54 7. " GPIO1_IO12_MUX_CTL ,MUX control for PAD" "SOC IOMUX,LPSR GPR" bitfld.long 0x54 5.--6. " GPIO1_IO12_PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x54 4. " GPIO1_IO12_PE ,Pull enable field" "Disabled,Enabled" textline " " bitfld.long 0x54 3. " GPIO1_IO12_HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x54 2. " GPIO1_IO12_SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x54 0.--1. " GPIO1_IO12_DSE ,Drive strength field" "X1,X2,X4,X6" line.long 0x58 "IOMUXC_LPSR_GPR22,IOMUXC_LPSR General Purpose Register 22" hexmask.long.word 0x58 16.--31. 1. " RO ,Read only bits" hexmask.long.word 0x58 0.--15. 1. " GP ,Common bits can be R/W freely" width 0x0B tree.end tree "IOMUXC" base ad:0x30330000 width 35. group.long 0x14++0x72B line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO08,SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO8,SD1_VSELECT,WDOG1_WDOG_B,UART3_RX_DATA,I2C3_SCL,,KPP_COL5,PWM1_OUT" line.long 0x04 "SW_MUX_CTL_PAD_GPIO1_IO09,SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO9,SD1_LCTL,CCM_ENET_PHY_REF_CLK,UART3_TX_DATA,I2C3_SDA,CCM_PMIC_READY,KPP_ROW5,PWM2_OUT" line.long 0x08 "SW_MUX_CTL_PAD_GPIO1_IO10,SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO10,SD2_LCTL,ENET1_MDIO,UART3_RTS_B,I2C4_SCL,FLEXTIMER1_PHA,KPP_COL6,PWM3_OUT" line.long 0x0C "SW_MUX_CTL_PAD_GPIO1_IO11,SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO11,SD3_LCTL,ENET1_MDC,UART3_CTS_B,I2C4_SDA,FLEXTIMER1_PHB,KPP_ROW6,PWM4_OUT" line.long 0x10 "SW_MUX_CTL_PAD_GPIO1_IO12,SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO12,SD2_VSELECT,CCM_ENET1_REF_CLK,FLEXCAN1_RX,CM4_NMI,CCM_EXT_CLK1,SNVS_VIO_5,USB_OTG1_ID" line.long 0x14 "SW_MUX_CTL_PAD_GPIO1_IO13,SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO13,SD3_VSELECT,CCM_ENET2_REF_CLK,FLEXCAN1_TX,CCM_PMIC_READY,CCM_EXT_CLK2,SNVS_VIO_5_CTL,USB_OTG2_ID" line.long 0x18 "SW_MUX_CTL_PAD_GPIO1_IO14,SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO14,SD3_CD_B,ENET2_MDIO,FLEXCAN2_RX,WDOG3_WDOG_B,CCM_EXT_CLK3,SDMA_EXT_EVENT0,?..." line.long 0x1C "SW_MUX_CTL_PAD_GPIO1_IO15,SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "GPIO1_IO15,SD3_WP,ENET2_MDC,FLEXCAN2_TX,WDOG4_WDOG_B,CCM_EXT_CLK4,SDMA_EXT_EVENT1,?..." line.long 0x20 "SW_MUX_CTL_PAD_EPDC_DATA00,SW_MUX_CTL_PAD_EPDC_DATA00 SW MUX Control Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA0,SIM1_PORT2_TRXD,QSPI_A_DATA0,KPP_ROW3,EIM_AD0,GPIO2_IO0,LCD_DATA0,LCD_CLK" line.long 0x24 "SW_MUX_CTL_PAD_EPDC_DATA01,SW_MUX_CTL_PAD_EPDC_DATA01 SW MUX Control Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA1,SIM1_PORT2_CLK,QSPI_A_DATA1,KPP_COL3,EIM_AD1,GPIO2_IO1,LCD_DATA1,LCD_ENABLE" line.long 0x28 "SW_MUX_CTL_PAD_EPDC_DATA02,SW_MUX_CTL_PAD_EPDC_DATA02 SW MUX Control Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA2,SIM1_PORT2_RST_B,QSPI_A_DATA2,KPP_ROW2,EIM_AD2,GPIO2_IO2,LCD_DATA2,LCD_VSYNC" line.long 0x2C "SW_MUX_CTL_PAD_EPDC_DATA03,SW_MUX_CTL_PAD_EPDC_DATA03 SW MUX Control Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA3,SIM1_PORT2_SVEN,QSPI_A_DATA3,KPP_COL2,EIM_AD3,GPIO2_IO3,LCD_DATA3,LCD_HSYNC" line.long 0x30 "SW_MUX_CTL_PAD_EPDC_DATA04,SW_MUX_CTL_PAD_EPDC_DATA04 SW MUX Control Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA4,SIM1_PORT2_PD,QSPI_A_DQS,KPP_ROW1,EIM_AD4,GPIO2_IO4,LCD_DATA4,JTAG_FAIL" line.long 0x34 "SW_MUX_CTL_PAD_EPDC_DATA05,SW_MUX_CTL_PAD_EPDC_DATA05 SW MUX Control Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA5,SIM2_PORT2_TRXD,QSPI_A_SCLK,KPP_COL1,EIM_AD5,GPIO2_IO5,LCD_DATA5,JTAG_ACTIVE" line.long 0x38 "SW_MUX_CTL_PAD_EPDC_DATA06,SW_MUX_CTL_PAD_EPDC_DATA06 SW MUX Control Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA6,SIM2_PORT2_CLK,QSPI_A_SS0_B,KPP_ROW0,EIM_AD6,GPIO2_IO6,LCD_DATA6,JTAG_DE_B" line.long 0x3C "SW_MUX_CTL_PAD_EPDC_DATA07,SW_MUX_CTL_PAD_EPDC_DATA07 SW MUX Control Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA7,SIM2_PORT2_RST_B,QSPI_A_SS1_B,KPP_COL0,EIM_AD7,GPIO2_IO7,LCD_DATA7,JTAG_DONE" line.long 0x40 "SW_MUX_CTL_PAD_EPDC_DATA08,SW_MUX_CTL_PAD_EPDC_DATA08 SW MUX Control Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA8,SIM1_PORT1_TRXD,QSPI_B_DATA0,UART6_RX_DATA,EIM_OE,GPIO2_IO8,LCD_DATA8,LCD_BUSY,EPDC_SDCLK,?..." line.long 0x44 "SW_MUX_CTL_PAD_EPDC_DATA09,SW_MUX_CTL_PAD_EPDC_DATA09 SW MUX Control Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA9,SIM1_PORT1_CLK,QSPI_B_DATA1,UART6_TX_DATA,EIM_RW,GPIO2_IO9,LCD_DATA9,LCD_DATA0,EPDC_SDLE,?..." line.long 0x48 "SW_MUX_CTL_PAD_EPDC_DATA10,SW_MUX_CTL_PAD_EPDC_DATA10 SW MUX Control Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA10,SIM1_PORT1_RST_B,QSPI_B_DATA2,UART6_RTS_B,EIM_CS0_B,GPIO2_IO10,LCD_DATA10,LCD_DATA9,EPDC_SDOE,?..." line.long 0x4C "SW_MUX_CTL_PAD_EPDC_DATA11,SW_MUX_CTL_PAD_EPDC_DATA11 SW MUX Control Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA11,SIM1_PORT1_SVEN,QSPI_B_DATA3,UART6_CTS_B,EIM_BCLK,GPIO2_IO11,LCD_DATA11,LCD_DATA1,EPDC_SDCE0,?..." line.long 0x50 "SW_MUX_CTL_PAD_EPDC_DATA12,SW_MUX_CTL_PAD_EPDC_DATA12 SW MUX Control Register" bitfld.long 0x50 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x50 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA12,SIM1_PORT1_PD,QSPI_B_DQS,UART7_RX_DATA,EIM_LBA_B,GPIO2_IO12,LCD_DATA12,LCD_DATA21,EPDC_GDCLK,?..." line.long 0x54 "SW_MUX_CTL_PAD_EPDC_DATA13,SW_MUX_CTL_PAD_EPDC_DATA13 SW MUX Control Register" bitfld.long 0x54 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x54 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA13,SIM2_PORT1_TRXD,QSPI_B_SCLK,UART7_TX_DATA,EIM_WAIT,GPIO2_IO13,LCD_DATA13,LCD_CS,EPDC_GDOE,?..." line.long 0x58 "SW_MUX_CTL_PAD_EPDC_DATA14,SW_MUX_CTL_PAD_EPDC_DATA14 SW MUX Control Register" bitfld.long 0x58 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x58 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA14,SIM2_PORT1_CLK,QSPI_B_SS0_B,UART7_RTS_B,EIM_EB_B0,GPIO2_IO14,LCD_DATA14,LCD_DATA22,EPDC_GDSP,?..." line.long 0x5C "SW_MUX_CTL_PAD_EPDC_DATA15,SW_MUX_CTL_PAD_EPDC_DATA15 SW MUX Control Register" bitfld.long 0x5C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x5C 0.--3. " MUX_MODE ,MUX mode select field" "EPDC_DATA15,SIM2_PORT1_RST_B,QSPI_B_SS1_B,UART7_CTS_B,EIM_CS1_B,GPIO2_IO15,LCD_DATA15,LCD_WR_RWN,EPDC_PWR_COM,?..." line.long 0x60 "SW_MUX_CTL_PAD_EPDC_SDCLK,SW_MUX_CTL_PAD_EPDC_SDCLK SW MUX Control Register" bitfld.long 0x60 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x60 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCLK,SIM2_PORT2_SVEN,ENET2_RGMII_RD0,KPP_ROW4,EIM_AD10,GPIO2_IO16,LCD_CLK,LCD_DATA20" line.long 0x64 "SW_MUX_CTL_PAD_EPDC_SDLE,SW_MUX_CTL_PAD_EPDC_SDLE SW MUX Control Register" bitfld.long 0x64 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x64 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDLE,SIM2_PORT2_PD,ENET2_RGMII_RD1,KPP_COL4,EIM_AD11,GPIO2_IO17,LCD_DATA16,LCD_DATA8" line.long 0x68 "SW_MUX_CTL_PAD_EPDC_SDOE,SW_MUX_CTL_PAD_EPDC_SDOE SW MUX Control Register" bitfld.long 0x68 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x68 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDOE,FLEXTIMER1_CH0,ENET2_RGMII_RD2,KPP_COL5,EIM_AD12,GPIO2_IO18,LCD_DATA17,LCD_DATA23" line.long 0x6C "SW_MUX_CTL_PAD_EPDC_SDSHR,SW_MUX_CTL_PAD_EPDC_SDSHR SW MUX Control Register" bitfld.long 0x6C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x6C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDSHR,FLEXTIMER1_CH1,ENET2_RGMII_RD3,KPP_ROW5,EIM_AD13,GPIO2_IO19,LCD_DATA18,LCD_DATA10" line.long 0x70 "SW_MUX_CTL_PAD_EPDC_SDCE0,SW_MUX_CTL_PAD_EPDC_SDCE0 SW MUX Control Register" bitfld.long 0x70 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x70 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE0,FLEXTIMER1_CH2,ENET2_RGMII_RX_CTL,,EIM_AD14,GPIO2_IO20,LCD_DATA19,LCD_DATA5" line.long 0x74 "SW_MUX_CTL_PAD_EPDC_SDCE1,SW_MUX_CTL_PAD_EPDC_SDCE1 SW MUX Control Register" bitfld.long 0x74 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x74 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE1,FLEXTIMER1_CH3,ENET2_RGMII_RXC,ENET2_RX_ER,EIM_AD15,GPIO2_IO21,LCD_DATA20,LCD_DATA4" line.long 0x78 "SW_MUX_CTL_PAD_EPDC_SDCE2,SW_MUX_CTL_PAD_EPDC_SDCE2 SW MUX Control Register" bitfld.long 0x78 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x78 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE2,SIM2_PORT1_SVEN,ENET2_RGMII_TD0,KPP_COL6,EIM_ADDR16,GPIO2_IO22,LCD_DATA21,LCD_DATA3" line.long 0x7C "SW_MUX_CTL_PAD_EPDC_SDCE3,SW_MUX_CTL_PAD_EPDC_SDCE3 SW MUX Control Register" bitfld.long 0x7C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x7C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE3,SIM2_PORT1_PD,ENET2_RGMII_TD1,KPP_ROW6,EIM_ADDR17,GPIO2_IO23,LCD_DATA22,LCD_DATA2" line.long 0x80 "SW_MUX_CTL_PAD_EPDC_GDCLK,SW_MUX_CTL_PAD_EPDC_GDCLK SW MUX Control Register" bitfld.long 0x80 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x80 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDCLK,FLEXTIMER2_CH0,ENET2_RGMII_TD2,KPP_COL7,EIM_ADDR18,GPIO2_IO24,LCD_DATA23,LCD_DATA16" line.long 0x84 "SW_MUX_CTL_PAD_EPDC_GDOE,SW_MUX_CTL_PAD_EPDC_GDOE SW MUX Control Register" bitfld.long 0x84 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x84 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDOE,FLEXTIMER2_CH1,ENET2_RGMII_TD3,KPP_ROW7,EIM_ADDR19,GPIO2_IO25,LCD_WR_RWN,LCD_DATA18" line.long 0x88 "SW_MUX_CTL_PAD_EPDC_GDRL,SW_MUX_CTL_PAD_EPDC_GDRL SW MUX Control Register" bitfld.long 0x88 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x88 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDRL,FLEXTIMER2_CH2,ENET2_RGMII_TX_CTL,,EIM_ADDR20,GPIO2_IO26,LCD_RD_E,LCD_DATA19" line.long 0x8C "SW_MUX_CTL_PAD_EPDC_GDSP,SW_MUX_CTL_PAD_EPDC_GDSP SW MUX Control Register" bitfld.long 0x8C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x8C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDSP,FLEXTIMER2_CH3,ENET2_RGMII_TXC,ENET2_TX_ER,EIM_ADDR21,GPIO2_IO27,LCD_BUSY,LCD_DATA17" line.long 0x90 "SW_MUX_CTL_PAD_EPDC_BDR0,SW_MUX_CTL_PAD_EPDC_BDR0 SW MUX Control Register" bitfld.long 0x90 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x90 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_BDR0,,ENET2_TX_CLK,CCM_ENET2_REF_CLK,EIM_ADDR22,GPIO2_IO28,LCD_CS,LCD_DATA7" line.long 0x94 "SW_MUX_CTL_PAD_EPDC_BDR1,SW_MUX_CTL_PAD_EPDC_BDR1 SW MUX Control Register" bitfld.long 0x94 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x94 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_BDR1,EPDC_SDCLKN,ENET2_RX_CLK,,EIM_AD8,GPIO2_IO29,LCD_ENABLE,LCD_DATA6" line.long 0x98 "SW_MUX_CTL_PAD_EPDC_PWR_COM,SW_MUX_CTL_PAD_EPDC_PWR_COM SW MUX Control Register" bitfld.long 0x98 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x98 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_COM,FLEXTIMER2_PHA,ENET2_CRS,,EIM_AD9,GPIO2_IO30,LCD_HSYNC,LCD_DATA11" line.long 0x9C "SW_MUX_CTL_PAD_EPDC_PWR_STAT,SW_MUX_CTL_PAD_EPDC_PWR_STAT SW MUX Control Register" bitfld.long 0x9C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x9C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_STAT,FLEXTIMER2_PHB,ENET2_COL,,EIM_EB_B1,GPIO2_IO31,LCD_VSYNC,LCD_DATA12" line.long 0xA0 "SW_MUX_CTL_PAD_LCD_CLK,SW_MUX_CTL_PAD_LCD_CLK SW MUX Control Register" bitfld.long 0xA0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_CLK,ECSPI4_MISO,ENET1_1588_EVENT2_IN,CSI_DATA16,UART2_RX_DATA,GPIO3_IO0,?..." line.long 0xA4 "SW_MUX_CTL_PAD_LCD_ENABLE,SW_MUX_CTL_PAD_LCD_ENABLE SW MUX Control Register" bitfld.long 0xA4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_ENABLE,ECSPI4_MOSI,ENET1_1588_EVENT3_IN,CSI_DATA17,UART2_TX_DATA,GPIO3_IO1,?..." line.long 0xA8 "SW_MUX_CTL_PAD_LCD_HSYNC,SW_MUX_CTL_PAD_LCD_HSYNC SW MUX Control Register" bitfld.long 0xA8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xA8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_HSYNC,ECSPI4_SCLK,ENET2_1588_EVENT2_IN,CSI_DATA18,UART2_RTS_B,GPIO3_IO2,?..." line.long 0xAC "SW_MUX_CTL_PAD_LCD_VSYNC,SW_MUX_CTL_PAD_LCD_VSYNC SW MUX Control Register" bitfld.long 0xAC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xAC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_VSYNC,ECSPI4_SS0,ENET2_1588_EVENT3_IN,CSI_DATA19,UART2_CTS_B,GPIO3_IO3,?..." line.long 0xB0 "SW_MUX_CTL_PAD_LCD_RESET,SW_MUX_CTL_PAD_LCD_RESET SW MUX Control Register" bitfld.long 0xB0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_RESET,GPT1_COMPARE1,ARM_PLATFORM_EVENTI,CSI_FIELD,EIM_DTACK_B,GPIO3_IO4,?..." line.long 0xB4 "SW_MUX_CTL_PAD_LCD_DATA00,SW_MUX_CTL_PAD_LCD_DATA00 SW MUX Control Register" bitfld.long 0xB4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA0,GPT1_COMPARE2,,CSI_DATA20,EIM_DATA0,GPIO3_IO5,SRC_BOOT_CFG0,?..." line.long 0xB8 "SW_MUX_CTL_PAD_LCD_DATA01,SW_MUX_CTL_PAD_LCD_DATA01 SW MUX Control Register" bitfld.long 0xB8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xB8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA1,GPT1_COMPARE3,,CSI_DATA21,EIM_DATA1,GPIO3_IO6,SRC_BOOT_CFG1,?..." line.long 0xBC "SW_MUX_CTL_PAD_LCD_DATA02,SW_MUX_CTL_PAD_LCD_DATA02 SW MUX Control Register" bitfld.long 0xBC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xBC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA2,GPT1_CLK,,CSI_DATA22,EIM_DATA2,GPIO3_IO7,SRC_BOOT_CFG2,?..." line.long 0xC0 "SW_MUX_CTL_PAD_LCD_DATA03,SW_MUX_CTL_PAD_LCD_DATA03 SW MUX Control Register" bitfld.long 0xC0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA3,GPT1_CAPTURE1,,CSI_DATA23,EIM_DATA3,GPIO3_IO8,SRC_BOOT_CFG3,?..." line.long 0xC4 "SW_MUX_CTL_PAD_LCD_DATA04,SW_MUX_CTL_PAD_LCD_DATA04 SW MUX Control Register" bitfld.long 0xC4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA4,GPT1_CAPTURE2,,CSI_VSYNC,EIM_DATA4,GPIO3_IO9,SRC_BOOT_CFG4,?..." line.long 0xC8 "SW_MUX_CTL_PAD_LCD_DATA05,SW_MUX_CTL_PAD_LCD_DATA05 SW MUX Control Register" bitfld.long 0xC8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xC8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA5,,,CSI_HSYNC,EIM_DATA5,GPIO3_IO10,SRC_BOOT_CFG5,?..." line.long 0xCC "SW_MUX_CTL_PAD_LCD_DATA06,SW_MUX_CTL_PAD_LCD_DATA06 SW MUX Control Register" bitfld.long 0xCC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xCC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA6,,,CSI_PIXCLK,EIM_DATA6,GPIO3_IO11,SRC_BOOT_CFG6,?..." line.long 0xD0 "SW_MUX_CTL_PAD_LCD_DATA07,SW_MUX_CTL_PAD_LCD_DATA07 SW MUX Control Register" bitfld.long 0xD0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA7,,,CSI_MCLK,EIM_DATA7,GPIO3_IO12,SRC_BOOT_CFG7,?..." line.long 0xD4 "SW_MUX_CTL_PAD_LCD_DATA08,SW_MUX_CTL_PAD_LCD_DATA08 SW MUX Control Register" bitfld.long 0xD4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA8,,,CSI_DATA9,EIM_DATA8,GPIO3_IO13,SRC_BOOT_CFG8,?..." line.long 0xD8 "SW_MUX_CTL_PAD_LCD_DATA09,SW_MUX_CTL_PAD_LCD_DATA09 SW MUX Control Register" bitfld.long 0xD8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xD8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA9,,,CSI_DATA8,EIM_DATA9,GPIO3_IO14,SRC_BOOT_CFG9,?..." line.long 0xDC "SW_MUX_CTL_PAD_LCD_DATA10,SW_MUX_CTL_PAD_LCD_DATA10 SW MUX Control Register" bitfld.long 0xDC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xDC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA10,,,CSI_DATA7,EIM_DATA10,GPIO3_IO15,SRC_BOOT_CFG10,?..." line.long 0xE0 "SW_MUX_CTL_PAD_LCD_DATA11,SW_MUX_CTL_PAD_LCD_DATA11 SW MUX Control Register" bitfld.long 0xE0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA11,,,CSI_DATA6,EIM_DATA11,GPIO3_IO16,SRC_BOOT_CFG11,?..." line.long 0xE4 "SW_MUX_CTL_PAD_LCD_DATA12,SW_MUX_CTL_PAD_LCD_DATA12 SW MUX Control Register" bitfld.long 0xE4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA12,,,CSI_DATA5,EIM_DATA12,GPIO3_IO17,SRC_BOOT_CFG12,?..." line.long 0xE8 "SW_MUX_CTL_PAD_LCD_DATA13,SW_MUX_CTL_PAD_LCD_DATA13 SW MUX Control Register" bitfld.long 0xE8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xE8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA13,,,CSI_DATA4,EIM_DATA13,GPIO3_IO18,SRC_BOOT_CFG13,?..." line.long 0xEC "SW_MUX_CTL_PAD_LCD_DATA14,SW_MUX_CTL_PAD_LCD_DATA14 SW MUX Control Register" bitfld.long 0xEC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xEC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA14,,,CSI_DATA3,EIM_DATA14,GPIO3_IO19,SRC_BOOT_CFG14,?..." line.long 0xF0 "SW_MUX_CTL_PAD_LCD_DATA15,SW_MUX_CTL_PAD_LCD_DATA15 SW MUX Control Register" bitfld.long 0xF0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF0 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA15,,,CSI_DATA2,EIM_DATA15,GPIO3_IO20,SRC_BOOT_CFG15,?..." line.long 0xF4 "SW_MUX_CTL_PAD_LCD_DATA16,SW_MUX_CTL_PAD_LCD_DATA16 SW MUX Control Register" bitfld.long 0xF4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF4 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA16,FLEXTIMER1_CH4,,CSI_DATA1,EIM_CRE,GPIO3_IO21,SRC_BOOT_CFG16,?..." line.long 0xF8 "SW_MUX_CTL_PAD_LCD_DATA17,SW_MUX_CTL_PAD_LCD_DATA17 SW MUX Control Register" bitfld.long 0xF8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xF8 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA17,FLEXTIMER1_CH5,,CSI_DATA0,EIM_ACLK_FREERUN,GPIO3_IO22,SRC_BOOT_CFG17,?..." line.long 0xFC "SW_MUX_CTL_PAD_LCD_DATA18,SW_MUX_CTL_PAD_LCD_DATA18 SW MUX Control Register" bitfld.long 0xFC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0xFC 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA18,FLEXTIMER1_CH6,ARM_PLATFORM_EVENTO,CSI_DATA15,EIM_CS2_B,GPIO3_IO23,SRC_BOOT_CFG18,?..." line.long 0x100 "SW_MUX_CTL_PAD_LCD_DATA19,SW_MUX_CTL_PAD_LCD_DATA19 SW MUX Control Register" bitfld.long 0x100 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x100 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA19,FLEXTIMER1_CH7,,CSI_DATA14,EIM_CS3_B,GPIO3_IO24,SRC_BOOT_CFG19,?..." line.long 0x104 "SW_MUX_CTL_PAD_LCD_DATA20,SW_MUX_CTL_PAD_LCD_DATA20 SW MUX Control Register" bitfld.long 0x104 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x104 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA20,FLEXTIMER2_CH4,ENET1_1588_EVENT2_OUT,CSI_DATA13,EIM_ADDR23,GPIO3_IO25,I2C3_SCL,?..." line.long 0x108 "SW_MUX_CTL_PAD_LCD_DATA21,SW_MUX_CTL_PAD_LCD_DATA21 SW MUX Control Register" bitfld.long 0x108 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x108 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA21,FLEXTIMER2_CH5,ENET1_1588_EVENT3_OUT,CSI_DATA12,EIM_ADDR24,GPIO3_IO26,I2C3_SDA,?..." line.long 0x10C "SW_MUX_CTL_PAD_LCD_DATA22,SW_MUX_CTL_PAD_LCD_DATA22 SW MUX Control Register" bitfld.long 0x10C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA22,FLEXTIMER2_CH6,ENET2_1588_EVENT2_OUT,CSI_DATA11,EIM_ADDR25,GPIO3_IO27,I2C4_SCL,?..." line.long 0x110 "SW_MUX_CTL_PAD_LCD_DATA23,SW_MUX_CTL_PAD_LCD_DATA23 SW MUX Control Register" bitfld.long 0x110 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x110 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA23,FLEXTIMER2_CH7,ENET2_1588_EVENT3_OUT,CSI_DATA10,EIM_ADDR26,GPIO3_IO28,I2C4_SDA,?..." line.long 0x114 "SW_MUX_CTL_PAD_UART1_RX_DATA,SW_MUX_CTL_PAD_UART1_RX_DATA SW MUX Control Register" bitfld.long 0x114 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x114 0.--2. " MUX_MODE ,MUX mode select field" "UART1_RX_DATA,I2C1_SCL,CCM_PMIC_READY,ECSPI1_SS1,ENET2_1588_EVENT0_IN,GPIO4_IO0,ENET1_MDIO,?..." line.long 0x118 "SW_MUX_CTL_PAD_UART1_TX_DATA,SW_MUX_CTL_PAD_UART1_TX_DATA SW MUX Control Register" bitfld.long 0x118 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x118 0.--2. " MUX_MODE ,MUX mode select field" "UART1_TX_DATA,I2C1_SDA,SAI3_MCLK,ECSPI1_SS2,ENET2_1588_EVENT0_OUT,GPIO4_IO1,ENET1_MDC,?..." line.long 0x11C "SW_MUX_CTL_PAD_UART2_RX_DATA,SW_MUX_CTL_PAD_UART2_RX_DATA SW MUX Control Register" bitfld.long 0x11C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x11C 0.--2. " MUX_MODE ,MUX mode select field" "UART2_RX_DATA,I2C2_SCL,SAI3_RX_BCLK,ECSPI1_SS3,ENET2_1588_EVENT1_IN,GPIO4_IO2,ENET2_MDIO,?..." line.long 0x120 "SW_MUX_CTL_PAD_UART2_TX_DATA,SW_MUX_CTL_PAD_UART2_TX_DATA SW MUX Control Register" bitfld.long 0x120 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x120 0.--2. " MUX_MODE ,MUX mode select field" "UART2_TX_DATA,I2C2_SDA,SAI3_RX_DATA0,ECSPI1_RDY,ENET2_1588_EVENT1_OUT,GPIO4_IO3,ENET2_MDC,?..." line.long 0x124 "SW_MUX_CTL_PAD_UART3_RX_DATA,SW_MUX_CTL_PAD_UART3_RX_DATA SW MUX Control Register" bitfld.long 0x124 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x124 0.--2. " MUX_MODE ,MUX mode select field" "UART3_RX_DATA,USB_OTG1_OC,SAI3_RX_SYNC,ECSPI1_MISO,ENET1_1588_EVENT0_IN,GPIO4_IO4,SD1_LCTL,?..." line.long 0x128 "SW_MUX_CTL_PAD_UART3_TX_DATA,SW_MUX_CTL_PAD_UART3_TX_DATA SW MUX Control Register" bitfld.long 0x128 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x128 0.--2. " MUX_MODE ,MUX mode select field" "UART3_TX_DATA,USB_OTG1_PWR,SAI3_TX_BCLK,ECSPI1_MOSI,ENET1_1588_EVENT0_OUT,GPIO4_IO5,SD2_LCTL,?..." line.long 0x12C "SW_MUX_CTL_PAD_UART3_RTS_B,SW_MUX_CTL_PAD_UART3_RTS_B SW MUX Control Register" bitfld.long 0x12C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x12C 0.--2. " MUX_MODE ,MUX mode select field" "UART3_RTS_B,USB_OTG2_OC,SAI3_TX_DATA0,ECSPI1_SCLK,ENET1_1588_EVENT1_IN,GPIO4_IO6,SD3_LCTL,?..." line.long 0x130 "SW_MUX_CTL_PAD_UART3_CTS_B,SW_MUX_CTL_PAD_UART3_CTS_B SW MUX Control Register" bitfld.long 0x130 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x130 0.--2. " MUX_MODE ,MUX mode select field" "UART3_CTS_B,USB_OTG2_PWR,SAI3_TX_SYNC,ECSPI1_SS0,ENET1_1588_EVENT1_OUT,GPIO4_IO7,SD1_VSELECT,?..." line.long 0x134 "SW_MUX_CTL_PAD_I2C1_SCL,SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register" bitfld.long 0x134 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x134 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SCL,UART4_CTS_B,FLEXCAN1_RX,ECSPI3_MISO,,GPIO4_IO8,SD2_VSELECT,?..." line.long 0x138 "SW_MUX_CTL_PAD_I2C1_SDA,SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register" bitfld.long 0x138 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x138 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SDA,UART4_RTS_B,FLEXCAN1_TX,ECSPI3_MOSI,CCM_ENET1_REF_CLK,GPIO4_IO9,SD3_VSELECT,?..." line.long 0x13C "SW_MUX_CTL_PAD_I2C2_SCL,SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register" bitfld.long 0x13C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x13C 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SCL,UART4_RX_DATA,WDOG3_WDOG_B,ECSPI3_SCLK,CCM_ENET2_REF_CLK,GPIO4_IO10,SD3_CD_B,?..." line.long 0x140 "SW_MUX_CTL_PAD_I2C2_SDA,SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register" bitfld.long 0x140 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x140 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SDA,UART4_TX_DATA,WDOG3_WDOG_RST_B_DEB,ECSPI3_SS0,CCM_ENET_PHY_REF_CLK,GPIO4_IO11,SD3_WP,?..." line.long 0x144 "SW_MUX_CTL_PAD_I2C3_SCL,SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register" bitfld.long 0x144 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x144 0.--2. " MUX_MODE ,MUX mode select field" "I2C3_SCL,UART5_CTS_B,FLEXCAN2_RX,CSI_VSYNC,SDMA_EXT_EVENT0,GPIO4_IO12,EPDC_BDR0,?..." line.long 0x148 "SW_MUX_CTL_PAD_I2C3_SDA,SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register" bitfld.long 0x148 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x148 0.--2. " MUX_MODE ,MUX mode select field" "I2C3_SDA,UART5_RTS_B,FLEXCAN2_TX,CSI_HSYNC,SDMA_EXT_EVENT1,GPIO4_IO13,EPDC_BDR1,?..." line.long 0x14C "SW_MUX_CTL_PAD_I2C4_SCL,SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register" bitfld.long 0x14C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14C 0.--2. " MUX_MODE ,MUX mode select field" "I2C4_SCL,UART5_RX_DATA,WDOG4_WDOG_B,CSI_PIXCLK,USB_OTG1_ID,GPIO4_IO14,EPDC_VCOM0,?..." line.long 0x150 "SW_MUX_CTL_PAD_I2C4_SDA,SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register" bitfld.long 0x150 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x150 0.--2. " MUX_MODE ,MUX mode select field" "I2C4_SDA,UART5_TX_DATA,WDOG4_WDOG_RST_B_DEB,CSI_MCLK,USB_OTG2_ID,GPIO4_IO15,EPDC_VCOM1,?..." line.long 0x154 "SW_MUX_CTL_PAD_ECSPI1_SCLK,SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register" bitfld.long 0x154 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x154 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SCLK,UART6_RX_DATA,SD2_DATA4,CSI_DATA2,,GPIO4_IO16,EPDC_PWR_COM,?..." line.long 0x158 "SW_MUX_CTL_PAD_ECSPI1_MOSI,SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register" bitfld.long 0x158 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x158 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MOSI,UART6_TX_DATA,SD2_DATA5,CSI_DATA3,,GPIO4_IO17,EPDC_PWR_STAT,?..." line.long 0x15C "SW_MUX_CTL_PAD_ECSPI1_MISO,SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register" bitfld.long 0x15C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x15C 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MISO,UART6_RTS_B,SD2_DATA6,CSI_DATA4,,GPIO4_IO18,EPDC_PWR_IRQ,?..." line.long 0x160 "SW_MUX_CTL_PAD_ECSPI1_SS0,SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register" bitfld.long 0x160 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x160 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SS0,UART6_CTS_B,SD2_DATA7,CSI_DATA5,,GPIO4_IO19,EPDC_PWR_CTRL3,?..." line.long 0x164 "SW_MUX_CTL_PAD_ECSPI2_SCLK,SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register" bitfld.long 0x164 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x164 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SCLK,UART7_RX_DATA,SD1_DATA4,CSI_DATA6,LCD_DATA13,GPIO4_IO20,EPDC_PWR_CTRL0,?..." line.long 0x168 "SW_MUX_CTL_PAD_ECSPI2_MOSI,SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register" bitfld.long 0x168 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x168 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MOSI,UART7_TX_DATA,SD1_DATA5,CSI_DATA7,LCD_DATA14,GPIO4_IO21,EPDC_PWR_CTRL1,?..." line.long 0x16C "SW_MUX_CTL_PAD_ECSPI2_MISO,SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register" bitfld.long 0x16C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x16C 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MISO,UART7_RTS_B,SD1_DATA6,CSI_DATA8,LCD_DATA15,GPIO4_IO22,EPDC_PWR_CTRL2,?..." line.long 0x170 "SW_MUX_CTL_PAD_ECSPI2_SS0,SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register" bitfld.long 0x170 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x170 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SS0,UART7_CTS_B,SD1_DATA7,CSI_DATA9,LCD_RESET,GPIO4_IO23,EPDC_PWR_WAKE,?..." line.long 0x174 "SW_MUX_CTL_PAD_SD1_CD_B,SW_MUX_CTL_PAD_SD1_CD_B SW MUX Control Register" bitfld.long 0x174 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x174 0.--2. " MUX_MODE ,MUX mode select field" "SD1_CD_B,,UART6_RX_DATA,ECSPI4_MISO,FLEXTIMER1_CH0,GPIO5_IO0,CCM_CLKO1,?..." line.long 0x178 "SW_MUX_CTL_PAD_SD1_WP,SW_MUX_CTL_PAD_SD1_WP SW MUX Control Register" bitfld.long 0x178 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x178 0.--2. " MUX_MODE ,MUX mode select field" "SD1_WP,,UART6_TX_DATA,ECSPI4_MOSI,FLEXTIMER1_CH1,GPIO5_IO1,CCM_CLKO2,?..." line.long 0x17C "SW_MUX_CTL_PAD_SD1_RESET_B,SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register" bitfld.long 0x17C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x17C 0.--2. " MUX_MODE ,MUX mode select field" "SD1_RESET_B,SAI3_MCLK,UART6_RTS_B,ECSPI4_SCLK,FLEXTIMER1_CH2,GPIO5_IO2,?..." line.long 0x180 "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register" bitfld.long 0x180 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x180 0.--2. " MUX_MODE ,MUX mode select field" "SD1_CLK,SAI3_RX_SYNC,UART6_CTS_B,ECSPI4_SS0,FLEXTIMER1_CH3,GPIO5_IO3,?..." line.long 0x184 "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register" bitfld.long 0x184 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x184 0.--2. " MUX_MODE ,MUX mode select field" "SD1_CMD,SAI3_RX_BCLK,,ECSPI4_SS1,FLEXTIMER2_CH0,GPIO5_IO4,?..." line.long 0x188 "SW_MUX_CTL_PAD_SD1_DATA0,SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register" bitfld.long 0x188 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x188 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA0,SAI3_RX_DATA0,UART7_RX_DATA,ECSPI4_SS2,FLEXTIMER2_CH1,GPIO5_IO5,CCM_EXT_CLK1,?..." line.long 0x18C "SW_MUX_CTL_PAD_SD1_DATA1,SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register" bitfld.long 0x18C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18C 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA1,SAI3_TX_BCLK,UART7_TX_DATA,ECSPI4_SS3,FLEXTIMER2_CH2,GPIO5_IO6,CCM_EXT_CLK2,?..." line.long 0x190 "SW_MUX_CTL_PAD_SD1_DATA2,SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register" bitfld.long 0x190 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x190 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA2,SAI3_TX_SYNC,UART7_CTS_B,ECSPI4_RDY,FLEXTIMER2_CH3,GPIO5_IO7,CCM_EXT_CLK3,?..." line.long 0x194 "SW_MUX_CTL_PAD_SD1_DATA3,SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register" bitfld.long 0x194 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x194 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA3,SAI3_TX_DATA0,UART7_RTS_B,ECSPI3_SS1,FLEXTIMER1_PHA,GPIO5_IO8,CCM_EXT_CLK4,?..." line.long 0x198 "SW_MUX_CTL_PAD_SD2_CD_B,SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register" bitfld.long 0x198 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x198 0.--2. " MUX_MODE ,MUX mode select field" "SD2_CD_B,ENET1_MDIO,ENET2_MDIO,ECSPI3_SS2,FLEXTIMER1_PHB,GPIO5_IO9,SDMA_EXT_EVENT0,?..." line.long 0x19C "SW_MUX_CTL_PAD_SD2_WP,SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register" bitfld.long 0x19C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x19C 0.--2. " MUX_MODE ,MUX mode select field" "SD2_WP,ENET1_MDC,ENET2_MDC,ECSPI3_SS3,USB_OTG1_ID,GPIO5_IO10,SDMA_EXT_EVENT1,?..." line.long 0x1A0 "SW_MUX_CTL_PAD_SD2_RESET_B,SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register" bitfld.long 0x1A0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A0 0.--2. " MUX_MODE ,MUX mode select field" "SD2_RESET_B,SAI2_MCLK,SD2_RESET,ECSPI3_RDY,USB_OTG2_ID,GPIO5_IO11,?..." line.long 0x1A4 "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register" bitfld.long 0x1A4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A4 0.--2. " MUX_MODE ,MUX mode select field" "SD2_CLK,SAI2_RX_SYNC,MQS_RIGHT,GPT4_CLK,,GPIO5_IO12,?..." line.long 0x1A8 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register" bitfld.long 0x1A8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1A8 0.--2. " MUX_MODE ,MUX mode select field" "SD2_CMD,SAI2_RX_BCLK,MQS_LEFT,GPT4_CAPTURE1,SIM2_PORT1_TRXD,GPIO5_IO13,?..." line.long 0x1AC "SW_MUX_CTL_PAD_SD2_DATA0,SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register" bitfld.long 0x1AC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1AC 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA0,SAI2_RX_DATA0,UART4_RX_DATA,GPT4_CAPTURE2,SIM2_PORT1_CLK,GPIO5_IO14,?..." line.long 0x1B0 "SW_MUX_CTL_PAD_SD2_DATA1,SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register" bitfld.long 0x1B0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B0 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA1,SAI2_TX_BCLK,UART4_TX_DATA,GPT4_COMPARE1,SIM2_PORT1_RST_B,GPIO5_IO15,?..." line.long 0x1B4 "SW_MUX_CTL_PAD_SD2_DATA2,SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register" bitfld.long 0x1B4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B4 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA2,SAI2_TX_SYNC,UART4_CTS_B,GPT4_COMPARE2,SIM2_PORT1_SVEN,GPIO5_IO16,?..." line.long 0x1B8 "SW_MUX_CTL_PAD_SD2_DATA3,SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register" bitfld.long 0x1B8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1B8 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA3,SAI2_TX_DATA0,UART4_RTS_B,GPT4_COMPARE3,SIM2_PORT1_PD,GPIO5_IO17,?..." line.long 0x1BC "SW_MUX_CTL_PAD_SD3_CLK,SW_MUX_CTL_PAD_SD3_CLK SW MUX Control Register" bitfld.long 0x1BC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1BC 0.--2. " MUX_MODE ,MUX mode select field" "SD3_CLK,NAND_CLE,ECSPI4_MISO,SAI3_RX_SYNC,GPT3_CLK,GPIO6_IO0,?..." line.long 0x1C0 "SW_MUX_CTL_PAD_SD3_CMD,SW_MUX_CTL_PAD_SD3_CMD SW MUX Control Register" bitfld.long 0x1C0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C0 0.--2. " MUX_MODE ,MUX mode select field" "SD3_CMD,NAND_ALE,ECSPI4_MOSI,SAI3_RX_BCLK,GPT3_CAPTURE1,GPIO6_IO1,?..." line.long 0x1C4 "SW_MUX_CTL_PAD_SD3_DATA0,SW_MUX_CTL_PAD_SD3_DATA0 SW MUX Control Register" bitfld.long 0x1C4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C4 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA0,NAND_DATA00,ECSPI4_SS0,SAI3_RX_DATA0,GPT3_CAPTURE2,GPIO6_IO2,?..." line.long 0x1C8 "SW_MUX_CTL_PAD_SD3_DATA1,SW_MUX_CTL_PAD_SD3_DATA1 SW MUX Control Register" bitfld.long 0x1C8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C8 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA1,NAND_DATA01,ECSPI4_SCLK,SAI3_TX_BCLK,GPT3_COMPARE1,GPIO6_IO3,?..." line.long 0x1CC "SW_MUX_CTL_PAD_SD3_DATA2,SW_MUX_CTL_PAD_SD3_DATA2 SW MUX Control Register" bitfld.long 0x1CC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1CC 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA2,NAND_DATA02,I2C3_SDA,SAI3_TX_SYNC,GPT3_COMPARE2,GPIO6_IO4,?..." line.long 0x1D0 "SW_MUX_CTL_PAD_SD3_DATA3,SW_MUX_CTL_PAD_SD3_DATA3 SW MUX Control Register" bitfld.long 0x1D0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D0 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA3,NAND_DATA03,I2C3_SCL,SAI3_TX_DATA0,GPT3_COMPARE3,GPIO6_IO5,?..." line.long 0x1D4 "SW_MUX_CTL_PAD_SD3_DATA4,SW_MUX_CTL_PAD_SD3_DATA4 SW MUX Control Register" bitfld.long 0x1D4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D4 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA4,NAND_DATA04,,UART3_RX_DATA,FLEXCAN2_RX,GPIO6_IO6,?..." line.long 0x1D8 "SW_MUX_CTL_PAD_SD3_DATA5,SW_MUX_CTL_PAD_SD3_DATA5 SW MUX Control Register" bitfld.long 0x1D8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1D8 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA5,NAND_DATA05,,UART3_TX_DATA,FLEXCAN1_TX,GPIO6_IO7,?..." line.long 0x1DC "SW_MUX_CTL_PAD_SD3_DATA6,SW_MUX_CTL_PAD_SD3_DATA6 SW MUX Control Register" bitfld.long 0x1DC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1DC 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA6,NAND_DATA06,SD3_WP,UART3_RTS_B,FLEXCAN2_TX,GPIO6_IO8,?..." line.long 0x1E0 "SW_MUX_CTL_PAD_SD3_DATA7,SW_MUX_CTL_PAD_SD3_DATA7 SW MUX Control Register" bitfld.long 0x1E0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E0 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA7,NAND_DATA07,SD3_CD_B,UART3_CTS_B,FLEXCAN1_RX,GPIO6_IO9,?..." line.long 0x1E4 "SW_MUX_CTL_PAD_SD3_STROBE,SW_MUX_CTL_PAD_SD3_STROBE SW MUX Control Register" bitfld.long 0x1E4 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E4 0.--2. " MUX_MODE ,MUX mode select field" "SD3_STROBE,NAND_RE_B,,,,GPIO6_IO10,?..." line.long 0x1E8 "SW_MUX_CTL_PAD_SD3_RESET_B,SW_MUX_CTL_PAD_SD3_RESET_B SW MUX Control Register" bitfld.long 0x1E8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1E8 0.--2. " MUX_MODE ,MUX mode select field" "SD3_RESET_B,NAND_WE_B,SD3_RESET,SAI3_MCLK,,GPIO6_IO11,?..." line.long 0x1EC "SW_MUX_CTL_PAD_SAI1_RX_DATA,SW_MUX_CTL_PAD_SAI1_RX_DATA SW MUX Control Register" bitfld.long 0x1EC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1EC 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_DATA0,NAND_CE1_B,UART5_RX_DATA,FLEXCAN1_RX,SIM1_PORT1_TRXD,GPIO6_IO12,,SRC_ANY_PU_RESET" line.long 0x1F0 "SW_MUX_CTL_PAD_SAI1_TX_BCLK,SW_MUX_CTL_PAD_SAI1_TX_BCLK SW MUX Control Register" bitfld.long 0x1F0 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1F0 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_BCLK,NAND_CE0_B,UART5_TX_DATA,FLEXCAN1_TX,SIM1_PORT1_CLK,GPIO6_IO13,,SRC_EARLY_RESET" line.long 0x1F4 "SW_MUX_CTL_PAD_SAI1_TX_SYNC,SW_MUX_CTL_PAD_SAI1_TX_SYNC SW MUX Control Register" bitfld.long 0x1F4 4. " SION ,Software input on field" "Disabled,Enabled" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x1F4 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_SYNC,NAND_DQS,UART5_CTS_B,FLEXCAN2_RX,SIM1_PORT1_RST_B,GPIO6_IO14,?..." else bitfld.long 0x1F4 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_SYNC,NAND_DQS,UART5_CTS_B,FLEXCAN2_RX,SIM1_PORT1_RST_B,GPIO6_IO14,,SRC_INT_BOOT" endif line.long 0x1F8 "SW_MUX_CTL_PAD_SAI1_TX_DATA,SW_MUX_CTL_PAD_SAI1_TX_DATA SW MUX Control Register" bitfld.long 0x1F8 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1F8 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_TX_DATA0,NAND_READY_B,UART5_RTS_B,FLEXCAN2_TX,SIM1_PORT1_SVEN,GPIO6_IO15,,SRC_SYSTEM_RESET" line.long 0x1FC "SW_MUX_CTL_PAD_SAI1_RX_SYNC,SW_MUX_CTL_PAD_SAI1_RX_SYNC SW MUX Control Register" bitfld.long 0x1FC 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1FC 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_SYNC,NAND_CE2_B,SAI2_RX_SYNC,I2C4_SCL,SIM1_PORT1_PD,GPIO6_IO16,MQS_RIGHT,SRC_CA7_RESET_B0" line.long 0x200 "SW_MUX_CTL_PAD_SAI1_RX_BCLK,SW_MUX_CTL_PAD_SAI1_RX_BCLK SW MUX Control Register" bitfld.long 0x200 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x200 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_RX_BCLK,NAND_CE3_B,SAI2_RX_BCLK,I2C4_SDA,FLEXTIMER2_PHA,GPIO6_IO17,MQS_LEFT,SRC_CA7_RESET_B1" line.long 0x204 "SW_MUX_CTL_PAD_SAI1_MCLK,SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register" bitfld.long 0x204 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x204 0.--2. " MUX_MODE ,MUX mode select field" "SAI1_MCLK,NAND_WP_B,SAI2_MCLK,CCM_PMIC_READY,FLEXTIMER2_PHB,GPIO6_IO18,,SRC_TESTER_ACK" line.long 0x208 "SW_MUX_CTL_PAD_SAI2_TX_SYNC,SW_MUX_CTL_PAD_SAI2_TX_SYNC SW MUX Control Register" bitfld.long 0x208 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x208 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_SYNC,ECSPI3_MISO,UART4_RX_DATA,UART1_CTS_B,FLEXTIMER2_CH4,GPIO6_IO19,?..." line.long 0x20C "SW_MUX_CTL_PAD_SAI2_TX_BCLK,SW_MUX_CTL_PAD_SAI2_TX_BCLK SW MUX Control Register" bitfld.long 0x20C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20C 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_BCLK,ECSPI3_MOSI,UART4_TX_DATA,UART1_RTS_B,FLEXTIMER2_CH5,GPIO6_IO20,?..." line.long 0x210 "SW_MUX_CTL_PAD_SAI2_RX_DATA,SW_MUX_CTL_PAD_SAI2_RX_DATA SW MUX Control Register" bitfld.long 0x210 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x210 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_RX_DATA0,ECSPI3_SCLK,UART4_CTS_B,UART2_CTS_B,FLEXTIMER2_CH6,GPIO6_IO21,KPP_COL7,?..." line.long 0x214 "SW_MUX_CTL_PAD_SAI2_TX_DATA,SW_MUX_CTL_PAD_SAI2_TX_DATA SW MUX Control Register" bitfld.long 0x214 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x214 0.--2. " MUX_MODE ,MUX mode select field" "SAI2_TX_DATA0,ECSPI3_SS0,UART4_RTS_B,UART2_RTS_B,FLEXTIMER2_CH7,GPIO6_IO22,KPP_ROW7,?..." line.long 0x218 "SW_MUX_CTL_PAD_ENET1_RGMII_RD0,SW_MUX_CTL_PAD_ENET1_RGMII_RD0 SW MUX Control Register" bitfld.long 0x218 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x218 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD0,PWM1_OUT,I2C3_SCL,UART1_CTS_B,EPDC_VCOM0,GPIO7_IO0,KPP_ROW3,?..." line.long 0x21C "SW_MUX_CTL_PAD_ENET1_RGMII_RD1,SW_MUX_CTL_PAD_ENET1_RGMII_RD1 SW MUX Control Register" bitfld.long 0x21C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x21C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD1,PWM2_OUT,I2C3_SDA,UART1_RTS_B,EPDC_VCOM1,GPIO7_IO1,KPP_COL3,?..." line.long 0x220 "SW_MUX_CTL_PAD_ENET1_RGMII_RD2,SW_MUX_CTL_PAD_ENET1_RGMII_RD2 SW MUX Control Register" bitfld.long 0x220 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x220 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD2,FLEXCAN1_RX,ECSPI2_SCLK,UART1_RX_DATA,EPDC_SDCE4,GPIO7_IO2,KPP_ROW2,?..." line.long 0x224 "SW_MUX_CTL_PAD_ENET1_RGMII_RD3,SW_MUX_CTL_PAD_ENET1_RGMII_RD3 SW MUX Control Register" bitfld.long 0x224 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x224 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RD3,FLEXCAN1_TX,ECSPI2_MOSI,UART1_TX_DATA,EPDC_SDCE5,GPIO7_IO3,KPP_COL2,?..." line.long 0x228 "SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL,SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL SW MUX Control Register" bitfld.long 0x228 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x228 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RX_CTL,,ECSPI2_SS1,,EPDC_SDCE6,GPIO7_IO4,KPP_ROW1,?..." line.long 0x22C "SW_MUX_CTL_PAD_ENET1_RGMII_RXC,SW_MUX_CTL_PAD_ENET1_RGMII_RXC SW MUX Control Register" bitfld.long 0x22C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x22C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_RXC,ENET1_RX_ER,ECSPI2_SS2,,EPDC_SDCE7,GPIO7_IO5,KPP_COL1,?..." line.long 0x230 "SW_MUX_CTL_PAD_ENET1_RGMII_TD0,SW_MUX_CTL_PAD_ENET1_RGMII_TD0 SW MUX Control Register" bitfld.long 0x230 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x230 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD0,PWM3_OUT,ECSPI2_SS3,,EPDC_SDCE8,GPIO7_IO6,KPP_ROW0,?..." line.long 0x234 "SW_MUX_CTL_PAD_ENET1_RGMII_TD1,SW_MUX_CTL_PAD_ENET1_RGMII_TD1 SW MUX Control Register" bitfld.long 0x234 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x234 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD1,PWM4_OUT,ECSPI2_RDY,,EPDC_SDCE9,GPIO7_IO7,KPP_COL0,?..." line.long 0x238 "SW_MUX_CTL_PAD_ENET1_RGMII_TD2,SW_MUX_CTL_PAD_ENET1_RGMII_TD2 SW MUX Control Register" bitfld.long 0x238 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x238 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD2,FLEXCAN2_RX,ECSPI2_MISO,I2C4_SCL,EPDC_SDOED,GPIO7_IO8,?..." line.long 0x23C "SW_MUX_CTL_PAD_ENET1_RGMII_TD3,SW_MUX_CTL_PAD_ENET1_RGMII_TD3 SW MUX Control Register" bitfld.long 0x23C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x23C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TD3,FLEXCAN2_TX,ECSPI2_SS0,I2C4_SDA,EPDC_SDOEZ,GPIO7_IO9,,CAAM_RNG_OSC_OBS" line.long 0x240 "SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL,SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL SW MUX Control Register" bitfld.long 0x240 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x240 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TX_CTL,,SAI1_RX_SYNC,GPT2_COMPARE1,EPDC_PWR_CTRL2,GPIO7_IO10,?..." line.long 0x244 "SW_MUX_CTL_PAD_ENET1_RGMII_TXC,SW_MUX_CTL_PAD_ENET1_RGMII_TXC SW MUX Control Register" bitfld.long 0x244 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x244 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RGMII_TXC,ENET1_TX_ER,SAI1_RX_BCLK,GPT2_COMPARE2,EPDC_PWR_CTRL3,GPIO7_IO11,?..." line.long 0x248 "SW_MUX_CTL_PAD_ENET1_TX_CLK,SW_MUX_CTL_PAD_ENET1_TX_CLK SW MUX Control Register" bitfld.long 0x248 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x248 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_TX_CLK,CCM_ENET1_REF_CLK,SAI1_RX_DATA0,GPT2_COMPARE3,EPDC_PWR_IRQ,GPIO7_IO12,CCM_EXT_CLK1,CSU_ALARM_AUT0" line.long 0x24C "SW_MUX_CTL_PAD_ENET1_RX_CLK,SW_MUX_CTL_PAD_ENET1_RX_CLK SW MUX Control Register" bitfld.long 0x24C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24C 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_RX_CLK,WDOG2_WDOG_B,SAI1_TX_BCLK,GPT2_CLK,EPDC_PWR_WAKE,GPIO7_IO13,CCM_EXT_CLK2,CSU_ALARM_AUT1" line.long 0x250 "SW_MUX_CTL_PAD_ENET1_CRS,SW_MUX_CTL_PAD_ENET1_CRS SW MUX Control Register" bitfld.long 0x250 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x250 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_CRS,WDOG2_WDOG_RST_B_DEB,SAI1_TX_SYNC,GPT2_CAPTURE1,EPDC_PWR_CTRL0,GPIO7_IO14,CCM_EXT_CLK3,CSU_ALARM_AUT2" line.long 0x254 "SW_MUX_CTL_PAD_ENET1_COL,SW_MUX_CTL_PAD_ENET1_COL SW MUX Control Register" bitfld.long 0x254 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x254 0.--2. " MUX_MODE ,MUX mode select field" "ENET1_COL,WDOG1_WDOG_ANY,SAI1_TX_DATA0,GPT2_CAPTURE2,EPDC_PWR_CTRL1,GPIO7_IO15,CCM_EXT_CLK4,CSU_INT_DEB" newline line.long 0x258 "SW_PAD_CTL_PAD_GPIO1_IO08,SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register" bitfld.long 0x258 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x258 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x258 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x258 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x258 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x25C "SW_PAD_CTL_PAD_GPIO1_IO09,SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register" bitfld.long 0x25C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x25C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x25C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x25C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x25C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x260 "SW_PAD_CTL_PAD_GPIO1_IO10,SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register" bitfld.long 0x260 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x260 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x260 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x260 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x260 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x264 "SW_PAD_CTL_PAD_GPIO1_IO11,SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register" bitfld.long 0x264 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x264 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x264 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x264 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x264 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x268 "SW_PAD_CTL_PAD_GPIO1_IO12,SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register" bitfld.long 0x268 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x268 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x268 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x268 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x268 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x26C "SW_PAD_CTL_PAD_GPIO1_IO13,SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register" bitfld.long 0x26C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x26C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x26C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x26C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x26C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x270 "SW_PAD_CTL_PAD_GPIO1_IO14,SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register" bitfld.long 0x270 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x270 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x270 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x270 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x270 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x274 "SW_PAD_CTL_PAD_GPIO1_IO15,SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register" bitfld.long 0x274 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x274 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x274 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x274 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x274 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x278 "SW_PAD_CTL_PAD_JTAG_MOD,SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register" bitfld.long 0x278 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x278 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x278 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x278 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x278 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x27C "SW_PAD_CTL_PAD_JTAG_TCK,SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register" bitfld.long 0x27C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x27C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x27C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x27C 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x27C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x280 "SW_PAD_CTL_PAD_JTAG_TDI,SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register" bitfld.long 0x280 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x280 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x280 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x280 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x280 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x284 "SW_PAD_CTL_PAD_JTAG_TDO,SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register" bitfld.long 0x284 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x284 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x284 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x284 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x284 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x288 "SW_PAD_CTL_PAD_JTAG_TMS,SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register" bitfld.long 0x288 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x288 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x288 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x288 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x288 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x28C "SW_PAD_CTL_PAD_JTAG_TRST_B,SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register" bitfld.long 0x28C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x28C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x28C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" rbitfld.long 0x28C 2. " SRE ,Slew rate field" "Fast,Slow" rbitfld.long 0x28C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x290 "SW_PAD_CTL_PAD_EPDC_DATA00,SW_PAD_CTL_PAD_EPDC_DATA00 SW PAD Control Register" bitfld.long 0x290 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x290 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x290 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x290 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x290 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x294 "SW_PAD_CTL_PAD_EPDC_DATA01,SW_PAD_CTL_PAD_EPDC_DATA01 SW PAD Control Register" bitfld.long 0x294 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x294 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x294 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x294 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x294 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x298 "SW_PAD_CTL_PAD_EPDC_DATA02,SW_PAD_CTL_PAD_EPDC_DATA02 SW PAD Control Register" bitfld.long 0x298 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x298 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x298 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x298 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x298 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x29C "SW_PAD_CTL_PAD_EPDC_DATA03,SW_PAD_CTL_PAD_EPDC_DATA03 SW PAD Control Register" bitfld.long 0x29C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x29C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x29C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x29C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x29C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2A0 "SW_PAD_CTL_PAD_EPDC_DATA04,SW_PAD_CTL_PAD_EPDC_DATA04 SW PAD Control Register" bitfld.long 0x2A0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2A0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2A0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2A0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2A0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2A4 "SW_PAD_CTL_PAD_EPDC_DATA05,SW_PAD_CTL_PAD_EPDC_DATA05 SW PAD Control Register" bitfld.long 0x2A4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2A4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2A4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2A4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2A4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2A8 "SW_PAD_CTL_PAD_EPDC_DATA06,SW_PAD_CTL_PAD_EPDC_DATA06 SW PAD Control Register" bitfld.long 0x2A8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2A8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2A8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2A8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2A8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2AC "SW_PAD_CTL_PAD_EPDC_DATA07,SW_PAD_CTL_PAD_EPDC_DATA07 SW PAD Control Register" bitfld.long 0x2AC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2AC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2AC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2AC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2AC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2B0 "SW_PAD_CTL_PAD_EPDC_DATA08,SW_PAD_CTL_PAD_EPDC_DATA08 SW PAD Control Register" bitfld.long 0x2B0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2B0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2B0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2B0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2B0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2B4 "SW_PAD_CTL_PAD_EPDC_DATA09,SW_PAD_CTL_PAD_EPDC_DATA09 SW PAD Control Register" bitfld.long 0x2B4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2B4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2B4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2B4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2B4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2B8 "SW_PAD_CTL_PAD_EPDC_DATA10,SW_PAD_CTL_PAD_EPDC_DATA10 SW PAD Control Register" bitfld.long 0x2B8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2B8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2B8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2B8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2B8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2BC "SW_PAD_CTL_PAD_EPDC_DATA11,SW_PAD_CTL_PAD_EPDC_DATA11 SW PAD Control Register" bitfld.long 0x2BC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2BC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2BC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2BC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2BC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2C0 "SW_PAD_CTL_PAD_EPDC_DATA12,SW_PAD_CTL_PAD_EPDC_DATA12 SW PAD Control Register" bitfld.long 0x2C0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2C0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2C0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2C0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2C0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2C4 "SW_PAD_CTL_PAD_EPDC_DATA13,SW_PAD_CTL_PAD_EPDC_DATA13 SW PAD Control Register" bitfld.long 0x2C4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2C4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2C4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2C4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2C4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2C8 "SW_PAD_CTL_PAD_EPDC_DATA14,SW_PAD_CTL_PAD_EPDC_DATA14 SW PAD Control Register" bitfld.long 0x2C8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2C8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2C8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2C8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2C8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2CC "SW_PAD_CTL_PAD_EPDC_DATA15,SW_PAD_CTL_PAD_EPDC_DATA15 SW PAD Control Register" bitfld.long 0x2CC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2CC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2CC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2CC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2CC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2D0 "SW_PAD_CTL_PAD_EPDC_SDCLK,SW_PAD_CTL_PAD_EPDC_SDCLK SW PAD Control Register" bitfld.long 0x2D0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2D0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2D0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2D0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2D0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2D4 "SW_PAD_CTL_PAD_EPDC_SDLE,SW_PAD_CTL_PAD_EPDC_SDLE SW PAD Control Register" bitfld.long 0x2D4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2D4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2D4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2D4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2D4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2D8 "SW_PAD_CTL_PAD_EPDC_SDOE,SW_PAD_CTL_PAD_EPDC_SDOE SW PAD Control Register" bitfld.long 0x2D8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2D8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2D8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2D8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2D8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2DC "SW_PAD_CTL_PAD_EPDC_SDSHR,SW_PAD_CTL_PAD_EPDC_SDSHR SW PAD Control Register" bitfld.long 0x2DC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2DC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2DC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2DC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2DC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2E0 "SW_PAD_CTL_PAD_EPDC_SDCE0,SW_PAD_CTL_PAD_EPDC_SDCE0 SW PAD Control Register" bitfld.long 0x2E0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2E0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2E0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2E0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2E0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2E4 "SW_PAD_CTL_PAD_EPDC_SDCE1,SW_PAD_CTL_PAD_EPDC_SDCE1 SW PAD Control Register" bitfld.long 0x2E4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2E4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2E4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2E4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2E4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2E8 "SW_PAD_CTL_PAD_EPDC_SDCE2,SW_PAD_CTL_PAD_EPDC_SDCE2 SW PAD Control Register" bitfld.long 0x2E8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2E8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2E8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2E8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2E8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2EC "SW_PAD_CTL_PAD_EPDC_SDCE3,SW_PAD_CTL_PAD_EPDC_SDCE3 SW PAD Control Register" bitfld.long 0x2EC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2EC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2EC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2EC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2EC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2F0 "SW_PAD_CTL_PAD_EPDC_GDCLK,SW_PAD_CTL_PAD_EPDC_GDCLK SW PAD Control Register" bitfld.long 0x2F0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2F0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2F0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2F0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2F0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2F4 "SW_PAD_CTL_PAD_EPDC_GDOE,SW_PAD_CTL_PAD_EPDC_GDOE SW PAD Control Register" bitfld.long 0x2F4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2F4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2F4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2F4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2F4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2F8 "SW_PAD_CTL_PAD_EPDC_GDRL,SW_PAD_CTL_PAD_EPDC_GDRL SW PAD Control Register" bitfld.long 0x2F8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2F8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2F8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2F8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2F8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x2FC "SW_PAD_CTL_PAD_EPDC_GDSP,SW_PAD_CTL_PAD_EPDC_GDSP SW PAD Control Register" bitfld.long 0x2FC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x2FC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x2FC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x2FC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x2FC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x300 "SW_PAD_CTL_PAD_EPDC_BDR0,SW_PAD_CTL_PAD_EPDC_BDR0 SW PAD Control Register" bitfld.long 0x300 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x300 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x300 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x300 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x300 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x304 "SW_PAD_CTL_PAD_EPDC_BDR1,SW_PAD_CTL_PAD_EPDC_BDR1 SW PAD Control Register" bitfld.long 0x304 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x304 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x304 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x304 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x304 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x308 "SW_PAD_CTL_PAD_EPDC_PWR_COM,SW_PAD_CTL_PAD_EPDC_PWR_COM SW PAD Control Register" bitfld.long 0x308 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x308 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x308 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x308 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x308 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x30C "SW_PAD_CTL_PAD_EPDC_PWR_STAT,SW_PAD_CTL_PAD_EPDC_PWR_STAT SW PAD Control Register" bitfld.long 0x30C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x30C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x30C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x30C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x30C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x310 "SW_PAD_CTL_PAD_LCD_CLK,SW_PAD_CTL_PAD_LCD_CLK SW PAD Control Register" bitfld.long 0x310 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x310 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x310 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x310 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x310 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x314 "SW_PAD_CTL_PAD_LCD_ENABLE,SW_PAD_CTL_PAD_LCD_ENABLE SW PAD Control Register" bitfld.long 0x314 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x314 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x314 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x314 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x314 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x318 "SW_PAD_CTL_PAD_LCD_HSYNC,SW_PAD_CTL_PAD_LCD_HSYNC SW PAD Control Register" bitfld.long 0x318 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x318 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x318 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x318 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x318 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x31C "SW_PAD_CTL_PAD_LCD_VSYNC,SW_PAD_CTL_PAD_LCD_VSYNC SW PAD Control Register" bitfld.long 0x31C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x31C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x31C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x31C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x31C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x320 "SW_PAD_CTL_PAD_LCD_RESET,SW_PAD_CTL_PAD_LCD_RESET SW PAD Control Register" bitfld.long 0x320 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x320 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x320 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x320 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x320 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x324 "SW_PAD_CTL_PAD_LCD_DATA00,SW_PAD_CTL_PAD_LCD_DATA00 SW PAD Control Register" bitfld.long 0x324 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x324 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x324 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x324 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x324 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x328 "SW_PAD_CTL_PAD_LCD_DATA01,SW_PAD_CTL_PAD_LCD_DATA01 SW PAD Control Register" bitfld.long 0x328 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x328 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x328 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x328 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x328 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x32C "SW_PAD_CTL_PAD_LCD_DATA02,SW_PAD_CTL_PAD_LCD_DATA02 SW PAD Control Register" bitfld.long 0x32C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x32C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x32C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x32C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x32C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x330 "SW_PAD_CTL_PAD_LCD_DATA03,SW_PAD_CTL_PAD_LCD_DATA03 SW PAD Control Register" bitfld.long 0x330 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x330 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x330 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x330 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x330 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x334 "SW_PAD_CTL_PAD_LCD_DATA04,SW_PAD_CTL_PAD_LCD_DATA04 SW PAD Control Register" bitfld.long 0x334 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x334 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x334 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x334 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x334 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x338 "SW_PAD_CTL_PAD_LCD_DATA05,SW_PAD_CTL_PAD_LCD_DATA05 SW PAD Control Register" bitfld.long 0x338 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x338 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x338 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x338 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x338 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x33C "SW_PAD_CTL_PAD_LCD_DATA06,SW_PAD_CTL_PAD_LCD_DATA06 SW PAD Control Register" bitfld.long 0x33C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x33C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x33C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x33C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x33C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x340 "SW_PAD_CTL_PAD_LCD_DATA07,SW_PAD_CTL_PAD_LCD_DATA07 SW PAD Control Register" bitfld.long 0x340 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x340 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x340 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x340 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x340 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x344 "SW_PAD_CTL_PAD_LCD_DATA08,SW_PAD_CTL_PAD_LCD_DATA08 SW PAD Control Register" bitfld.long 0x344 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x344 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x344 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x344 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x344 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x348 "SW_PAD_CTL_PAD_LCD_DATA09,SW_PAD_CTL_PAD_LCD_DATA09 SW PAD Control Register" bitfld.long 0x348 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x348 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x348 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x348 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x348 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x34C "SW_PAD_CTL_PAD_LCD_DATA10,SW_PAD_CTL_PAD_LCD_DATA10 SW PAD Control Register" bitfld.long 0x34C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x34C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x34C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x34C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x34C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x350 "SW_PAD_CTL_PAD_LCD_DATA11,SW_PAD_CTL_PAD_LCD_DATA11 SW PAD Control Register" bitfld.long 0x350 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x350 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x350 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x350 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x350 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x354 "SW_PAD_CTL_PAD_LCD_DATA12,SW_PAD_CTL_PAD_LCD_DATA12 SW PAD Control Register" bitfld.long 0x354 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x354 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x354 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x354 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x354 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x358 "SW_PAD_CTL_PAD_LCD_DATA13,SW_PAD_CTL_PAD_LCD_DATA13 SW PAD Control Register" bitfld.long 0x358 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x358 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x358 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x358 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x358 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x35C "SW_PAD_CTL_PAD_LCD_DATA14,SW_PAD_CTL_PAD_LCD_DATA14 SW PAD Control Register" bitfld.long 0x35C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x35C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x35C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x35C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x35C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x360 "SW_PAD_CTL_PAD_LCD_DATA15,SW_PAD_CTL_PAD_LCD_DATA15 SW PAD Control Register" bitfld.long 0x360 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x360 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x360 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x360 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x360 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x364 "SW_PAD_CTL_PAD_LCD_DATA16,SW_PAD_CTL_PAD_LCD_DATA16 SW PAD Control Register" bitfld.long 0x364 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x364 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x364 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x364 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x364 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x368 "SW_PAD_CTL_PAD_LCD_DATA17,SW_PAD_CTL_PAD_LCD_DATA17 SW PAD Control Register" bitfld.long 0x368 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x368 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x368 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x368 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x368 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x36C "SW_PAD_CTL_PAD_LCD_DATA18,SW_PAD_CTL_PAD_LCD_DATA18 SW PAD Control Register" bitfld.long 0x36C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x36C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x36C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x36C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x36C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x370 "SW_PAD_CTL_PAD_LCD_DATA19,SW_PAD_CTL_PAD_LCD_DATA19 SW PAD Control Register" bitfld.long 0x370 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x370 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x370 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x370 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x370 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x374 "SW_PAD_CTL_PAD_LCD_DATA20,SW_PAD_CTL_PAD_LCD_DATA20 SW PAD Control Register" bitfld.long 0x374 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x374 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x374 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x374 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x374 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x378 "SW_PAD_CTL_PAD_LCD_DATA21,SW_PAD_CTL_PAD_LCD_DATA21 SW PAD Control Register" bitfld.long 0x378 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x378 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x378 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x378 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x378 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x37C "SW_PAD_CTL_PAD_LCD_DATA22,SW_PAD_CTL_PAD_LCD_DATA22 SW PAD Control Register" bitfld.long 0x37C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x37C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x37C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x37C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x37C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x380 "SW_PAD_CTL_PAD_LCD_DATA23,SW_PAD_CTL_PAD_LCD_DATA23 SW PAD Control Register" bitfld.long 0x380 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x380 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x380 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x380 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x380 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x384 "SW_PAD_CTL_PAD_UART1_RX_DATA,SW_PAD_CTL_PAD_UART1_RX_DATA SW PAD Control Register" bitfld.long 0x384 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x384 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x384 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x384 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x384 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x388 "SW_PAD_CTL_PAD_UART1_TX_DATA,SW_PAD_CTL_PAD_UART1_TX_DATA SW PAD Control Register" bitfld.long 0x388 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x388 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x388 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x388 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x388 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x38C "SW_PAD_CTL_PAD_UART2_RX_DATA,SW_PAD_CTL_PAD_UART2_RX_DATA SW PAD Control Register" bitfld.long 0x38C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x38C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x38C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x38C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x38C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x390 "SW_PAD_CTL_PAD_UART2_TX_DATA,SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register" bitfld.long 0x390 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x390 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x390 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x390 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x390 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x394 "SW_PAD_CTL_PAD_UART3_RX_DATA,SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register" bitfld.long 0x394 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x394 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x394 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x394 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x394 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x398 "SW_PAD_CTL_PAD_UART3_TX_DATA,SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register" bitfld.long 0x398 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x398 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x398 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x398 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x398 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x39C "SW_PAD_CTL_PAD_UART3_RTS_B,SW_PAD_CTL_PAD_UART3_RTS_B SW PAD Control Register" bitfld.long 0x39C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x39C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x39C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x39C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x39C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3A0 "SW_PAD_CTL_PAD_UART3_CTS_B,SW_PAD_CTL_PAD_UART3_CTS_B SW PAD Control Register" bitfld.long 0x3A0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3A0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3A0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3A0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3A0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3A4 "SW_PAD_CTL_PAD_I2C1_SCL,SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register" bitfld.long 0x3A4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3A4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3A4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3A4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3A4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3A8 "SW_PAD_CTL_PAD_I2C1_SDA,SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register" bitfld.long 0x3A8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3A8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3A8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3A8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3A8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3AC "SW_PAD_CTL_PAD_I2C2_SCL,SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register" bitfld.long 0x3AC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3AC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3AC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3AC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3AC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3B0 "SW_PAD_CTL_PAD_I2C2_SDA,SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register" bitfld.long 0x3B0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3B0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3B0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3B0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3B0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3B4 "SW_PAD_CTL_PAD_I2C3_SCL,SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register" bitfld.long 0x3B4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3B4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3B4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3B4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3B4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3B8 "SW_PAD_CTL_PAD_I2C3_SDA,SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register" bitfld.long 0x3B8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3B8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3B8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3B8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3B8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3BC "SW_PAD_CTL_PAD_I2C4_SCL,SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register" bitfld.long 0x3BC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3BC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3BC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3BC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3BC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3C0 "SW_PAD_CTL_PAD_I2C4_SDA,SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register" bitfld.long 0x3C0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3C0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3C0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3C0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3C0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3C4 "SW_PAD_CTL_PAD_ECSPI1_SCLK,SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register" bitfld.long 0x3C4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3C4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3C4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3C4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3C4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3C8 "SW_PAD_CTL_PAD_ECSPI1_MOSI,SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register" bitfld.long 0x3C8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3C8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3C8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3C8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3C8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3CC "SW_PAD_CTL_PAD_ECSPI1_MISO,SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register" bitfld.long 0x3CC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3CC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3CC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3CC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3CC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3D0 "SW_PAD_CTL_PAD_ECSPI1_SS0,SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register" bitfld.long 0x3D0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3D0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3D0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3D0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3D0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3D4 "SW_PAD_CTL_PAD_ECSPI2_SCLK,SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register" bitfld.long 0x3D4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3D4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3D4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3D4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3D4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3D8 "SW_PAD_CTL_PAD_ECSPI2_MOSI,SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register" bitfld.long 0x3D8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3D8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3D8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3D8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3D8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3DC "SW_PAD_CTL_PAD_ECSPI2_MISO,SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register" bitfld.long 0x3DC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3DC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3DC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3DC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3DC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3E0 "SW_PAD_CTL_PAD_ECSPI2_SS0,SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register" bitfld.long 0x3E0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3E0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3E0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3E0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3E0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3E4 "SW_PAD_CTL_PAD_SD1_CD_B,SW_PAD_CTL_PAD_SD1_CD_B SW PAD Control Register" bitfld.long 0x3E4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3E4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3E4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3E4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3E4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3E8 "SW_PAD_CTL_PAD_SD1_WP,SW_PAD_CTL_PAD_SD1_WP SW PAD Control Register" bitfld.long 0x3E8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3E8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3E8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3E8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3E8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3EC "SW_PAD_CTL_PAD_SD1_RESET_B,SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register" bitfld.long 0x3EC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3EC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3EC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3EC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3EC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3F0 "SW_PAD_CTL_PAD_SD1_CLK,SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register" bitfld.long 0x3F0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3F0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3F0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3F0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3F0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3F4 "SW_PAD_CTL_PAD_SD1_CMD,SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register" bitfld.long 0x3F4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3F4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3F4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3F4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3F4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3F8 "SW_PAD_CTL_PAD_SD1_DATA0,SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register" bitfld.long 0x3F8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3F8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3F8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3F8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3F8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x3FC "SW_PAD_CTL_PAD_SD1_DATA1,SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register" bitfld.long 0x3FC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x3FC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x3FC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x3FC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x3FC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x400 "SW_PAD_CTL_PAD_SD1_DATA2,SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register" bitfld.long 0x400 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x400 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x400 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x400 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x400 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x404 "SW_PAD_CTL_PAD_SD1_DATA3,SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register" bitfld.long 0x404 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x404 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x404 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x404 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x404 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x408 "SW_PAD_CTL_PAD_SD2_CD_B,SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register" bitfld.long 0x408 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x408 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x408 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x408 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x408 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x40C "SW_PAD_CTL_PAD_SD2_WP,SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register" bitfld.long 0x40C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x40C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x40C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x40C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x40C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x410 "SW_PAD_CTL_PAD_SD2_RESET_B,SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register" bitfld.long 0x410 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x410 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x410 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x410 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x410 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x414 "SW_PAD_CTL_PAD_SD2_CLK,SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register" bitfld.long 0x414 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x414 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x414 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x414 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x414 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x418 "SW_PAD_CTL_PAD_SD2_CMD,SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register" bitfld.long 0x418 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x418 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x418 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x418 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x418 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x41C "SW_PAD_CTL_PAD_SD2_DATA0,SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register" bitfld.long 0x41C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x41C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x41C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x41C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x41C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x420 "SW_PAD_CTL_PAD_SD2_DATA1,SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register" bitfld.long 0x420 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x420 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x420 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x420 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x420 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x424 "SW_PAD_CTL_PAD_SD2_DATA2,SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register" bitfld.long 0x424 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x424 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x424 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x424 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x424 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x428 "SW_PAD_CTL_PAD_SD2_DATA3,SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register" bitfld.long 0x428 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x428 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x428 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x428 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x428 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x42C "SW_PAD_CTL_PAD_SD3_CLK,SW_PAD_CTL_PAD_SD3_CLK SW PAD Control Register" bitfld.long 0x42C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x42C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x42C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x42C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x42C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x430 "SW_PAD_CTL_PAD_SD3_CMD,SW_PAD_CTL_PAD_SD3_CMD SW PAD Control Register" bitfld.long 0x430 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x430 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x430 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x430 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x430 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x434 "SW_PAD_CTL_PAD_SD3_DATA0,SW_PAD_CTL_PAD_SD3_DATA0 SW PAD Control Register" bitfld.long 0x434 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x434 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x434 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x434 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x434 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x438 "SW_PAD_CTL_PAD_SD3_DATA1,SW_PAD_CTL_PAD_SD3_DATA1 SW PAD Control Register" bitfld.long 0x438 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x438 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x438 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x438 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x438 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x43C "SW_PAD_CTL_PAD_SD3_DATA2,SW_PAD_CTL_PAD_SD3_DATA2 SW PAD Control Register" bitfld.long 0x43C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x43C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x43C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x43C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x43C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x440 "SW_PAD_CTL_PAD_SD3_DATA3,SW_PAD_CTL_PAD_SD3_DATA3 SW PAD Control Register" bitfld.long 0x440 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x440 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x440 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x440 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x440 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x444 "SW_PAD_CTL_PAD_SD3_DATA4,SW_PAD_CTL_PAD_SD3_DATA4 SW PAD Control Register" bitfld.long 0x444 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x444 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x444 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x444 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x444 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x448 "SW_PAD_CTL_PAD_SD3_DATA5,SW_PAD_CTL_PAD_SD3_DATA5 SW PAD Control Register" bitfld.long 0x448 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x448 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x448 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x448 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x448 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x44C "SW_PAD_CTL_PAD_SD3_DATA6,SW_PAD_CTL_PAD_SD3_DATA6 SW PAD Control Register" bitfld.long 0x44C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x44C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x44C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x44C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x44C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x450 "SW_PAD_CTL_PAD_SD3_DATA7,SW_PAD_CTL_PAD_SD3_DATA7 SW PAD Control Register" bitfld.long 0x450 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x450 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x450 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x450 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x450 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x454 "SW_PAD_CTL_PAD_SD3_STROBE,SW_PAD_CTL_PAD_SD3_STROBE SW PAD Control Register" bitfld.long 0x454 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x454 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x454 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x454 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x454 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x458 "SW_PAD_CTL_PAD_SD3_RESET_B,SW_PAD_CTL_PAD_SD3_RESET_B SW PAD Control Register" bitfld.long 0x458 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x458 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x458 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x458 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x458 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x45C "SW_PAD_CTL_PAD_SAI1_RX_DATA,SW_PAD_CTL_PAD_SAI1_RX_DATA SW PAD Control Register" bitfld.long 0x45C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x45C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x45C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x45C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x45C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x460 "SW_PAD_CTL_PAD_SAI1_TX_BCLK,SW_PAD_CTL_PAD_SAI1_TX_BCLK SW PAD Control Register" bitfld.long 0x460 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x460 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x460 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x460 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x460 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x464 "SW_PAD_CTL_PAD_SAI1_TX_SYNC,SW_PAD_CTL_PAD_SAI1_TX_SYNC SW PAD Control Register" bitfld.long 0x464 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x464 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x464 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x464 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x464 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x468 "SW_PAD_CTL_PAD_SAI1_TX_DATA,SW_PAD_CTL_PAD_SAI1_TX_DATA SW PAD Control Register" bitfld.long 0x468 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x468 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x468 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x468 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x468 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x46C "SW_PAD_CTL_PAD_SAI1_RX_SYNC,SW_PAD_CTL_PAD_SAI1_RX_SYNC SW PAD Control Register" bitfld.long 0x46C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x46C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x46C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x46C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x46C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x470 "SW_PAD_CTL_PAD_SAI1_RX_BCLK,SW_PAD_CTL_PAD_SAI1_RX_BCLK SW PAD Control Register" bitfld.long 0x470 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x470 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x470 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x470 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x470 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x474 "SW_PAD_CTL_PAD_SAI1_MCLK,SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register" bitfld.long 0x474 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x474 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x474 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x474 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x474 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x478 "SW_PAD_CTL_PAD_SAI2_TX_SYNC,SW_PAD_CTL_PAD_SAI2_TX_SYNC SW PAD Control Register" bitfld.long 0x478 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x478 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x478 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x478 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x478 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x47C "SW_PAD_CTL_PAD_SAI2_TX_BCLK,SW_PAD_CTL_PAD_SAI2_TX_BCLK SW PAD Control Register" bitfld.long 0x47C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x47C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x47C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x47C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x47C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x480 "SW_PAD_CTL_PAD_SAI2_RX_DATA,SW_PAD_CTL_PAD_SAI2_RX_DATA SW PAD Control Register" bitfld.long 0x480 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x480 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x480 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x480 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x480 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x484 "SW_PAD_CTL_PAD_SAI2_TX_DATA,SW_PAD_CTL_PAD_SAI2_TX_DATA SW PAD Control Register" bitfld.long 0x484 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x484 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x484 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x484 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x484 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x488 "SW_PAD_CTL_PAD_ENET1_RGMII_RD0,SW_PAD_CTL_PAD_ENET1_RGMII_RD0 SW PAD Control Register" bitfld.long 0x488 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x488 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x488 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x488 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x488 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x48C "SW_PAD_CTL_PAD_ENET1_RGMII_RD1,SW_PAD_CTL_PAD_ENET1_RGMII_RD1 SW PAD Control Register" bitfld.long 0x48C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x48C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x48C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x48C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x48C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x490 "SW_PAD_CTL_PAD_ENET1_RGMII_RD2,SW_PAD_CTL_PAD_ENET1_RGMII_RD2 SW PAD Control Register" bitfld.long 0x490 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x490 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x490 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x490 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x490 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x494 "SW_PAD_CTL_PAD_ENET1_RGMII_RD3,SW_PAD_CTL_PAD_ENET1_RGMII_RD3 SW PAD Control Register" bitfld.long 0x494 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x494 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x494 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x494 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x494 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x498 "SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL,SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL SW PAD Control Register" bitfld.long 0x498 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x498 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x498 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x498 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x498 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x49C "SW_PAD_CTL_PAD_ENET1_RGMII_RXC,SW_PAD_CTL_PAD_ENET1_RGMII_RXC SW PAD Control Register" bitfld.long 0x49C 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x49C 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x49C 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x49C 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x49C 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4A0 "SW_PAD_CTL_PAD_ENET1_RGMII_TD0,SW_PAD_CTL_PAD_ENET1_RGMII_TD0 SW PAD Control Register" bitfld.long 0x4A0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4A0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4A0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4A0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4A0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4A4 "SW_PAD_CTL_PAD_ENET1_RGMII_TD1,SW_PAD_CTL_PAD_ENET1_RGMII_TD1 SW PAD Control Register" bitfld.long 0x4A4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4A4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4A4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4A4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4A4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4A8 "SW_PAD_CTL_PAD_ENET1_RGMII_TD2,SW_PAD_CTL_PAD_ENET1_RGMII_TD2 SW PAD Control Register" bitfld.long 0x4A8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4A8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4A8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4A8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4A8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4AC "SW_PAD_CTL_PAD_ENET1_RGMII_TD3,SW_PAD_CTL_PAD_ENET1_RGMII_TD3 SW PAD Control Register" bitfld.long 0x4AC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4AC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4AC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4AC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4AC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4B0 "SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL,SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL SW PAD Control Register" bitfld.long 0x4B0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4B0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4B0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4B0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4B0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4B4 "SW_PAD_CTL_PAD_ENET1_RGMII_TXC,SW_PAD_CTL_PAD_ENET1_RGMII_TXC SW PAD Control Register" bitfld.long 0x4B4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4B4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4B4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4B4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4B4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4B8 "SW_PAD_CTL_PAD_ENET1_TX_CLK,SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register" bitfld.long 0x4B8 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4B8 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4B8 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4B8 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4B8 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4BC "SW_PAD_CTL_PAD_ENET1_RX_CLK,SW_PAD_CTL_PAD_ENET1_RX_CLK SW PAD Control Register" bitfld.long 0x4BC 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4BC 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4BC 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4BC 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4BC 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4C0 "SW_PAD_CTL_PAD_ENET1_CRS,SW_PAD_CTL_PAD_ENET1_CRS SW PAD Control Register" bitfld.long 0x4C0 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4C0 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4C0 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4C0 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4C0 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" line.long 0x4C4 "SW_PAD_CTL_PAD_ENET1_COL,SW_PAD_CTL_PAD_ENET1_COL SW PAD Control Register" bitfld.long 0x4C4 5.--6. " PS ,Pull select field" "100K PD,5K PU,47K PU,100K PU" bitfld.long 0x4C4 4. " PE ,Pull enable field" "Disabled,Enabled" bitfld.long 0x4C4 3. " HYS ,Hysteresis enable field" "Disabled,Enabled" bitfld.long 0x4C4 2. " SRE ,Slew rate field" "Fast,Slow" bitfld.long 0x4C4 0.--1. " DSE ,Drive strength field" "X1,X4,X2,X6" newline line.long 0x4C8 "FLEXCAN1_RX_SELECT_INPUT,FLEXCAN1_RX_SELECT_INPUT DAISY Register" bitfld.long 0x4C8 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO12_ALT3,I2C1_SCL_ALT2,SD3_DATA7_ALT4,SAI1_RX_DATA_ALT3,ENET1_RGMII_RD2_ALT1,?..." line.long 0x4CC "FLEXCAN2_RX_SELECT_INPUT,FLEXCAN2_RX_SELECT_INPUT DAISY Register" bitfld.long 0x4CC 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO14_ALT3,I2C3_SCL_ALT2,SD3_DATA4_ALT4,SAI1_TX_SYNC_ALT3,ENET1_RGMII_TD2_ALT1,?..." line.long 0x4D0 "FLEXCAN2_RX_SELECT_INPUT,FLEXCAN2_RX_SELECT_INPUT DAISY Register" bitfld.long 0x4D0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO12_ALT5,SD1_DATA0_ALT6,ENET1_TX_CLK_ALT6,?..." line.long 0x4D4 "CCM_EXT_CLK_2_SELECT_INPUT,CCM_EXT_CLK_2_SELECT_INPUT DAISY Register" bitfld.long 0x4D4 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO13_ALT5,SD1_DATA1_ALT6,ENET1_RX_CLK_ALT6,?..." line.long 0x4D8 "CCM_EXT_CLK_3_SELECT_INPUT,CCM_EXT_CLK_3_SELECT_INPUT DAISY Register" bitfld.long 0x4D8 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO14_ALT5,SD1_DATA2_ALT6,ENET1_CRS_ALT6,?..." line.long 0x4DC "CCM_EXT_CLK_4_SELECT_INPUT,CCM_EXT_CLK_4_SELECT_INPUT DAISY Register" bitfld.long 0x4DC 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO15_ALT5,SD1_DATA3_ALT6,ENET1_COL_ALT6,?..." line.long 0x4E0 "CCM_PMIC_READY_SELECT_INPUT,CCM_PMIC_READY_SELECT_INPUT DAISY Register" bitfld.long 0x4E0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO09_ALT5,GPIO1_IO13_ALT4,UART1_RX_DATA_ALT2,SAI1_MCLK_ALT3" line.long 0x4E4 "CSI_DATA2_SELECT_INPUT,CSI_DATA2_SELECT_INPUT DAISY Register" bitfld.long 0x4E4 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA15_ALT3,ECSPI1_SCLK_ALT3" line.long 0x4E8 "CSI_DATA3_SELECT_INPUT,CSI_DATA3_SELECT_INPUT DAISY Register" bitfld.long 0x4E8 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA14_ALT3,ECSPI1_MOSI_ALT3" line.long 0x4EC "CSI_DATA4_SELECT_INPUT,CSI_DATA4_SELECT_INPUT DAISY Register" bitfld.long 0x4EC 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA13_ALT3,ECSPI1_MISO_ALT3" line.long 0x4F0 "CSI_DATA5_SELECT_INPUT,CSI_DATA5_SELECT_INPUT DAISY Register" bitfld.long 0x4F0 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA12_ALT3,ECSPI1_SS0_ALT3" line.long 0x4F4 "CSI_DATA6_SELECT_INPUT,CSI_DATA6_SELECT_INPUT DAISY Register" bitfld.long 0x4F4 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA11_ALT3,ECSPI2_SCLK_ALT3" line.long 0x4F8 "CSI_DATA7_SELECT_INPUT,CSI_DATA7_SELECT_INPUT DAISY Register" bitfld.long 0x4F8 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA10_ALT3,ECSPI2_MOSI_ALT3" line.long 0x4FC "CSI_DATA8_SELECT_INPUT,CSI_DATA8_SELECT_INPUT DAISY Register" bitfld.long 0x4FC 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA09_ALT3,ECSPI2_MISO_ALT3" line.long 0x500 "CSI_DATA9_SELECT_INPUT,CSI_DATA9_SELECT_INPUT DAISY Register" bitfld.long 0x500 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA08_ALT3,ECSPI2_SS0_ALT3" line.long 0x504 "CSI_HSYNC_SELECT_INPUT,CSI_HSYNC_SELECT_INPUT DAISY Register" bitfld.long 0x504 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA05_ALT3,I2C3_SDA_ALT3" line.long 0x508 "CSI_PIXCLK_SELECT_INPUT,CSI_PIXCLK_SELECT_INPUT DAISY Register" bitfld.long 0x508 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA06_ALT3,I2C4_SCL_ALT3" line.long 0x50C "CSI_VSYNC_SELECT_INPUT,CSI_VSYNC_SELECT_INPUT DAISY Register" bitfld.long 0x50C 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA04_ALT3,I2C3_SCL_ALT3" line.long 0x510 "ECSPI1_SCLK_SELECT_INPUT,ECSPI1_SCLK_SELECT_INPUT DAISY Register" bitfld.long 0x510 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_RTS_B_ALT3,ECSPI1_SCLK_ALT0" line.long 0x514 "ECSPI1_MISO_SELECT_INPUT,ECSPI1_MISO_SELECT_INPUT DAISY Register" bitfld.long 0x514 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_RX_DATA_ALT3,ECSPI1_MISO_ALT0" line.long 0x518 "ECSPI1_MOSI_SELECT_INPUT,ECSPI1_MOSI_SELECT_INPUT DAISY Register" bitfld.long 0x518 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_TX_DATA_ALT3,ECSPI1_MOSI_ALT0" line.long 0x51C "ECSPI1_SS0_B_SELECT_INPUT,ECSPI1_SS0_B_SELECT_INPUT DAISY Register" bitfld.long 0x51C 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_CTS_B_ALT3,ECSPI1_SS0_ALT0" line.long 0x520 "ECSPI2_SCLK_SELECT_INPUT,ECSPI2_SCLK_SELECT_INPUT DAISY Register" bitfld.long 0x520 0. " DAISY ,Selecting pads involved in daisy chain" "ECSPI2_SCLK_ALT0,ENET1_RGMII_RD2_ALT2" line.long 0x524 "ECSPI2_MISO_SELECT_INPUT,ECSPI2_MISO_SELECT_INPUT DAISY Register" bitfld.long 0x524 0. " DAISY ,Selecting pads involved in daisy chain" "ECSPI2_MISO_ALT0,ENET1_RGMII_TD2_ALT2" line.long 0x528 "ECSPI2_MOSI_SELECT_INPUT,ECSPI2_MOSI_SELECT_INPUT DAISY Register" bitfld.long 0x528 0. " DAISY ,Selecting pads involved in daisy chain" "ECSPI2_MOSI_ALT0,ENET1_RGMII_RD3_ALT2" line.long 0x52C "ECSPI2_SS0_B_SELECT_INPUT,ECSPI2_SS0_B_SELECT_INPUT DAISY Register" bitfld.long 0x52C 0. " DAISY ,Selecting pads involved in daisy chain" "ECSPI2_SS0_ALT0,ENET1_RGMII_TD3_ALT2" line.long 0x530 "ECSPI3_SCLK_SELECT_INPUT,ECSPI3_SCLK_SELECT_INPUT DAISY Register" bitfld.long 0x530 0. " DAISY ,Selecting pads involved in daisy chain" "I2C2_SCL_ALT3,SAI2_RX_DATA_ALT1" line.long 0x534 "ECSPI3_MISO_SELECT_INPUT,ECSPI3_MISO_SELECT_INPUT DAISY Register" bitfld.long 0x534 0. " DAISY ,Selecting pads involved in daisy chain" "I2C1_SCL_ALT3,SAI2_TX_SYNC_ALT1" line.long 0x538 "ECSPI3_MOSI_SELECT_INPUT,ECSPI3_MOSI_SELECT_INPUT DAISY Register" bitfld.long 0x538 0. " DAISY ,Selecting pads involved in daisy chain" "I2C1_SDA_ALT3,SAI2_TX_BCLK_ALT1" line.long 0x53C "ECSPI3_SS0_B_SELECT_INPUT,ECSPI3_SS0_B_SELECT_INPUT DAISY Register" bitfld.long 0x53C 0. " DAISY ,Selecting pads involved in daisy chain" "I2C2_SDA_ALT3,SAI2_TX_DATA_ALT1" line.long 0x540 "ECSPI4_SCLK_SELECT_INPUT,ECSPI4_SCLK_SELECT_INPUT DAISY Register" bitfld.long 0x540 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_HSYNC_ALT1,SD1_RESET_B_ALT3,SD3_DATA1_ALT2,?..." line.long 0x544 "ECSPI4_MISO_SELECT_INPUT,ECSPI4_MISO_SELECT_INPUT DAISY Register" bitfld.long 0x544 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_CLK_ALT1,SD1_CD_B_ALT3,SD3_CLK_ALT2,?..." line.long 0x548 "ECSPI4_MOSI_SELECT_INPUT,ECSPI4_MOSI_SELECT_INPUT DAISY Register" bitfld.long 0x548 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_ENABLE_ALT1,SD1_WP_ALT3,SD3_CMD_ALT2,?..." line.long 0x54C "ECSPI4_SS0_B_SELECT_INPUT,ECSPI4_SS0_B_SELECT_INPUT DAISY Register" bitfld.long 0x54C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_VSYNC_ALT1,SD1_CLK_ALT3,SD3_DATA0_ALT2,?..." line.long 0x550 "CCM_ENET1_REF_CLK_SELECT_INPUT,CCM_ENET1_REF_CLK_SELECT_INPUT DAISY Register" bitfld.long 0x550 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO12_ALT2,I2C1_SDA_ALT4,ENET1_TX_CLK_ALT1,GPIO1_IO02_ALT2" line.long 0x554 "ENET1_MDIO_SELECT_INPUT,ENET1_MDIO_SELECT_INPUT DAISY Register" bitfld.long 0x554 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO10_ALT2,UART1_RX_DATA_ALT6,SD2_CD_B_ALT1,?..." line.long 0x558 "ENET1_RX_CLK_SELECT_INPUT,ENET1_RX_CLK_SELECT_INPUT DAISY Register" bitfld.long 0x558 0. " DAISY ,Selecting pads involved in daisy chain" "ENET1_RGMII_RXC_ALT0,ENET1_RX_CLK_ALT0" line.long 0x55C "CCM_ENET2_REF_CLK_SELECT_INPUT,CCM_ENET2_REF_CLK_SELECT_INPUT DAISY Register" bitfld.long 0x55C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO13_ALT2,EPDC_BDR0_ALT3,I2C2_SCL_ALT4,GPIO1_IO03_ALT2" line.long 0x560 "ENET2_MDIO_SELECT_INPUT,ENET2_MDIO_SELECT_INPUT DAISY Register" bitfld.long 0x560 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO14_ALT2,UART2_RX_DATA_ALT6,SD2_CD_B_ALT2,?..." line.long 0x564 "ENET2_RX_CLK_SELECT_INPUT,ENET2_RX_CLK_SELECT_INPUT DAISY Register" bitfld.long 0x564 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCE1_ALT2,EPDC_BDR1_ALT2" line.long 0x568 "EPDC_PWR_IRQ_SELECT_INPUT,EPDC_PWR_IRQ_SELECT_INPUT DAISY Register" bitfld.long 0x568 0. " DAISY ,Selecting pads involved in daisy chain" "ECSPI1_MISO_ALT6,ENET1_TX_CLK_ALT4" line.long 0x56C "EPDC_PWR_STAT_SELECT_INPUT,EPDC_PWR_STAT_SELECT_INPUT DAISY Register" bitfld.long 0x56C 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_PWR_STAT_ALT0,ECSPI1_MOSI_ALT6" line.long 0x570 "FLEXTIMER1_CH0_SELECT_INPUT,FLEXTIMER1_CH0_SELECT_INPUT DAISY Register" bitfld.long 0x570 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDOE_ALT1,SD1_CD_B_ALT4" line.long 0x574 "FLEXTIMER1_CH1_SELECT_INPUT,FLEXTIMER1_CH1_SELECT_INPUT DAISY Register" bitfld.long 0x574 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDSHR_ALT1,SD1_WP_ALT4" line.long 0x578 "FLEXTIMER1_CH2_SELECT_INPUT,FLEXTIMER1_CH2_SELECT_INPUT DAISY Register" bitfld.long 0x578 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCE0_ALT1,SD1_RESET_B_ALT4" line.long 0x57C "FLEXTIMER1_CH3_SELECT_INPUT,FLEXTIMER1_CH3_SELECT_INPUT DAISY Register" bitfld.long 0x57C 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCE1_ALT1,SD1_CLK_ALT4" line.long 0x580 "FLEXTIMER1_CH4_SELECT_INPUT,FLEXTIMER1_CH4_SELECT_INPUT DAISY Register" bitfld.long 0x580 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA16_ALT1,GPIO1_IO04_ALT2" line.long 0x584 "FLEXTIMER1_CH5_SELECT_INPUT,FLEXTIMER1_CH5_SELECT_INPUT DAISY Register" bitfld.long 0x584 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA17_ALT1,GPIO1_IO05_ALT2" line.long 0x588 "FLEXTIMER1_CH6_SELECT_INPUT,FLEXTIMER1_CH6_SELECT_INPUT DAISY Register" bitfld.long 0x588 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA18_ALT1,GPIO1_IO06_ALT2" line.long 0x58C "FLEXTIMER1_CH7_SELECT_INPUT,FLEXTIMER1_CH7_SELECT_INPUT DAISY Register" bitfld.long 0x58C 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA19_ALT1,GPIO1_IO07_ALT2" line.long 0x590 "FLEXTIMER1_PHA_SELECT_INPUT,FLEXTIMER1_PHA_SELECT_INPUT DAISY Register" bitfld.long 0x590 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO10_ALT5,SD1_DATA3_ALT4" line.long 0x594 "FLEXTIMER1_PHB_SELECT_INPUT,FLEXTIMER1_PHB_SELECT_INPUT DAISY Register" bitfld.long 0x594 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO11_ALT5,SD2_CD_B_ALT4" line.long 0x598 "FLEXTIMER2_CH0_SELECT_INPUT,FLEXTIMER2_CH0_SELECT_INPUT DAISY Register" bitfld.long 0x598 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDCLK_ALT1,SD1_CMD_ALT4" line.long 0x59C "FLEXTIMER2_CH1_SELECT_INPUT,FLEXTIMER2_CH1_SELECT_INPUT DAISY Register" bitfld.long 0x59C 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDOE_ALT1,SD1_DATA0_ALT4" line.long 0x5A0 "FLEXTIMER2_CH2_SELECT_INPUT,FLEXTIMER2_CH2_SELECT_INPUT DAISY Register" bitfld.long 0x5A0 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDRL_ALT1,SD1_DATA1_ALT4" line.long 0x5A4 "FLEXTIMER2_CH3_SELECT_INPUT,FLEXTIMER2_CH3_SELECT_INPUT DAISY Register" bitfld.long 0x5A4 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDSP_ALT1,SD1_DATA2_ALT4" line.long 0x5A8 "FLEXTIMER2_CH4_SELECT_INPUT,FLEXTIMER2_CH4_SELECT_INPUT DAISY Register" bitfld.long 0x5A8 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA20_ALT1,SAI2_TX_SYNC_ALT4" line.long 0x5AC "FLEXTIMER2_CH5_SELECT_INPUT,FLEXTIMER2_CH5_SELECT_INPUT DAISY Register" bitfld.long 0x5AC 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA21_ALT1,SAI2_TX_BCLK_ALT4" line.long 0x5B0 "FLEXTIMER2_CH6_SELECT_INPUT,FLEXTIMER2_CH6_SELECT_INPUT DAISY Register" bitfld.long 0x5B0 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA22_ALT1,SAI2_RX_DATA_ALT4" line.long 0x5B4 "FLEXTIMER2_CH7_SELECT_INPUT,FLEXTIMER2_CH7_SELECT_INPUT DAISY Register" bitfld.long 0x5B4 0. " DAISY ,Selecting pads involved in daisy chain" "LCD_DATA23_ALT1,SAI2_TX_DATA_ALT4" line.long 0x5B8 "FLEXTIMER2_PHA_SELECT_INPUT,FLEXTIMER2_PHA_SELECT_INPUT DAISY Register" bitfld.long 0x5B8 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_PWR_COM_ALT1,SAI1_RX_BCLK_ALT4" line.long 0x5BC "FLEXTIMER2_PHB_SELECT_INPUT,FLEXTIMER2_PHB_SELECT_INPUT DAISY Register" bitfld.long 0x5BC 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_PWR_STAT_ALT1,SAI1_MCLK_ALT4" line.long 0x5C0 "I2C1_SCL_SELECT_INPUT,I2C1_SCL_SELECT_INPUT DAISY Register" bitfld.long 0x5C0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART1_RX_DATA_ALT1,I2C1_SCL_ALT0,GPIO1_IO04_ALT4,?..." line.long 0x5C4 "I2C1_SDA_SELECT_INPUT,I2C1_SDA_SELECT_INPUT DAISY Register" bitfld.long 0x5C4 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART1_TX_DATA_ALT1,I2C1_SDA_ALT0,GPIO1_IO05_ALT4,?..." line.long 0x5C8 "I2C2_SCL_SELECT_INPUT,I2C2_SCL_SELECT_INPUT DAISY Register" bitfld.long 0x5C8 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART2_RX_DATA_ALT1,I2C2_SCL_ALT0,GPIO1_IO06_ALT4,?..." line.long 0x5CC "I2C2_SDA_SELECT_INPUT,I2C2_SDA_SELECT_INPUT DAISY Register" bitfld.long 0x5CC 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART2_TX_DATA_ALT1,I2C2_SDA_ALT0,GPIO1_IO07_ALT4,?..." line.long 0x5D0 "I2C3_SCL_SELECT_INPUT,I2C3_SCL_SELECT_INPUT DAISY Register" bitfld.long 0x5D0 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO08_ALT4,LCD_DATA20_ALT6,I2C3_SCL_ALT0,SD3_DATA3_ALT2,ENET1_RGMII_RD0_ALT2,?..." line.long 0x5D4 "I2C3_SDA_SELECT_INPUT,I2C3_SDA_SELECT_INPUT DAISY Register" bitfld.long 0x5D4 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO09_ALT4,LCD_DATA21_ALT6,I2C3_SDA_ALT0,SD3_DATA2_ALT2,ENET1_RGMII_RD1_ALT2,?..." line.long 0x5D8 "I2C4_SCL_SELECT_INPUT,I2C4_SCL_SELECT_INPUT DAISY Register" bitfld.long 0x5D8 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO10_ALT4,LCD_DATA22_ALT6,I2C4_SCL_ALT0,SAI1_RX_SYNC_ALT3,ENET1_RGMII_TD2_ALT3,?..." line.long 0x5DC "I2C4_SDA_SELECT_INPUT,I2C4_SDA_SELECT_INPUT DAISY Register" bitfld.long 0x5DC 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO11_ALT4,LCD_DATA23_ALT6,I2C4_SDA_ALT0,SAI1_RX_BCLK_ALT3,ENET1_RGMII_TD3_ALT3,?..." line.long 0x5E0 "KPP_COL0_SELECT_INPUT,KPP_COL0_SELECT_INPUT DAISY Register" bitfld.long 0x5E0 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA07_ALT3,ENET1_RGMII_TD1_ALT6" line.long 0x5E4 "KPP_COL1_SELECT_INPUT,KPP_COL1_SELECT_INPUT DAISY Register" bitfld.long 0x5E4 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA05_ALT3,ENET1_RGMII_RXC_ALT6" line.long 0x5E8 "KPP_COL2_SELECT_INPUT,KPP_COL2_SELECT_INPUT DAISY Register" bitfld.long 0x5E8 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA03_ALT3,ENET1_RGMII_RD3_ALT6" line.long 0x5EC "KPP_COL3_SELECT_INPUT,KPP_COL3_SELECT_INPUT DAISY Register" bitfld.long 0x5EC 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA01_ALT3,ENET1_RGMII_RD1_ALT6" line.long 0x5F0 "KPP_COL4_SELECT_INPUT,KPP_COL4_SELECT_INPUT DAISY Register" bitfld.long 0x5F0 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDLE_ALT3,GPIO1_IO07_ALT6" line.long 0x5F4 "KPP_COL5_SELECT_INPUT,KPP_COL5_SELECT_INPUT DAISY Register" bitfld.long 0x5F4 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO08_ALT6,EPDC_SDOE_ALT3" line.long 0x5F8 "KPP_COL6_SELECT_INPUT,KPP_COL6_SELECT_INPUT DAISY Register" bitfld.long 0x5F8 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO10_ALT6,EPDC_SDCE2_ALT3" line.long 0x5FC "KPP_COL7_SELECT_INPUT,KPP_COL7_SELECT_INPUT DAISY Register" bitfld.long 0x5FC 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDCLK_ALT3,SAI2_RX_DATA_ALT6" line.long 0x600 "KPP_ROW0_SELECT_INPUT,KPP_ROW0_SELECT_INPUT DAISY Register" bitfld.long 0x600 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA06_ALT3,ENET1_RGMII_TD0_ALT6" line.long 0x604 "KPP_ROW1_SELECT_INPUT,KPP_ROW1_SELECT_INPUT DAISY Register" bitfld.long 0x604 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA04_ALT3,ENET1_RGMII_RX_CTL_ALT6" line.long 0x608 "KPP_ROW2_SELECT_INPUT,KPP_ROW2_SELECT_INPUT DAISY Register" bitfld.long 0x608 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA02_ALT3,ENET1_RGMII_RD2_ALT6" line.long 0x60C "KPP_ROW3_SELECT_INPUT,KPP_ROW3_SELECT_INPUT DAISY Register" bitfld.long 0x60C 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA00_ALT3,ENET1_RGMII_RD0_ALT6" line.long 0x610 "KPP_ROW4_SELECT_INPUT,KPP_ROW4_SELECT_INPUT DAISY Register" bitfld.long 0x610 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCLK_ALT3,GPIO1_IO06_ALT6" line.long 0x614 "KPP_ROW5_SELECT_INPUT,KPP_ROW5_SELECT_INPUT DAISY Register" bitfld.long 0x614 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO09_ALT6,EPDC_SDSHR_ALT3" line.long 0x618 "KPP_ROW6_SELECT_INPUT,KPP_ROW6_SELECT_INPUT DAISY Register" bitfld.long 0x618 0. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO11_ALT6,EPDC_SDCE3_ALT3" line.long 0x61C "KPP_ROW7_SELECT_INPUT,KPP_ROW7_SELECT_INPUT DAISY Register" bitfld.long 0x61C 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_GDOE_ALT3,SAI2_TX_DATA_ALT6" line.long 0x620 "LCD_BUSY_SELECT_INPUT,LCD_BUSY_SELECT_INPUT DAISY Register" bitfld.long 0x620 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA08_ALT7,EPDC_GDSP_ALT6" line.long 0x624 "LCD_DATA00_SELECT_INPUT,LCD_DATA00_SELECT_INPUT DAISY Register" bitfld.long 0x624 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA00_ALT6,EPDC_DATA09_ALT7,LCD_DATA00_ALT0,?..." line.long 0x628 "LCD_DATA01_SELECT_INPUT,LCD_DATA01_SELECT_INPUT DAISY Register" bitfld.long 0x628 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA01_ALT6,EPDC_DATA11_ALT7,LCD_DATA01_ALT0,?..." line.long 0x62C "LCD_DATA02_SELECT_INPUT,LCD_DATA02_SELECT_INPUT DAISY Register" bitfld.long 0x62C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA02_ALT6,EPDC_SDCE3_ALT7,LCD_DATA02_ALT0,?..." line.long 0x630 "LCD_DATA03_SELECT_INPUT,LCD_DATA03_SELECT_INPUT DAISY Register" bitfld.long 0x630 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA03_ALT6,EPDC_SDCE2_ALT7,LCD_DATA03_ALT0,?..." line.long 0x634 "LCD_DATA04_SELECT_INPUT,LCD_DATA04_SELECT_INPUT DAISY Register" bitfld.long 0x634 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA04_ALT6,EPDC_SDCE1_ALT7,LCD_DATA04_ALT0,?..." line.long 0x638 "LCD_DATA05_SELECT_INPUT,LCD_DATA05_SELECT_INPUT DAISY Register" bitfld.long 0x638 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA05_ALT6,EPDC_SDCE0_ALT7,LCD_DATA05_ALT0,?..." line.long 0x63C "LCD_DATA06_SELECT_INPUT,LCD_DATA06_SELECT_INPUT DAISY Register" bitfld.long 0x63C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA06_ALT6,EPDC_BDR1_ALT7,LCD_DATA06_ALT0,?..." line.long 0x640 "LCD_DATA07_SELECT_INPUT,LCD_DATA07_SELECT_INPUT DAISY Register" bitfld.long 0x640 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA07_ALT6,EPDC_BDR0_ALT7,LCD_DATA07_ALT0,?..." line.long 0x644 "LCD_DATA08_SELECT_INPUT,LCD_DATA08_SELECT_INPUT DAISY Register" bitfld.long 0x644 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA08_ALT6,EPDC_SDLE_ALT7,LCD_DATA08_ALT0,?..." line.long 0x648 "LCD_DATA09_SELECT_INPUT,LCD_DATA09_SELECT_INPUT DAISY Register" bitfld.long 0x648 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA09_ALT6,EPDC_DATA10_ALT7,LCD_DATA09_ALT0,?..." line.long 0x64C "LCD_DATA10_SELECT_INPUT,LCD_DATA10_SELECT_INPUT DAISY Register" bitfld.long 0x64C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA10_ALT6,EPDC_SDSHR_ALT7,LCD_DATA10_ALT0,?..." line.long 0x650 "LCD_DATA11_SELECT_INPUT,LCD_DATA11_SELECT_INPUT DAISY Register" bitfld.long 0x650 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA11_ALT6,EPDC_PWR_COM_ALT7,LCD_DATA11_ALT0,?..." line.long 0x654 "LCD_DATA12_SELECT_INPUT,LCD_DATA12_SELECT_INPUT DAISY Register" bitfld.long 0x654 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA12_ALT6,EPDC_PWR_STAT_ALT7,LCD_DATA12_ALT0,?..." line.long 0x658 "LCD_DATA13_SELECT_INPUT,LCD_DATA13_SELECT_INPUT DAISY Register" bitfld.long 0x658 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA13_ALT6,LCD_DATA13_ALT0,ECSPI2_SCLK_ALT4,?..." line.long 0x65C "LCD_DATA14_SELECT_INPUT,LCD_DATA14_SELECT_INPUT DAISY Register" bitfld.long 0x65C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA14_ALT6,LCD_DATA14_ALT0,ECSPI2_MOSI_ALT4,?..." line.long 0x660 "LCD_DATA15_SELECT_INPUT,LCD_DATA15_SELECT_INPUT DAISY Register" bitfld.long 0x660 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA15_ALT6,LCD_DATA15_ALT0,ECSPI2_MISO_ALT4,?..." line.long 0x664 "LCD_DATA16_SELECT_INPUT,LCD_DATA16_SELECT_INPUT DAISY Register" bitfld.long 0x664 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDLE_ALT6,EPDC_GDCLK_ALT7,LCD_DATA16_ALT0,?..." line.long 0x668 "LCD_DATA17_SELECT_INPUT,LCD_DATA17_SELECT_INPUT DAISY Register" bitfld.long 0x668 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDOE_ALT6,EPDC_GDSP_ALT7,LCD_DATA17_ALT0,?..." line.long 0x66C "LCD_DATA18_SELECT_INPUT,LCD_DATA18_SELECT_INPUT DAISY Register" bitfld.long 0x66C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDSHR_ALT6,EPDC_GDOE_ALT7,LCD_DATA18_ALT0,?..." line.long 0x670 "LCD_DATA19_SELECT_INPUT,LCD_DATA19_SELECT_INPUT DAISY Register" bitfld.long 0x670 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCE0_ALT6,EPDC_GDRL_ALT7,LCD_DATA19_ALT0,?..." line.long 0x674 "LCD_DATA20_SELECT_INPUT,LCD_DATA20_SELECT_INPUT DAISY Register" bitfld.long 0x674 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCLK_ALT7,EPDC_SDCE1_ALT6,LCD_DATA20_ALT0,?..." line.long 0x678 "LCD_DATA21_SELECT_INPUT,LCD_DATA21_SELECT_INPUT DAISY Register" bitfld.long 0x678 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA12_ALT7,EPDC_SDCE2_ALT6,LCD_DATA21_ALT0,?..." line.long 0x67C "LCD_DATA22_SELECT_INPUT,LCD_DATA22_SELECT_INPUT DAISY Register" bitfld.long 0x67C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA14_ALT7,EPDC_SDCE3_ALT6,LCD_DATA22_ALT0,?..." line.long 0x680 "LCD_DATA23_SELECT_INPUT,LCD_DATA23_SELECT_INPUT DAISY Register" bitfld.long 0x680 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDOE_ALT7,EPDC_GDCLK_ALT6,LCD_DATA23_ALT0,?..." line.long 0x684 "LCD_VSYNC_SELECT_INPUT,LCD_VSYNC_SELECT_INPUT DAISY Register" bitfld.long 0x684 0.--1. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA02_ALT7,EPDC_PWR_STAT_ALT6,LCD_VSYNC_ALT0,?..." line.long 0x688 "SAI1_RX_BCLK_SELECT_INPUT,SAI1_RX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x688 0. " DAISY ,Selecting pads involved in daisy chain" "SAI1_RX_BCLK_ALT0,ENET1_TXC_ALT2" line.long 0x68C "SAI1_RX_DATA_SELECT_INPUT,SAI1_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x68C 0. " DAISY ,Selecting pads involved in daisy chain" "SAI1_RX_DATA_ALT0,ENET1_TX_CLK_ALT2" line.long 0x690 "SAI1_RX_SYNC_SELECT_INPUT,SAI1_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x690 0. " DAISY ,Selecting pads involved in daisy chain" "SAI1_RX_SYNC_ALT0,ENET1_TX_CTL_ALT2" line.long 0x694 "SAI1_TX_BCLK_SELECT_INPUT,SAI1_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x694 0. " DAISY ,Selecting pads involved in daisy chain" "SAI1_TX_BCLK_ALT0,ENET1_RX_CLK_ALT2" line.long 0x698 "SAI1_TX_SYNC_SELECT_INPUT,SAI1_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x698 0. " DAISY ,Selecting pads involved in daisy chain" "SAI1_TX_SYNC_ALT0,ENET1_CRS_ALT2" line.long 0x69C "SAI2_RX_BCLK_SELECT_INPUT,SAI2_RX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x69C 0. " DAISY ,Selecting pads involved in daisy chain" "SD2_CMD_ALT1,SAI1_RX_BCLK_ALT2" line.long 0x6A0 "SAI2_RX_DATA_SELECT_INPUT,SAI2_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6A0 0. " DAISY ,Selecting pads involved in daisy chain" "SD2_DATA0_ALT1,SAI2_RX_DATA_ALT0" line.long 0x6A4 "SAI2_RX_SYNC_SELECT_INPUT,SAI2_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x6A4 0. " DAISY ,Selecting pads involved in daisy chain" "SD2_CLK_ALT1,SAI1_RX_SYNC_ALT2" line.long 0x6A8 "SAI2_TX_BCLK_SELECT_INPUT,SAI2_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x6A8 0. " DAISY ,Selecting pads involved in daisy chain" "SD2_DATA1_ALT1,SAI2_TX_BCLK_ALT0" line.long 0x6AC "SAI2_TX_SYNC_SELECT_INPUT,SAI2_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x6AC 0. " DAISY ,Selecting pads involved in daisy chain" "SD2_DATA2_ALT1,SAI2_TX_SYNC_ALT0" line.long 0x6B0 "SAI3_RX_BCLK_SELECT_INPUT,SAI3_RX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x6B0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART2_RX_DATA_ALT2,SD1_CMD_ALT1,SD3_CMD_ALT3,?..." line.long 0x6B4 "SAI3_RX_DATA_SELECT_INPUT,SAI3_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6B4 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART2_TX_DATA_ALT2,SD1_DATA0_ALT1,SD3_DATA0_ALT3,?..." line.long 0x6B8 "SAI3_RX_SYNC_SELECT_INPUT,SAI3_RX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x6B8 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART3_RX_DATA_ALT2,SD1_CLK_ALT1,SD3_CLK_ALT3,?..." line.long 0x6BC "SAI3_TX_BCLK_SELECT_INPUT,SAI3_TX_BCLK_SELECT_INPUT DAISY Register" bitfld.long 0x6BC 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART3_TX_DATA_ALT2,SD1_DATA1_ALT1,SD3_DATA1_ALT3,?..." line.long 0x6C0 "SAI3_TX_SYNC_SELECT_INPUT,SAI3_TX_SYNC_SELECT_INPUT DAISY Register" bitfld.long 0x6C0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART3_CTS_B_ALT2,SD1_DATA2_ALT1,SD3_DATA2_ALT3,?..." line.long 0x6C4 "SDMA_EVENTS0_SELECT_INPUT,SDMA_EVENTS0_SELECT_INPUT DAISY Register" bitfld.long 0x6C4 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO14_ALT6,I2C3_SCL_ALT4,SD2_CD_B_ALT6,?..." line.long 0x6C8 "SDMA_EVENTS1_SELECT_INPUT,SDMA_EVENTS1_SELECT_INPUT DAISY Register" bitfld.long 0x6C8 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO15_ALT6,I2C3_SDA_ALT4,SD2_WP_ALT6,?..." line.long 0x6CC "SIM1_PORT1_PD_SELECT_INPUT,SIM1_PORT1_PD_SELECT_INPUT DAISY Register" bitfld.long 0x6CC 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA12_ALT1,SAI1_RX_SYNC_ALT4" line.long 0x6D0 "SIM1_PORT1_TRXD_SELECT_INPUT,SIM1_PORT1_TRXD_SELECT_INPUT DAISY Register" bitfld.long 0x6D0 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA08_ALT1,SAI1_RX_DATA_ALT4" line.long 0x6D4 "SIM2_PORT1_PD_SELECT_INPUT,SIM2_PORT1_PD_SELECT_INPUT DAISY Register" bitfld.long 0x6D4 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_SDCE3_ALT1,SD2_DATA3_ALT4" line.long 0x6D8 "SIM2_PORT1_TRXD_SELECT_INPUT,SIM2_PORT1_TRXD_SELECT_INPUT DAISY Register" bitfld.long 0x6D8 0. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA13_ALT1,SD2_CMD_ALT4" line.long 0x6DC "UART1_RTS_B_SELECT_INPUT,UART1_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x6DC 0.--1. " DAISY ,Selecting pads involved in daisy chain" "SAI2_TX_SYNC_ALT3,SAI2_TX_BCLK_ALT3,ENET1_RGMII_RD0_ALT3,ENET1_RGMII_RD1_ALT3" line.long 0x6E0 "UART1_RX_DATA_SELECT_INPUT,UART1_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6E0 0.--1. " DAISY ,Selecting pads involved in daisy chain" "UART1_RX_DATA_ALT0,UART1_TX_DATA_ALT0,ENET1_RGMII_RD2_ALT3,ENET1_RGMII_RD3_ALT3" line.long 0x6E4 "UART2_RTS_B_SELECT_INPUT,UART2_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x6E4 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_HSYNC_ALT4,LCD_VSYNC_ALT4,SAI2_RX_DATA_ALT3,SAI2_TX_DATA_ALT3" line.long 0x6E8 "UART2_RX_DATA_SELECT_INPUT,UART2_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6E8 0.--1. " DAISY ,Selecting pads involved in daisy chain" "LCD_CLK_ALT4,LCD_ENABLE_ALT4,UART2_RX_DATA_ALT0,?..." line.long 0x6EC "UART3_RTS_B_SELECT_INPUT,UART3_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x6EC 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO10_ALT3,GPIO1_IO11_ALT3,UART3_RTS_B_ALT0,UART3_CTS_B_ALT0,SD3_DATA6_ALT3,SD3_DATA7_ALT3,?..." line.long 0x6F0 "UART3_RX_DATA_SELECT_INPUT,UART3_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6F0 0.--2. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO08_ALT3,GPIO1_IO09_ALT3,UART3_RX_DATA_ALT0,UART3_TX_DATA_ALT0,SD3_DATA4_ALT3,SD3_DATA5_ALT3,?..." line.long 0x6F4 "UART4_RTS_B_SELECT_INPUT,UART4_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x6F4 0.--2. " DAISY ,Selecting pads involved in daisy chain" "I2C1_SCL_ALT1,I2C1_SDA_ALT1,SD2_DATA2_ALT2,SD2_DATA3_ALT2,SAI2_RX_DATA_ALT2,SAI2_TX_DATA_ALT2,?..." line.long 0x6F8 "UART4_RX_DATA_SELECT_INPUT,UART4_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x6F8 0.--2. " DAISY ,Selecting pads involved in daisy chain" "I2C2_SCL_ALT1,I2C2_SDA_ALT1,SD2_DATA0_ALT2,SD2_DATA1_ALT2,SAI2_TX_SYNC_ALT2,SAI2_TX_BCLK_ALT2,?..." line.long 0x6FC "UART5_RTS_B_SELECT_INPUT,UART5_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x6FC 0.--2. " DAISY ,Selecting pads involved in daisy chain" "I2C3_SCL_ALT1,I2C3_SDA_ALT1,SAI1_TX_SYNC_ALT2,SAI1_TX_DATA_ALT2,GPIO1_IO04_ALT3,GPIO1_IO05_ALT3,?..." line.long 0x700 "UART5_RX_DATA_SELECT_INPUT,UART5_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x700 0.--2. " DAISY ,Selecting pads involved in daisy chain" "I2C4_SCL_ALT1,I2C4_SDA_ALT1,SAI1_RX_DATA_ALT2,SAI1_TX_BCLK_ALT2,GPIO1_IO06_ALT3,GPIO1_IO07_ALT3,?..." line.long 0x704 "UART6_RTS_B_SELECT_INPUT,UART6_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x704 0.--2. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA10_ALT3,EPDC_DATA11_ALT3,ECSPI1_MISO_ALT1,ECSPI1_SS0_ALT1,SD1_RESET_B_ALT2,SD1_CLK_ALT2,?..." line.long 0x708 "UART6_RX_DATA_SELECT_INPUT,UART6_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x708 0.--2. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA08_ALT3,EPDC_DATA09_ALT3,ECSPI1_SCLK_ALT1,ECSPI1_MOSI_ALT1,SD1_CD_B_ALT2,SD1_WP_ALT2,?..." line.long 0x70C "UART7_RTS_B_SELECT_INPUT,UART7_RTS_B_SELECT_INPUT DAISY Register" bitfld.long 0x70C 0.--2. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA14_ALT3,EPDC_DATA15_ALT3,ECSPI2_MISO_ALT1,ECSPI2_SS0_ALT1,SD1_DATA2_ALT2,SD1_DATA3_ALT2,?..." line.long 0x710 "UART7_RX_DATA_SELECT_INPUT,UART7_RX_DATA_SELECT_INPUT DAISY Register" bitfld.long 0x710 0.--2. " DAISY ,Selecting pads involved in daisy chain" "EPDC_DATA12_ALT3,EPDC_DATA13_ALT3,ECSPI2_SCLK_ALT1,ECSPI2_MOSI_ALT1,SD1_DATA0_ALT2,SD1_DATA1_ALT2,?..." line.long 0x714 "USB_OTG2_OC_SELECT_INPUT,USB_OTG2_OC_SELECT_INPUT DAISY Register" bitfld.long 0x714 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_RTS_B_ALT1,GPIO1_IO06_ALT1" line.long 0x718 "USB_OTG1_OC_SELECT_INPUT,USB_OTG1_OC_SELECT_INPUT DAISY Register" bitfld.long 0x718 0. " DAISY ,Selecting pads involved in daisy chain" "UART3_RX_DATA_ALT1,GPIO1_IO04_ALT1" line.long 0x71C "USB_OTG2_ID_SELECT_INPUT,USB_OTG2_ID_SELECT_INPUT DAISY Register" bitfld.long 0x71C 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO13_ALT7,I2C4_SDA_ALT4,SD2_RESET_B_ALT4,GPIO1_IO03_ALT7" line.long 0x720 "USB_OTG1_ID_SELECT_INPUT,USB_OTG1_ID_SELECT_INPUT DAISY Register" bitfld.long 0x720 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO12_ALT7,I2C4_SCL_ALT4,SD2_WP_ALT4,GPIO1_IO02_ALT7" line.long 0x724 "SD3_CD_B_SELECT_INPUT,SD3_CD_B_SELECT_INPUT DAISY Register" bitfld.long 0x724 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO14_ALT1,I2C2_SCL_ALT6,SD3_DATA7_ALT2,?..." line.long 0x728 "SD3_WP_SELECT_INPUT,SD3_WP_SELECT_INPUT DAISY Register" bitfld.long 0x728 0.--1. " DAISY ,Selecting pads involved in daisy chain" "GPIO1_IO15_ALT1,I2C2_SDA_ALT6,SD3_DATA6_ALT2,?..." width 0x0B tree.end tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIO1" base ad:0x30200000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" hgroup.long 0x10++0x03 hide.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO2" base ad:0x30210000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR31 ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " GDIR27 ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR31 ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " PSR28 ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " PSR27 ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 30.--31. " ICR31 ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR30 ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR29 ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR28 ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR27 ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR26 ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 31. " IMR31 ,Interrupt 31 mask bit" "Masked,Not masked" bitfld.long 0x00 30. " IMR30 ,Interrupt 30 mask bit" "Masked,Not masked" bitfld.long 0x00 29. " IMR29 ,Interrupt 29 mask bit" "Masked,Not masked" bitfld.long 0x00 28. " IMR28 ,Interrupt 28 mask bit" "Masked,Not masked" newline bitfld.long 0x00 27. " IMR27 ,Interrupt 27 mask bit" "Masked,Not masked" bitfld.long 0x00 26. " IMR26 ,Interrupt 26 mask bit" "Masked,Not masked" bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" newline bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" newline bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" newline bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 31. " ISR31 ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x04 30. " ISR30 ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x04 29. " ISR29 ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x04 28. " ISR28 ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " ISR27 ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x04 26. " ISR26 ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "ICR 31 setting,Any edge" bitfld.long 0x08 30. " GPIO_EDGE_SEL[30] ,Edge select bit 30" "ICR 30 setting,Any edge" bitfld.long 0x08 29. " GPIO_EDGE_SEL[29] ,Edge select bit 29" "ICR 29 setting,Any edge" bitfld.long 0x08 28. " GPIO_EDGE_SEL[28] ,Edge select bit 28" "ICR 28 setting,Any edge" newline bitfld.long 0x08 27. " GPIO_EDGE_SEL[27] ,Edge select bit 27" "ICR 27 setting,Any edge" bitfld.long 0x08 26. " GPIO_EDGE_SEL[26] ,Edge select bit 26" "ICR 26 setting,Any edge" bitfld.long 0x08 25. " GPIO_EDGE_SEL[25] ,Edge select bit 25" "ICR 25 setting,Any edge" bitfld.long 0x08 24. " GPIO_EDGE_SEL[24] ,Edge select bit 24" "ICR 24 setting,Any edge" newline bitfld.long 0x08 23. " GPIO_EDGE_SEL[23] ,Edge select bit 23" "ICR 23 setting,Any edge" bitfld.long 0x08 22. " GPIO_EDGE_SEL[22] ,Edge select bit 22" "ICR 22 setting,Any edge" bitfld.long 0x08 21. " GPIO_EDGE_SEL[21] ,Edge select bit 21" "ICR 21 setting,Any edge" bitfld.long 0x08 20. " GPIO_EDGE_SEL[20] ,Edge select bit 20" "ICR 20 setting,Any edge" newline bitfld.long 0x08 19. " GPIO_EDGE_SEL[19] ,Edge select bit 19" "ICR 19 setting,Any edge" bitfld.long 0x08 18. " GPIO_EDGE_SEL[18] ,Edge select bit 18" "ICR 18 setting,Any edge" bitfld.long 0x08 17. " GPIO_EDGE_SEL[17] ,Edge select bit 17" "ICR 17 setting,Any edge" bitfld.long 0x08 16. " GPIO_EDGE_SEL[16] ,Edge select bit 16" "ICR 16 setting,Any edge" newline bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO3" base ad:0x30220000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 28. " GDIR28 ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " GDIR27 ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 28. " PSR28 ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " PSR27 ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " PSR25 ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 24.--25. " ICR28 ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR27 ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR26 ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR25 ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR24 ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 28. " IMR28 ,Interrupt 28 mask bit" "Masked,Not masked" newline bitfld.long 0x00 27. " IMR27 ,Interrupt 27 mask bit" "Masked,Not masked" bitfld.long 0x00 26. " IMR26 ,Interrupt 26 mask bit" "Masked,Not masked" bitfld.long 0x00 25. " IMR25 ,Interrupt 25 mask bit" "Masked,Not masked" bitfld.long 0x00 24. " IMR24 ,Interrupt 24 mask bit" "Masked,Not masked" newline bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" newline bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" newline bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 28. " ISR28 ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " ISR27 ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x04 26. " ISR26 ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x04 25. " ISR25 ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x04 24. " ISR24 ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 28. " GPIO_EDGE_SEL[28] ,Edge select bit 28" "ICR 28 setting,Any edge" newline bitfld.long 0x08 27. " GPIO_EDGE_SEL[27] ,Edge select bit 27" "ICR 27 setting,Any edge" bitfld.long 0x08 26. " GPIO_EDGE_SEL[26] ,Edge select bit 26" "ICR 26 setting,Any edge" bitfld.long 0x08 25. " GPIO_EDGE_SEL[25] ,Edge select bit 25" "ICR 25 setting,Any edge" bitfld.long 0x08 24. " GPIO_EDGE_SEL[24] ,Edge select bit 24" "ICR 24 setting,Any edge" newline bitfld.long 0x08 23. " GPIO_EDGE_SEL[23] ,Edge select bit 23" "ICR 23 setting,Any edge" bitfld.long 0x08 22. " GPIO_EDGE_SEL[22] ,Edge select bit 22" "ICR 22 setting,Any edge" bitfld.long 0x08 21. " GPIO_EDGE_SEL[21] ,Edge select bit 21" "ICR 21 setting,Any edge" bitfld.long 0x08 20. " GPIO_EDGE_SEL[20] ,Edge select bit 20" "ICR 20 setting,Any edge" newline bitfld.long 0x08 19. " GPIO_EDGE_SEL[19] ,Edge select bit 19" "ICR 19 setting,Any edge" bitfld.long 0x08 18. " GPIO_EDGE_SEL[18] ,Edge select bit 18" "ICR 18 setting,Any edge" bitfld.long 0x08 17. " GPIO_EDGE_SEL[17] ,Edge select bit 17" "ICR 17 setting,Any edge" bitfld.long 0x08 16. " GPIO_EDGE_SEL[16] ,Edge select bit 16" "ICR 16 setting,Any edge" newline bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO4" base ad:0x30230000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 23. " GDIR23 ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 23. " PSR23 ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 14.--15. " ICR23 ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 23. " IMR23 ,Interrupt 23 mask bit" "Masked,Not masked" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" newline bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" newline bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 23. " ISR23 ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 23. " GPIO_EDGE_SEL[23] ,Edge select bit 23" "ICR 23 setting,Any edge" bitfld.long 0x08 22. " GPIO_EDGE_SEL[22] ,Edge select bit 22" "ICR 22 setting,Any edge" bitfld.long 0x08 21. " GPIO_EDGE_SEL[21] ,Edge select bit 21" "ICR 21 setting,Any edge" bitfld.long 0x08 20. " GPIO_EDGE_SEL[20] ,Edge select bit 20" "ICR 20 setting,Any edge" newline bitfld.long 0x08 19. " GPIO_EDGE_SEL[19] ,Edge select bit 19" "ICR 19 setting,Any edge" bitfld.long 0x08 18. " GPIO_EDGE_SEL[18] ,Edge select bit 18" "ICR 18 setting,Any edge" bitfld.long 0x08 17. " GPIO_EDGE_SEL[17] ,Edge select bit 17" "ICR 17 setting,Any edge" bitfld.long 0x08 16. " GPIO_EDGE_SEL[16] ,Edge select bit 16" "ICR 16 setting,Any edge" newline bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO5" base ad:0x30240000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" newline bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 17. " GPIO_EDGE_SEL[17] ,Edge select bit 17" "ICR 17 setting,Any edge" bitfld.long 0x08 16. " GPIO_EDGE_SEL[16] ,Edge select bit 16" "ICR 16 setting,Any edge" newline bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO6" base ad:0x30250000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 22. " GDIR22 ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 22. " PSR22 ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " PSR16 ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x10++0x03 line.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x00 12.--13. " ICR22 ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR21 ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR20 ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR19 ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR18 ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR17 ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR16 ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rise-edge,Fall-edge" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 22. " IMR22 ,Interrupt 22 mask bit" "Masked,Not masked" bitfld.long 0x00 21. " IMR21 ,Interrupt 21 mask bit" "Masked,Not masked" bitfld.long 0x00 20. " IMR20 ,Interrupt 20 mask bit" "Masked,Not masked" newline bitfld.long 0x00 19. " IMR19 ,Interrupt 19 mask bit" "Masked,Not masked" bitfld.long 0x00 18. " IMR18 ,Interrupt 18 mask bit" "Masked,Not masked" bitfld.long 0x00 17. " IMR17 ,Interrupt 17 mask bit" "Masked,Not masked" bitfld.long 0x00 16. " IMR16 ,Interrupt 16 mask bit" "Masked,Not masked" newline bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 22. " ISR22 ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x04 21. " ISR21 ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x04 20. " ISR20 ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 19. " ISR19 ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x04 18. " ISR18 ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x04 17. " ISR17 ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x04 16. " ISR16 ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 22. " GPIO_EDGE_SEL[22] ,Edge select bit 22" "ICR 22 setting,Any edge" bitfld.long 0x08 21. " GPIO_EDGE_SEL[21] ,Edge select bit 21" "ICR 21 setting,Any edge" bitfld.long 0x08 20. " GPIO_EDGE_SEL[20] ,Edge select bit 20" "ICR 20 setting,Any edge" newline bitfld.long 0x08 19. " GPIO_EDGE_SEL[19] ,Edge select bit 19" "ICR 19 setting,Any edge" bitfld.long 0x08 18. " GPIO_EDGE_SEL[18] ,Edge select bit 18" "ICR 18 setting,Any edge" bitfld.long 0x08 17. " GPIO_EDGE_SEL[17] ,Edge select bit 17" "ICR 17 setting,Any edge" bitfld.long 0x08 16. " GPIO_EDGE_SEL[16] ,Edge select bit 16" "ICR 16 setting,Any edge" newline bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree "GPIO7" base ad:0x30260000 width 10. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 15. " GDIR15 ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " GDIR11 ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " GDIR3 ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 15. " PSR15 ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " PSR13 ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " PSR11 ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " PSR10 ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " PSR4 ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " PSR3 ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " PSR1 ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x03 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR15 ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 28.--29. " ICR14 ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 26.--27. " ICR13 ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 24.--25. " ICR12 ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 22.--23. " ICR11 ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 20.--21. " ICR10 ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 18.--19. " ICR9 ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 16.--17. " ICR8 ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 14.--15. " ICR7 ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 12.--13. " ICR6 ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 10.--11. " ICR5 ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 8.--9. " ICR4 ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rise-edge,Fall-edge" newline bitfld.long 0x00 6.--7. " ICR3 ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 4.--5. " ICR2 ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 2.--3. " ICR1 ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rise-edge,Fall-edge" bitfld.long 0x00 0.--1. " ICR0 ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rise-edge,Fall-edge" hgroup.long 0x10++0x03 hide.long 0x00 "ICR2,GPIO Interrupt Configuration Register 2" group.long 0x14++0x0B line.long 0x00 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x00 15. " IMR15 ,Interrupt 15 mask bit" "Masked,Not masked" bitfld.long 0x00 14. " IMR14 ,Interrupt 14 mask bit" "Masked,Not masked" bitfld.long 0x00 13. " IMR13 ,Interrupt 13 mask bit" "Masked,Not masked" bitfld.long 0x00 12. " IMR12 ,Interrupt 12 mask bit" "Masked,Not masked" newline bitfld.long 0x00 11. " IMR11 ,Interrupt 11 mask bit" "Masked,Not masked" bitfld.long 0x00 10. " IMR10 ,Interrupt 10 mask bit" "Masked,Not masked" bitfld.long 0x00 9. " IMR9 ,Interrupt 9 mask bit" "Masked,Not masked" bitfld.long 0x00 8. " IMR8 ,Interrupt 8 mask bit" "Masked,Not masked" newline bitfld.long 0x00 7. " IMR7 ,Interrupt 7 mask bit" "Masked,Not masked" bitfld.long 0x00 6. " IMR6 ,Interrupt 6 mask bit" "Masked,Not masked" bitfld.long 0x00 5. " IMR5 ,Interrupt 5 mask bit" "Masked,Not masked" bitfld.long 0x00 4. " IMR4 ,Interrupt 4 mask bit" "Masked,Not masked" newline bitfld.long 0x00 3. " IMR3 ,Interrupt 3 mask bit" "Masked,Not masked" bitfld.long 0x00 2. " IMR2 ,Interrupt 2 mask bit" "Masked,Not masked" bitfld.long 0x00 1. " IMR1 ,Interrupt 1 mask bit" "Masked,Not masked" bitfld.long 0x00 0. " IMR0 ,Interrupt 0 mask bit" "Masked,Not masked" line.long 0x04 "ISR,GPIO Interrupt Status Register" eventfld.long 0x04 15. " ISR15 ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x04 14. " ISR14 ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x04 13. " ISR13 ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x04 12. " ISR12 ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " ISR11 ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x04 10. " ISR10 ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x04 9. " ISR9 ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x04 8. " ISR8 ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " ISR7 ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x04 6. " ISR6 ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x04 5. " ISR5 ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x04 4. " ISR4 ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " ISR3 ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x04 2. " ISR2 ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x04 1. " ISR1 ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x04 0. " ISR0 ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x08 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x08 15. " GPIO_EDGE_SEL[15] ,Edge select bit 15" "ICR 15 setting,Any edge" bitfld.long 0x08 14. " GPIO_EDGE_SEL[14] ,Edge select bit 14" "ICR 14 setting,Any edge" bitfld.long 0x08 13. " GPIO_EDGE_SEL[13] ,Edge select bit 13" "ICR 13 setting,Any edge" bitfld.long 0x08 12. " GPIO_EDGE_SEL[12] ,Edge select bit 12" "ICR 12 setting,Any edge" newline bitfld.long 0x08 11. " GPIO_EDGE_SEL[11] ,Edge select bit 11" "ICR 11 setting,Any edge" bitfld.long 0x08 10. " GPIO_EDGE_SEL[10] ,Edge select bit 10" "ICR 10 setting,Any edge" bitfld.long 0x08 9. " GPIO_EDGE_SEL[9] ,Edge select bit 9" "ICR 9 setting,Any edge" bitfld.long 0x08 8. " GPIO_EDGE_SEL[8] ,Edge select bit 8" "ICR 8 setting,Any edge" newline bitfld.long 0x08 7. " GPIO_EDGE_SEL[7] ,Edge select bit 7" "ICR 7 setting,Any edge" bitfld.long 0x08 6. " GPIO_EDGE_SEL[6] ,Edge select bit 6" "ICR 6 setting,Any edge" bitfld.long 0x08 5. " GPIO_EDGE_SEL[5] ,Edge select bit 5" "ICR 5 setting,Any edge" bitfld.long 0x08 4. " GPIO_EDGE_SEL[4] ,Edge select bit 4" "ICR 4 setting,Any edge" newline bitfld.long 0x08 3. " GPIO_EDGE_SEL[3] ,Edge select bit 3" "ICR 3 setting,Any edge" bitfld.long 0x08 2. " GPIO_EDGE_SEL[2] ,Edge select bit 2" "ICR 2 setting,Any edge" bitfld.long 0x08 1. " GPIO_EDGE_SEL[1] ,Edge select bit 1" "ICR 1 setting,Any edge" bitfld.long 0x08 0. " GPIO_EDGE_SEL[0] ,Edge select bit 0" "ICR 0 setting,Any edge" width 0x0B tree.end tree.end tree.open "DDRC (DDR Controller)" tree "DDRC" base ad:0x307A0000 width 11. group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register" bitfld.long 0x00 24.--27. " ACTIVE_RANKS ,Represents the number of active ranks" ",One rank,,Two ranks,,,,,,,,,,,,Four ranks" bitfld.long 0x00 16.--19. " BURST_RDWR ,Controls the burst size used to access the SDRAM" ",2,4,,8,,,,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,Indicates whether the DDRC and DRAM have to be put in DLL-off mode" "On mode,Off mode" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,?..." else bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,Quarter,?..." endif bitfld.long 0x00 9. " BURSTCHOP ,Burst-chop in DDR3" "Disabled,Enabled" newline bitfld.long 0x00 8. " BURST_MODE ,Indicates burst mode" "Sequential,Interleaved" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "Non-LPDDR3,LPDDR3" bitfld.long 0x00 2. " LPDDR2 ,Select LPDDR2 SDRAM" "Non-LPDDR2,LPDDR2" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "Non-DDR3,DDR3" newline if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" sif (!cpuis("IMX7DUAL-CM4")&&!cpuis("IMX7DUAL-CA7")) bitfld.long 0x00 8.--9. " SELFREF_STATE ,Indicates self refresh or self refresh power down state for LPDDR4" "SDRAM is not in self refresh,Self refresh 1,Self refresh power down,Self refresh 2" newline endif bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SDRAM's self-refresh type" "Not in self-refresh,,Self-refresh not only by autom.self-refr.,Self-refresh by autom.self-refr." newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self-refresh,Deep power-down,Deep power-down,Deep power-down,Deep power-down" else group.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" sif (!cpuis("IMX7DUAL-CM4")&&!cpuis("IMX7DUAL-CA7")) bitfld.long 0x00 8.--9. " SELFREF_STATE ,Indicates self refresh or self refresh power down state for LPDDR4" "SDRAM is not in self refresh,Self refresh 1,Self refresh power down,Self refresh 2" newline endif bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SDRAM's self-refresh type" "Not in self-refresh,,Self-refresh not only by autom.self-refr.,Self-refresh by autom.self-refr." newline bitfld.long 0x00 0.--1. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self-refresh" endif newline group.long 0x10++0x07 line.long 0x00 "MRCTRL0,Mode Register Read/write Control Register 0" bitfld.long 0x00 31. " MR_WR ,Triggers a mode register read or write operation" "Not triggered,Triggered" bitfld.long 0x00 12.--15. " MR_ADDR ,Address of the mode register that is to be written to" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x00 7. " MR_RANK[3] ,Controls rank 3 is accessed by MRCTRL0.MR_WR" "Not accessed,Accessed" newline bitfld.long 0x00 6. " MR_RANK[2] ,Controls rank 2 is accessed by MRCTRL0.MR_WR" "Not accessed,Accessed" bitfld.long 0x00 5. " MR_RANK[1] ,Controls rank 1 is accessed by MRCTRL0.MR_WR" "Not accessed,Accessed" newline bitfld.long 0x00 4. " MR_RANK[0] ,Controls rank 0 is accessed by MRCTRL0.MR_WR" "Not accessed,Accessed" bitfld.long 0x00 0. " MR_TYPE ,Indicates whether the mode register operation is read or write" "Write,Read" line.long 0x04 "MRCTRL1,Mode Register Read/write Control Register 1" hexmask.long.tbyte 0x04 0.--17. 1. " MR_DATA ,Mode register write data for all Non-LPDDR2 / Non-LPDDR3 modes" rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/write Status Register" bitfld.long 0x00 0. " MR_WR_BUSY ,Mode register write operation status" "Idle,Busy" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x20++0x07 line.long 0x00 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enable derating" "Disabled,Enabled" line.long 0x04 "DERATEINT,Temperature Derate Interval Register" group.long 0x30++0x07 line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Entered,Exited" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "Disabled,Enabled" bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Enable for deep power-down" "Disabled,Enabled" newline bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,T_DPD_X4096" bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x20++0x07 hide.long 0x00 "DERATEEN,Temperature Derate Enable Register" hide.long 0x04 "DERATEINT,Temperature Derate Interval Register" group.long 0x30++0x07 line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Entered,Exited" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "Disabled,Enabled" newline bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x38++0x03 line.long 0x00 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x00 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x00 1. " HW_LP_EXIT_IDLE_EN ,Enable for exit from the automatic clock stop, automatic power down or automatic self-refresh modes" "Disabled,Enabled" bitfld.long 0x00 0. " HW_LP_EN ,Enable for hardware low power interface" "Disabled,Enabled" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--8. " REFRESH_BURST ,The number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" newline sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "All bank refresh,Per bank refresh" else bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "Per bank refresh,All bank refresh" endif else group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--8. " REFRESH_BURST ,The number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" endif group.long 0x54++0x03 line.long 0x00 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer start for rank 1" hexmask.long.word 0x00 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer start for rank 0" group.long 0x60++0x03 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Indicates that the refresh Register(S) have been updated" "0,1" bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disables auto-refresh generated by the DDRC" "No,Yes" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x64++0x03 line.long 0x00 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" else hgroup.long 0x64++0x03 hide.long 0x00 "RFSHTMG,Refresh Timing Register" endif newline group.long 0xD0++0x03 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,SDRAM intialization routine" "Run after power-up,Skipped after power-up & Normal mode,Run after power-up,Skipped after power-up & Self-refresh mode" newline hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence" hexmask.long.word 0x00 0.--10. 1. " PRE_CKE_X1024 ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence" if (((per.l(ad:0x307A0000))&0x08)!=0x08) group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x00 16.--23. 1. " DRAM_RSTN_X1024 ,Number of cycles to assert SDRAM reset signal during init sequence" hexmask.long.byte 0x00 8.--14. 1. " FINAL_WAIT_X32 ,Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x00 8.--14. 1. " FINAL_WAIT_X32 ,Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0xD8++0x0F line.long 0x00 "INIT2,SDRAM Initialization Register 2" hexmask.long.byte 0x00 8.--15. 1. " IDLE_AFTER_RESET_X32 ,Idle time after the reset command" bitfld.long 0x00 0.--3. " MIN_STABLE_CLOCK_X1 ,Time to wait after the first CKE high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x04 16.--31. 1. " MR ,Value to write to MR1 register" hexmask.long.word 0x04 0.--15. 1. " EMR ,Value to write to MR2 register" line.long 0x08 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x08 16.--31. 1. " EMR2 ,Value to write to MR3 register" line.long 0x0C "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0C 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x0C 0.--9. 1. " MAX_AUTO_INIT_X1024 ,Maximum duration of the auto initialization" elif ((per.l(ad:0x307A0000)&0x01)==0x01) hgroup.long 0xD8++0x03 hide.long 0x00 "INIT2,SDRAM Initialization Register 2" group.long 0xDC++0x0B line.long 0x00 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value loaded into MR0 register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to MR1 register" line.long 0x04 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to MR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" line.long 0x08 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x08 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" else hgroup.long 0xD8++0x0F hide.long 0x00 "INIT2,SDRAM Initialization Register 2" hide.long 0x04 "INIT3,SDRAM Initialization Register 3" hide.long 0x08 "INIT4,SDRAM Initialization Register 4" hide.long 0x0C "INIT5,SDRAM Initialization Register 5" endif newline group.long 0xF4++0x03 line.long 0x00 "RANKCTL,Rank Control Register" bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP ,Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DIFF_RANK_RD_GAP ,Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0B line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif ((per.l(ad:0x307A0000)&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" else group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x110++0x07 line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5,SDRAM Timing Register5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x118++0x07 line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,Time before deep power down exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,Time after power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x118++0x07 hide.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" hide.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" endif group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" newline if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x180++0x0B line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disables DDRC generation of ZQCS command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disables issuing of ZQCL command at Self-Refresh exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,Sharing ZQ resistor between ranks" "Not shared,Shared" hexmask.long.word 0x00 16.--25. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" newline hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" line.long 0x04 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x04 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset (ZQ calibration reset) command is issued to SDRAM" hexmask.long.tbyte 0x04 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" line.long 0x08 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x08 0. " ZQ_RESET ,ZQ reset" "No reset,Reset" rgroup.long 0x18C++0x0B line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset operation initialization by soc core" "Possibility of initialization,In progress" elif ((per.l(ad:0x307A0000)&0x01)==0x01) group.long 0x180++0x07 line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disables DDRC generation of ZQCS command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disables issuing of ZQCL command at Self-Refresh exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,Sharing ZQ resistor between ranks" "Not shared,Shared between ranks" hexmask.long.word 0x00 16.--25. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" newline hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" line.long 0x04 "ZQCTL1,ZQ Control Register 1" hexmask.long.tbyte 0x04 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" hgroup.long 0x188++0x07 hide.long 0x00 "ZQCTL2,ZQ Control Register 2" hide.long 0x04 "ZQSTAT,ZQ Status Register" else hgroup.long 0x180++0x0F hide.long 0x00 "ZQCTL0,ZQ Control Register 0" newline newline hide.long 0x04 "ZQCTL1,ZQ Control Register 1" hide.long 0x08 "ZQCTL2,ZQ Control Register 2" hide.long 0x0C "ZQSTAT,ZQ Status Register" endif newline group.long 0x190++0x07 line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_T_RDDATA_EN is in terms of SDR or HDR clock cycles" "HDR,SDR" bitfld.long 0x00 16.--21. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_TPHY_WRLAT is in terms of SDR or HDR clock cycles" "HDR,SDR" bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clocks between when the DFI_WRDATA_EN signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--11. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x307A0000))&0x0C)!=0x00) group.long 0x198++0x03 line.long 0x00 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x00 24.--27. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " DFI_LP_WAKEUP_DPD ,Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" bitfld.long 0x00 16. " DFI_LP_EN_DPD ,Enables DFI low power interface handshaking during deep power down entry/exit" "Disabled,Enabled" newline bitfld.long 0x00 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" bitfld.long 0x00 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" bitfld.long 0x00 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" else group.long 0x198++0x03 line.long 0x00 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x00 24.--27. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" bitfld.long 0x00 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" bitfld.long 0x00 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" endif group.long 0x1A0++0x13 line.long 0x00 "DFIUPD0,DFI Update Register 0" bitfld.long 0x00 31. " DIS_AUTO_CTRLUPD ,Disables the automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x00 30. " DIS_AUTO_CTRLUPD_SRX ,Disables the automatic dfi_ctrlupd_req generation by the DDRC following a self-refresh exit" "No,Yes" newline hexmask.long.word 0x00 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" hexmask.long.word 0x00 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x04 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x04 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x04 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x08 "DFIUPD2,DFI Update Register 2" bitfld.long 0x08 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" hexmask.long.word 0x08 16.--27. 1. " DFI_PHYUPD_TYPE1 ,Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01" newline hexmask.long.word 0x08 0.--11. 1. " DFI_PHYUPD_TYPE0 ,Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00" line.long 0x0C "DFIUPD3,DFI Update Register 3" hexmask.long.word 0x0C 16.--27. 1. " DFI_PHYUPD_TYPE3 ,Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11" hexmask.long.word 0x0C 0.--11. 1. " DFI_PHYUPD_TYPE2 ,Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10" line.long 0x10 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x10 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" newline group.long 0x200++0x17 line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 8.--12. " ADDRMAP_CS_BIT1 ,Selects the HIF address bit used as rank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,,,,,31" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,,,,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,ADDRMAP_COL_B5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,ADDRMAP_COL_B4" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,ADDRMAP_COL_B3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,ADDRMAP_COL_B2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,ADDRMAP_COL_B9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,ADDRMAP_COL_B8" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,ADDRMAP_COL_B7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,ADDRMAP_COL_B6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,ADDRMAP_COL_B11" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,ADDRMAP_COL_B10" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Selects the HIF address bit used as row address bit 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." if ((per.l(ad:0x307A0000)&0x08)==0x08) group.long 0x218++0x03 line.long 0x00 "ADDRMAP6,Address Map Register 6" bitfld.long 0x00 31. " LPDDR3_6GB_12GB ,LPDDR3 SDRAM 6 gb or 12 gb device in use" "Non-LPDDR3,LPDDR3" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" else group.long 0x218++0x03 line.long 0x00 "ADDRMAP6,Address Map Register 6" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" endif group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,Cycles to hold ODT for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,Cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/rank Map Register" bitfld.long 0x04 12.--15. " RANK1_RD_ODT ,Indicates which remote ODTs must be turned on during a read from rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RANK1_WR_ODT ,Indicates which remote ODTs must be turned on during a write to rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " RANK0_RD_ODT ,Indicates which remote ODTs must be turned on during a read from rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " RANK0_WR_ODT ,Indicates which remote ODTs must be turned on during a write to rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty" bitfld.long 0x00 8.--13. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "Reads over writes,Writes over reads" newline bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Low priority for incoming transactions" "Forced,Not forced" if ((per.l(ad:0x307A0000+0x250)&0x04)==0x04) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" else hgroup.long 0x254++0x03 hide.long 0x00 "SCHED1,Scheduler Control Register 1" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of clocks that the WR queue can be starved before it goes critical" group.long 0x274++0x07 line.long 0x00 "PERFVPR1,Variable Priority Read CAM Register 1" hexmask.long.word 0x00 0.--10. 1. " VPR_TIMEOUT_RANGE ,Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC" line.long 0x04 "PERFVPW1,Variable Priority Write CAM Register 1" hexmask.long.word 0x04 0.--10. 1. " VPW_TIMEOUT_RANGE ,Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC" newline group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x13 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" newline bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" newline bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" hexmask.long.byte 0x00 16.--22. 1. " DBG_W_Q_DEPTH ,Write queue depth" hexmask.long.byte 0x00 8.--14. 1. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" newline hexmask.long.byte 0x00 0.--6. 1. " DBG_HPR_Q_DEPTH ,High priority read queue depth" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,ZQ calibration" newline bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" newline bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "Not done,Done" width 0x0B tree.end tree "DDRC_MP (DDRMC Multi Port)" base ad:0x307A0000 width 19. rgroup.long 0x3FC++0x03 line.long 0x00 "PSTAT,Port Status Register" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for port 0" "No reads,Reads" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" bitfld.long 0x00 0. " GO2CRITICAL_EN ,Go2critical enable" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port N Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enable the page match feature" "Disabled,Enabled" bitfld.long 0x04 13. " RD_PORT_URGENT_EN ,Enable the AXI urgent sideband signal" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enable aging function for the read channel of the port" "Disabled,Enabled" bitfld.long 0x04 11. " READ_REORDER_BYPASS_EN ,Read transactions with ID not covered by any of the virtual channel ID mapping registers are not reordered" "Disabled,Enabled" hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port N Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enable the page match feature" "Disabled,Enabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enable the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enable aging function for the write channel of the port" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x410++0x07 line.long 0x00 "PCFGIDMASKCH_0,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_0,Port N Channel M Configuration ID Value Register" group.long 0x418++0x07 line.long 0x00 "PCFGIDMASKCH_10,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_10,Port N Channel M Configuration ID Value Register" group.long 0x420++0x07 line.long 0x00 "PCFGIDMASKCH_20,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_20,Port N Channel M Configuration ID Value Register" group.long 0x428++0x07 line.long 0x00 "PCFGIDMASKCH_30,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_30,Port N Channel M Configuration ID Value Register" group.long 0x430++0x07 line.long 0x00 "PCFGIDMASKCH_40,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_40,Port N Channel M Configuration ID Value Register" group.long 0x438++0x07 line.long 0x00 "PCFGIDMASKCH_50,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_50,Port N Channel M Configuration ID Value Register" group.long 0x440++0x07 line.long 0x00 "PCFGIDMASKCH_60,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_60,Port N Channel M Configuration ID Value Register" group.long 0x448++0x07 line.long 0x00 "PCFGIDMASKCH_70,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_70,Port N Channel M Configuration ID Value Register" group.long 0x450++0x07 line.long 0x00 "PCFGIDMASKCH_80,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_80,Port N Channel M Configuration ID Value Register" group.long 0x458++0x07 line.long 0x00 "PCFGIDMASKCH_90,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_90,Port N Channel M Configuration ID Value Register" group.long 0x460++0x07 line.long 0x00 "PCFGIDMASKCH_100,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_100,Port N Channel M Configuration ID Value Register" group.long 0x468++0x07 line.long 0x00 "PCFGIDMASKCH_110,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_110,Port N Channel M Configuration ID Value Register" group.long 0x470++0x07 line.long 0x00 "PCFGIDMASKCH_120,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_120,Port N Channel M Configuration ID Value Register" group.long 0x478++0x07 line.long 0x00 "PCFGIDMASKCH_130,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_130,Port N Channel M Configuration ID Value Register" group.long 0x480++0x07 line.long 0x00 "PCFGIDMASKCH_140,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_140,Port N Channel M Configuration ID Value Register" group.long 0x488++0x07 line.long 0x00 "PCFGIDMASKCH_150,Port N Channel M Configuration ID Mask Register" line.long 0x04 "PCFGIDVALUECH_150,Port N Channel M Configuration ID Value Register" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port N Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port N Read QoS Configuration Register 0" bitfld.long 0x04 24.--25. " RQOS_MAP_REGION2 ,Indicates the traffic class of region2" ",VPR,HPR,?..." bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,Indicates the traffic class of region 0" "LPR,VPR,HPR,?..." textline " " bitfld.long 0x04 8.--11. " RQOS_MAP_LEVEL2 ,Separation level2 indicating the end of region1 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." line.long 0x08 "PCFGQOS1_0,Port N Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port N Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,Indicates the traffic class of region 0" "NPW,VPW,?..." bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x10 "PCFGWQOS1_0,Port N Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" group.long 0xF04++0x07 line.long 0x00 "SARBASE0,SAR Base Address Register 0" line.long 0x04 "SARSIZE0,SAR Size Register 0" hexmask.long.byte 0x04 0.--7. 1. " NBLOCKS ,Number of blocks for address region 0" group.long 0xF0C++0x07 line.long 0x00 "SARBASE1,SAR Base Address Register 1" line.long 0x04 "SARSIZE1,SAR Size Register 1" hexmask.long.byte 0x04 0.--7. 1. " NBLOCKS ,Number of blocks for address region 1" group.long 0xF14++0x07 line.long 0x00 "SARBASE2,SAR Base Address Register 2" line.long 0x04 "SARSIZE2,SAR Size Register 2" hexmask.long.byte 0x04 0.--7. 1. " NBLOCKS ,Number of blocks for address region 2" group.long 0xF1C++0x07 line.long 0x00 "SARBASE3,SAR Base Address Register 3" line.long 0x04 "SARSIZE3,SAR Size Register 3" hexmask.long.byte 0x04 0.--7. 1. " NBLOCKS ,Number of blocks for address region 3" width 0x0B tree.end tree.end tree "DDRP (DDR PHY)" base ad:0x30790000 width 17. group.long 0x00++0x13 line.long 0x00 "PHY_CON0,DDR_PHY_PHY_CON0" bitfld.long 0x00 22.--23. " CTRL_UPD_MODE ,Controls when DLL is updated" "Always,Depending on ctrl_flock,Depending on ctrl_flock,Not updated" bitfld.long 0x00 20.--21. " CTRL_UPD_RANGE ,Decides how many differences between the new lock value and the current lock value are needed for updating lock value" "More than 0,More than 1,More than 7,More than 15" bitfld.long 0x00 16. " WRLVL_MODE ,Write leveling mode enable" "Disabled,Enabled" newline bitfld.long 0x00 11.--12. " CTRL_DDR_MODE ,CTRL_DDR mode" ",DDR3,LPDDR2,LPDDR3" bitfld.long 0x00 9. " CTRL_DFDQS ,CTRL_DFDQS" "Single-ended DQS,Differential DQS" bitfld.long 0x00 8. " CTRL_SHGATE ,Gate signal length" "(Burst length/2)+n,(Burst length/2)-1" newline bitfld.long 0x00 6. " CTRL_ATGATE ,CTRL_ATGATE" "0,1" bitfld.long 0x00 4. " CTRL_CMOSRCV ,Controls the input mode of I/O" "0,1" bitfld.long 0x00 3. " CTRL_TWPRE ,Write preamble setting" "0,1" newline bitfld.long 0x00 0.--2. " CTRL_FNC_FB ,CTRL_FNC_FB" "Normal operation mode,,External FNC read feedback test mode,Internal FNC read feedback test mode,External PHY read feedback test mode,Internal PHY read feedback test mode,Internal PHY write feedback test mode,?..." line.long 0x04 "PHY_CON1,DDR_PHY_PHY_CON1" bitfld.long 0x04 28.--31. " CTRL_GATEADJ ,Adjust enable time of ctrl_gate on a clock cycle base" "+0,+1,+2,+3,+4,+5,+6,+7,-0,-1,-2,-3,-4,-5,-6,-7" bitfld.long 0x04 20.--23. " CTRL_GATEDURADJ ,Adjust duration cycle of ctrl_gate on a clock cycle base" "+0,+1,+2,+3,+4,+5,+6,+7,-0,-1,-2,-3,-4,-5,-6,-7" newline bitfld.long 0x04 31. " CTRL_GATEADJ[31] ,Adjusts the enable time of ctrl_gate on a clock cycle base controls direction" "Add delay,Subtract delay" bitfld.long 0x04 28.--30. " CTRL_GATEADJ[30:28] ,Adjusts the enable time of ctrl_gate on a clock cycle base sets delay value" "0,1,2,3,4,5,6,7" bitfld.long 0x04 23. " CTRL_GATEDURADJ[23] ,Adjusts the duration cycle of ctrl_gate on a clock cycle base controls direction" "Add delay,Subtract delay" newline bitfld.long 0x04 20.--22. " CTRL_GATEDURADJ[22:20] ,Adjusts the duration cycle of ctrl_gate on a clock cycle base sets delay value" "0,1,2,3,4,5,6,7" line.long 0x08 "PHY_CON2,DDR_PHY_PHY_CON2" bitfld.long 0x08 24. " GATE_CAL_MODE ,GATE_CAL_MODE" "CTRL_SHIFTC*,Gate leveling" bitfld.long 0x08 14. " WRDESKEW_CLEAR ,Write ctrl_offsetw* to WrDeSkewCode" "No effect,Clear" bitfld.long 0x08 13. " RDDESKEW_CLEAR ,Clear ctrl_offsetr* to RdDeSkewCode" "No effect,Clear" line.long 0x0C "PHY_CON3,DDR_PHY_PHY_CON3" bitfld.long 0x0C 27. " WL_CAL_RESP ,Response after write leveling calibration" "No response,Response" bitfld.long 0x0C 24. " WRLVL_RESP ,Response after write leveling" "No response,Response" bitfld.long 0x0C 21. " WL_CAL_START ,Start write leveling calibration" "No effect,Start" newline bitfld.long 0x0C 20. " WL_CAL_MODE ,Write leveling calibration mode enable" "Disabled,Enabled" bitfld.long 0x0C 16. " WRLVL_START ,Start write leveling signal" "No effect,Start" hexmask.long.byte 0x0C 0.--7. 1. " REG_MODE ,Register mode control to write the information at each data" line.long 0x10 "PHY_CON4,DDR_PHY_PHY_CON4" bitfld.long 0x10 16.--20. " CTRL_WRLAT ,Clock cycles between write command and the first edge of DQS which can capture the first valid DQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " CTRL_BSTLEN ,Burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " CTRL_RDLAT ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x30790000+0x0C)&0x100000)==0x100000) rgroup.long 0x14++0x03 line.long 0x00 "PHY_CON5,DDR_PHY_PHY_CON5" bitfld.long 0x00 9.--11. " CTRL_WRLAT_PLUS3 ,Controls write latency increase for data_slice3" "Half clock cycle,One clock cycle,Two clock cycle,?..." bitfld.long 0x00 6.--8. " CTRL_WRLAT_PLUS2 ,Controls write latency increase for data_slice2" "Half clock cycle,One clock cycle,Two clock cycle,?..." bitfld.long 0x00 3.--5. " CTRL_WRLAT_PLUS1 ,Controls write latency increase for data_slice1" "Half clock cycle,One clock cycle,Two clock cycle,?..." newline bitfld.long 0x00 0.--2. " CTRL_WRLAT_PLUS0 ,Controls write latency increase for data_slice0" "Half clock cycle,One clock cycle,Two clock cycle,?..." else group.long 0x14++0x03 line.long 0x00 "PHY_CON5,DDR_PHY_PHY_CON5" bitfld.long 0x00 9.--11. " CTRL_WRLAT_PLUS3 ,Controls write latency increase for data_slice3" "Half clock cycle,One clock cycle,Two clock cycle,?..." bitfld.long 0x00 6.--8. " CTRL_WRLAT_PLUS2 ,Controls write latency increase for data_slice2" "Half clock cycle,One clock cycle,Two clock cycle,?..." bitfld.long 0x00 3.--5. " CTRL_WRLAT_PLUS1 ,Controls write latency increase for data_slice1" "Half clock cycle,One clock cycle,Two clock cycle,?..." newline bitfld.long 0x00 0.--2. " CTRL_WRLAT_PLUS0 ,Controls write latency increase for data_slice0" "Half clock cycle,One clock cycle,Two clock cycle,?..." endif newline group.long 0x18++0x0B line.long 0x00 "LP_CON0,DDR_PHY_LP_CON0" hexmask.long.word 0x00 16.--24. 1. " CTRL_PULLD_DQ ,Control pull-down DQ signals" hexmask.long.word 0x00 0.--8. 1. " CTRL_PULLD_DQS ,Control pull-down PDQS/ NDQS signals" line.long 0x04 "RODT_CON0,DDR_PHY_RODT_CON0" bitfld.long 0x04 16. " CTRL_READ_DIS ,Read ODT (On-die-termination) disable signal" "No,Yes" line.long 0x08 "OFFSET_RD_CON0,DDR_PHY_OFFSET_RD_CON0" hexmask.long.byte 0x08 24.--31. 1. " CTRL_OFFSETR3 ,Gives offset to read DQS" hexmask.long.byte 0x08 16.--23. 1. " CTRL_OFFSETR2 ,Gives offset to read DQS" hexmask.long.byte 0x08 8.--15. 1. " CTRL_OFFSETR1 ,Gives offset to read DQS" hexmask.long.byte 0x08 0.--7. 1. " CTRL_OFFSETR0 ,Gives offset to read DQS" group.long 0x30++0x03 line.long 0x00 "OFFSET_WR_CON0,DDR_PHY_OFFSET_WR_CON0" hexmask.long.byte 0x00 24.--31. 1. " CTRL_OFFSETW3 ,Gives offset to write DQS" hexmask.long.byte 0x00 16.--23. 1. " CTRL_OFFSETW2 ,Gives offset to write DQS" hexmask.long.byte 0x00 8.--15. 1. " CTRL_OFFSETW1 ,Gives offset to write DQS" hexmask.long.byte 0x00 0.--7. 1. " CTRL_OFFSETW0 ,Gives offset to write DQS" group.long 0x40++0x03 line.long 0x00 "GATE_CODE_CON0,DDR_PHY_GATE_CODE_CON0" hexmask.long.byte 0x00 24.--31. 1. " CTRL_OFFSETC3 ,Gate offset amount for DDR3 data slice 3" hexmask.long.byte 0x00 16.--23. 1. " CTRL_OFFSETC2 ,Gate offset amount for DDR3 data slice 2" hexmask.long.byte 0x00 8.--15. 1. " CTRL_OFFSETC1 ,Gate offset amount for DDR3 data slice 1" hexmask.long.byte 0x00 0.--7. 1. " CTRL_OFFSETC0 ,Gate offset amount for DDR3 data slice 0" group.long 0x4C++0x07 line.long 0x00 "SHIFTC_CON0,DDR_PHY_SHIFTC_CON0" bitfld.long 0x00 9.--11. " CTRL_SHIFTC3 ,GATEin signal delay amount for DDR" "0,T,T/2,T/4,T/8,T/16,?..." bitfld.long 0x00 6.--8. " CTRL_SHIFTC2 ,GATEin signal delay amount for DDR" "0,T,T/2,T/4,T/8,T/16,?..." bitfld.long 0x00 3.--5. " CTRL_SHIFTC1 ,GATEin signal delay amount for DDR" "0,T,T/2,T/4,T/8,T/16,?..." bitfld.long 0x00 0.--2. " CTRL_SHIFTC0 ,GATEin signal delay amount for DDR" "0,T,T/2,T/4,T/8,T/16,?..." line.long 0x04 "CMD_SDLL_CON0,DDR_PHY_CMD_SDLL_CON0" bitfld.long 0x04 28. " UPD_MODE ,Controls PHY update mode" "PHY-initiated,MC-initiated" bitfld.long 0x04 24. " CTRL_RESYNC ,CTRL_RESYNC" "0,1" hexmask.long.byte 0x04 0.--7. 1. " CTRL_OFFSETD ,CTRL_OFFSETD" group.long 0x6C++0x03 line.long 0x00 "LVL_CON0,DDR_PHY_LVL_CON0" hexmask.long.byte 0x00 24.--31. 1. " CTRL_WRLV13_CODE ,Write level slave DLL code value for data_slice 3" hexmask.long.byte 0x00 16.--23. 1. " CTRL_WRLV12_CODE ,Write level slave DLL code value for data_slice 2" hexmask.long.byte 0x00 8.--15. 1. " CTRL_WRLV11_CODE ,Write level slave DLL code value for data_slice 1" hexmask.long.byte 0x00 0.--7. 1. " CTRL_WRLV10_CODE ,Write level slave DLL code value for data_slice 0" group.long 0x78++0x13 line.long 0x00 "LVL_CON3,DDR_PHY_LVL_CON3" bitfld.long 0x00 0. " CTRL_WRLVL_RESYNC ,Write level DLL code update enable" "Disabled,Enabled" line.long 0x04 "CMD_DESKEW_CON0,DDR_PHY_CMD_DESKEW_CON0" hexmask.long.byte 0x04 24.--31. 1. " CA3DESKEWCODE ,Deskew code for CA[3]" hexmask.long.byte 0x04 16.--23. 1. " CA2DESKEWCODE ,Deskew code for CA[2]" hexmask.long.byte 0x04 8.--15. 1. " CA1DESKEWCODE_1 ,Deskew code for CA[1]" hexmask.long.byte 0x04 0.--7. 1. " CA1DESKEWCODE_0 ,Deskew code for CA[0]" line.long 0x08 "CMD_DESKEW_CON1,DDR_PHY_CMD_DESKEW_CON1" hexmask.long.byte 0x08 24.--31. 1. " CA7DESKEWCODE ,Deskew code for CA[7]" hexmask.long.byte 0x08 16.--23. 1. " CA6DESKEWCODE ,Deskew code for CA[6]" hexmask.long.byte 0x08 8.--15. 1. " CA5DESKEWCODE ,Deskew code for CA[5]" hexmask.long.byte 0x08 0.--7. 1. " CA4DESKEWCODE ,Deskew code for CA[4]" line.long 0x0C "CMD_DESKEW_CON2,DDR_PHY_CMD_DESKEW_CON2" hexmask.long.byte 0x0C 24.--31. 1. " CS0DESKEWCODE ,Deskew code for CS0" hexmask.long.byte 0x0C 16.--23. 1. " CKDESKEWCODE ,Deskew code for CK" hexmask.long.byte 0x0C 8.--15. 1. " CA9DESKEWCODE ,Deskew code for CA[9]" hexmask.long.byte 0x0C 0.--7. 1. " CA8DESKEWCODE ,Deskew code for CA[8]" line.long 0x10 "CMD_DESKEW_CON3,DDR_PHY_CMD_DESKEW_CON3" hexmask.long.byte 0x10 16.--23. 1. " CKE1DESKEWCODE ,Deskew code for CKE1" hexmask.long.byte 0x10 8.--15. 1. " CKE0DESKEWCODE ,Deskew code for CKE0" hexmask.long.byte 0x10 0.--7. 1. " CS1DESKEWCODE ,Deskew code for CS1" group.long 0x94++0x03 line.long 0x00 "CMD_DESKEW_CON4,DDR_PHY_CMD_DESKEW_CON4" hexmask.long.byte 0x00 0.--7. 1. " RSTDESKEWCODE ,Deskew code for RST" group.long 0x9C++0x03 line.long 0x00 "DRVDS_CON0,DDR_PHY_DRVDS_CON0" bitfld.long 0x00 9.--11. " CACKDRVRDS ,Output driver's impedence for CK" ",,,,48 Ohm,40 Ohm,34 Ohm,30 Ohm" bitfld.long 0x00 6.--8. " CACKEDRVRDS ,Output driver's impedence for CKE" ",,,,48 Ohm,40 Ohm,34 Ohm,30 Ohm" bitfld.long 0x00 3.--5. " CACSDRVRDS ,Output driver's impedence for CS" ",,,,48 Ohm,40 Ohm,34 Ohm,30 Ohm" bitfld.long 0x00 0.--2. " CAADRDRVRDS ,Output driver's impedence for CA|RAS|CAS|WEN|ODT|RESET|BANK" ",,,,48 Ohm,40 Ohm,34 Ohm,30 Ohm" if ((per.l(ad:0x30790000+0xB0)&0x20)==0x00) group.long 0xB0++0x03 line.long 0x00 "MDLL_CON0,DDR_PHY_MDLL_CON0" hexmask.long.byte 0x00 24.--30. 1. " CTRL_START_POINT ,Initial DLL lock start point" hexmask.long.byte 0x00 16.--22. 1. " CTRL_INC ,Increase amount of start point" hexmask.long.word 0x00 7.--15. 1. " CTRL_FORCE ,Generates 270 deg clock and shift DQS by 90 deg" newline bitfld.long 0x00 6. " CTRL_START ,Starts DLL locking" "No locking,Locking" bitfld.long 0x00 5. " CTRL_DLL_ON ,Starts signal to turn on the DLL" "Turned off,Turned on" bitfld.long 0x00 1.--4. " CTRL_REF ,Determines the period of time when ctrl_locked is cleared" "Do not use,16 clock cycles,24 clock cycles,,,,,,,,,,,,120 clock cycles,After rst_n assertion" else group.long 0xB0++0x03 line.long 0x00 "MDLL_CON0,DDR_PHY_MDLL_CON0" hexmask.long.byte 0x00 24.--30. 1. " CTRL_START_POINT ,Initial DLL lock start point" hexmask.long.byte 0x00 16.--22. 1. " CTRL_INC ,Increase amount of start point" newline bitfld.long 0x00 6. " CTRL_START ,Starts DLL locking" "No locking,Locking" bitfld.long 0x00 5. " CTRL_DLL_ON ,Starts signal to turn on the DLL" "Turned off,Turned on" bitfld.long 0x00 1.--4. " CTRL_REF ,Determines the period of time when ctrl_locked is cleared" "Do not use,16 clock cycles,24 clock cycles,,,,,,,,,,,,120 clock cycles,After rst_n assertion" endif group.long 0xB4++0x03 line.long 0x00 "MDLL_CON1,DDR_PHY_MDLL_CON1" hexmask.long.word 0x00 8.--16. 1. " CTRL_LOCK_VALUE ,Defines the number of fine steps to be used for one clock period" bitfld.long 0x00 1.--2. " CTRL_FLOCK&CTRL_CLOCK ,Fine lock information & coarse lock information" "DLL is not locked,,Locked,Locked" bitfld.long 0x00 0. " CTRL_LOCKED ,DLL stable lock information" "Not locked,Locked" group.long 0xC0++0x0B line.long 0x00 "ZQ_CON0,DDR_PHY_ZQ_CON0" bitfld.long 0x00 27. " ZQ_CLK_EN ,ZQ I/O clock enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " ZQ_MODE_DDS ,Output driver's impedance" ",,,,48 Ohm,40 Ohm,34 Ohm,30 Ohm" bitfld.long 0x00 21.--23. " ZQ_MODE_TERM ,On-die-termination (ODT) resistor value" ",120 Ohm,60 Ohm,40 Ohm,30 Ohm,?..." bitfld.long 0x00 19. " ZQ_MODE_NOTERM ,Termination disable selection" "No,Yes" newline bitfld.long 0x00 18. " ZQ_CLK_DIV_EN ,Clock dividing enable" "Disabled,Enabled" bitfld.long 0x00 15.--17. " ZQ_FORCE_IMPN ,Immediate control code for pull-down" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " ZQ_FORCE_IMPP ,Immediate control code for pull-up" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 4.--11. 1. " ZQ_UDT_DLY ,ZQ I/O clock enable duration for auto calibration mode" newline bitfld.long 0x00 2.--3. " ZQ_MANUAL_MODE ,Manual calibration mode selection" "Force,Long,Short,?..." bitfld.long 0x00 1. " ZQ_MANUAL_STR ,Manual calibration start" "No effect,Start" bitfld.long 0x00 0. " ZQ_AUTO_EN ,Auto calibration enable" "Disabled,Enabled" line.long 0x04 "ZQ_CON1,DDR_PHY_ZQ_CON1" bitfld.long 0x04 6.--8. " ZQ_PMON ,Control code found by auto calibration for pull-up" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " ZQ_NMON ,Control code found by auto calibration for pull-down" "0,1,2,3,4,5,6,7" bitfld.long 0x04 2. " ZQ_ERROR ,Calibration fail indication" "Not failed,Failed" newline bitfld.long 0x04 1. " ZQ_PENDING ,Auto calibration enable status" "Disabled,Enabled" bitfld.long 0x04 0. " ZQ_DONE ,ZQ calibration is finished" "In progress,Finished" line.long 0x08 "ZQ_CON2,DDR_PHY_ZQ_CON2" hexmask.long.word 0x08 0.--15. 1. " CTRL_ZQ_CLK_DIV ,ZQ clock divider setting value" newline rgroup.long 0x190++0x03 line.long 0x00 "RD_DESKEW_CON0,DDR_PHY_RD_DESKEW_CON0" hexmask.long.byte 0x00 24.--31. 1. " RD0DESKEW3 ,Read DQ24 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD0DESKEW2 ,Read DQ16 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD0DESKEW1 ,Read DQ8 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD0DESKEW0 ,Read DQ0 De-Skew code" rgroup.long 0x19C++0x03 line.long 0x00 "RD_DESKEW_CON3,DDR_PHY_RD_DESKEW_CON3" hexmask.long.byte 0x00 24.--31. 1. " RD1DESKEW3 ,Read DQ25 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD1DESKEW2 ,Read DQ17 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD1DESKEW1 ,Read DQ9 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD1DESKEW0 ,Read DQ1 De-Skew code" rgroup.long 0x1A8++0x03 line.long 0x00 "RD_DESKEW_CON6,DDR_PHY_RD_DESKEW_CON6" hexmask.long.byte 0x00 24.--31. 1. " RD2DESKEW3 ,Read DQ26 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD2DESKEW2 ,Read DQ18 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD2DESKEW1 ,Read DQ10 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD2DESKEW0 ,Read DQ2 De-Skew code" rgroup.long 0x1B4++0x03 line.long 0x00 "RD_DESKEW_CON9,DDR_PHY_RD_DESKEW_CON9" hexmask.long.byte 0x00 24.--31. 1. " RD3DESKEW3 ,Read DQ27 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD3DESKEW2 ,Read DQ19 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD3DESKEW1 ,Read DQ11 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD3DESKEW0 ,Read DQ3 De-Skew code" rgroup.long 0x1C0++0x03 line.long 0x00 "RD_DESKEW_CON12,DDR_PHY_RD_DESKEW_CON12" hexmask.long.byte 0x00 24.--31. 1. " RD4DESKEW3 ,Read DQ28 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD4DESKEW2 ,Read DQ20 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD4DESKEW1 ,Read DQ12 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD4DESKEW0 ,Read DQ4 De-Skew code" rgroup.long 0x1CC++0x03 line.long 0x00 "RD_DESKEW_CON15,DDR_PHY_RD_DESKEW_CON15" hexmask.long.byte 0x00 24.--31. 1. " RD5DESKEW3 ,Read DQ29 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD5DESKEW2 ,Read DQ21 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD5DESKEW1 ,Read DQ13 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD5DESKEW0 ,Read DQ5 De-Skew code" rgroup.long 0x1D8++0x03 line.long 0x00 "RD_DESKEW_CON18,DDR_PHY_RD_DESKEW_CON18" hexmask.long.byte 0x00 24.--31. 1. " RD6DESKEW3 ,Read DQ30 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD6DESKEW2 ,Read DQ22 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD6DESKEW1 ,Read DQ14 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD6DESKEW0 ,Read DQ6 De-Skew code" rgroup.long 0x1E4++0x03 line.long 0x00 "RD_DESKEW_CON21,DDR_PHY_RD_DESKEW_CON21" hexmask.long.byte 0x00 24.--31. 1. " RD7DESKEW3 ,Read DQ31 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " RD7DESKEW2 ,Read DQ23 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " RD7DESKEW1 ,Read DQ17 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " RD7DESKEW0 ,Read DQ7 De-Skew code" group.long 0x1F0++0x03 line.long 0x00 "WR_DESKEW_CON0,DDR_PHY_WR_DESKEW_CON0" hexmask.long.byte 0x00 24.--31. 1. " WR0DESKEW3 ,Write DQ24 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " WR0DESKEW2 ,Write DQ16 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " WR0DESKEW1 ,Write DQ8 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " WR0DESKEW0 ,Write DQ0 De-Skew code" group.long 0x1FC++0x03 line.long 0x00 "WR_DESKEW_CON3,DDR_PHY_WR_DESKEW_CON3" hexmask.long.byte 0x00 24.--31. 1. " WR1DESKEW3 ,Write DQ25 De-Skew code" hexmask.long.byte 0x00 16.--23. 1. " WR1DESKEW2 ,Write DQ17 De-Skew code" hexmask.long.byte 0x00 8.--15. 1. " WR1DESKEW1 ,Write DQ9 De-Skew code" hexmask.long.byte 0x00 0.--7. 1. " WR1DESKEW0 ,Write DQ1 De-Skew code" group.long 0x208++0x03 line.long 0x00 "WR_DESKEW_CON6,DDR_PHY_WR_DESKEW_CON6" hexmask.long.byte 0x00 24.--31. 1. " WR2DESKEW3 ,Write DQ2 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR2DESKEW2 ,Write DQ2 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR2DESKEW1 ,Write DQ2 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " WR2DESKEW0 ,Write DQ2 De-Skew code for data slice0" group.long 0x214++0x03 line.long 0x00 "WR_DESKEW_CON9,DDR_PHY_WR_DESKEW_CON9" hexmask.long.byte 0x00 24.--31. 1. " WR3DESKEW3 ,Write DQ3 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR3DESKEW2 ,Write DQ3 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR3DESKEW1 ,Write DQ3 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " WR3DESKEW0 ,Write DQ3 De-Skew code for data slice0" group.long 0x220++0x03 line.long 0x00 "WR_DESKEW_CON12,DDR_PHY_WR_DESKEW_CON12" hexmask.long.byte 0x00 24.--31. 1. " WR4DESKEW3 ,Write DQ4 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR4DESKEW2 ,Write DQ4 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR4DESKEW1 ,Write DQ4 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " WR4DESKEW0 ,Write DQ4 De-Skew code for data slice0" group.long 0x22C++0x03 line.long 0x00 "WR_DESKEW_CON15,DDR_PHY_WR_DESKEW_CON15" hexmask.long.byte 0x00 24.--31. 1. " WR5DESKEW3 ,Write DQ5 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR5DESKEW2 ,Write DQ5 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR5DESKEW1 ,Write DQ5 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " WR5DESKEW0 ,Write DQ5 De-Skew code for data slice0" group.long 0x238++0x03 line.long 0x00 "WR_DESKEW_CON18,DDR_PHY_WR_DESKEW_CON18" hexmask.long.byte 0x00 24.--31. 1. " WR6DESKEW3 ,Write DQ6 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR6DESKEW2 ,Write DQ6 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR6DESKEW1 ,Write DQ6 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " RD6DESKEW0 ,Read DQ6 De-Skew code for data slice0" group.long 0x244++0x03 line.long 0x00 "WR_DESKEW_CON21,DDR_PHY_WR_DESKEW_CON21" hexmask.long.byte 0x00 24.--31. 1. " WR7DESKEW3 ,Write DQ7 De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " WR7DESKEW2 ,Write DQ7 De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " WR7DESKEW1 ,Write DQ7 De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " WR7DESKEW0 ,Write DQ7 De-Skew code for data slice0" group.long 0x250++0x03 line.long 0x00 "DM_DESKEW_CON,DDR_PHY_DM_DESKEW_CON" hexmask.long.byte 0x00 24.--31. 1. " DMDESKEW3 ,Write DM De-Skew code for data slice3" hexmask.long.byte 0x00 16.--23. 1. " DMDESKEW2 ,Write DM De-Skew code for data slice2" hexmask.long.byte 0x00 8.--15. 1. " DMDESKEW1 ,Write DM De-Skew code for data slice1" hexmask.long.byte 0x00 0.--7. 1. " DMDESKEW0 ,Write DM De-Skew code for data slice0" rgroup.long 0x3A0++0x03 line.long 0x00 "RDATA0,DDR_PHY_RDATA0" hexmask.long.byte 0x00 24.--31. 1. " DQ_IO_RD3 ,DQ I/O read data for DS3" hexmask.long.byte 0x00 16.--23. 1. " DQ_IO_RD2 ,DQ I/O read data for DS2" hexmask.long.byte 0x00 8.--15. 1. " DQ_IO_RD1 ,DQ I/O read data for DS1" hexmask.long.byte 0x00 0.--7. 1. " DQ_IO_RD0 ,DQ I/O read data for DS0" rgroup.long 0x3AC++0x03 line.long 0x00 "STAT0,DDR_PHY_STAT0" width 0x0B tree.end tree "APBH-Bridge-DMA (AHB-to-APBH Bridge with DMA)" base ad:0x33000000 width 18. group.long 0x00++0x0F line.long 0x00 "CTRL0,AHB To APBH Bridge Control And Status Register 0" bitfld.long 0x00 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Gated on,Gated off" bitfld.long 0x00 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "Disabled,Enabled" newline bitfld.long 0x00 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "Disabled,Enabled" bitfld.long 0x00 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "Gated on,Gated off" bitfld.long 0x00 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "Gated on,Gated off" newline bitfld.long 0x00 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "Gated on,Gated off" bitfld.long 0x00 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "Gated on,Gated off" bitfld.long 0x00 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "Gated on,Gated off" newline bitfld.long 0x00 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "Gated on,Gated off" bitfld.long 0x00 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "Gated on,Gated off" newline bitfld.long 0x00 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "Gated on,Gated off" bitfld.long 0x00 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "Gated on,Gated off" line.long 0x04 "CTRL0_SET,AHB To APBH Bridge Control And Status Set Register 0" bitfld.long 0x04 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Set" newline bitfld.long 0x04 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Set" bitfld.long 0x04 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Set" bitfld.long 0x04 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Set" newline bitfld.long 0x04 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Set" bitfld.long 0x04 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Set" bitfld.long 0x04 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Set" newline bitfld.long 0x04 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Set" bitfld.long 0x04 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Set" newline bitfld.long 0x04 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Set" bitfld.long 0x04 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Set" line.long 0x08 "CTRL0_CLR,AHB To APBH Bridge Control And Status Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Clear" newline bitfld.long 0x08 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Clear" bitfld.long 0x08 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Clear" bitfld.long 0x08 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Clear" newline bitfld.long 0x08 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Clear" bitfld.long 0x08 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Clear" bitfld.long 0x08 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Clear" newline bitfld.long 0x08 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Clear" bitfld.long 0x08 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Clear" newline bitfld.long 0x08 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Clear" bitfld.long 0x08 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Clear" line.long 0x0C "CTRL0_TOG,AHB To APBH Bridge Control And Status Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Disables clocking with the APBH DMA and holds it in its reset state" "No effect,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Toggle" bitfld.long 0x0C 29. " AHB_BURST8_EN ,Enables AHB 8-beat burst" "No effect,Toggle" newline bitfld.long 0x0C 28. " APB_BURST_EN ,Enables APB master do a continuous transfers when a device request a burst DMA" "No effect,Toggle" bitfld.long 0x0C 8. " CLKGATE_SSP ,Gates off the individual clocks to the SSP" "No effect,Toggle" bitfld.long 0x0C 7. " CLKGATE_NAND7 ,Gates off the individual clocks to the NAND7" "No effect,Toggle" newline bitfld.long 0x0C 6. " CLKGATE_NAND6 ,Gates off the individual clocks to the NAND6" "No effect,Toggle" bitfld.long 0x0C 5. " CLKGATE_NAND5 ,Gates off the individual clocks to the NAND5" "No effect,Toggle" bitfld.long 0x0C 4. " CLKGATE_NAND4 ,Gates off the individual clocks to the NAND4" "No effect,Toggle" newline bitfld.long 0x0C 3. " CLKGATE_NAND3 ,Gates off the individual clocks to the NAND3" "No effect,Toggle" bitfld.long 0x0C 2. " CLKGATE_NAND2 ,Gates off the individual clocks to the NAND2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CLKGATE_NAND1 ,Gates off the individual clocks to the NAND1" "No effect,Toggle" bitfld.long 0x0C 0. " CLKGATE_NAND0 ,Gates off the individual clocks to the NAND0" "No effect,Toggle" group.long 0x10++0x0F line.long 0x00 "CTRL1,AHB To APBH Bridge Control And Status Register 1" bitfld.long 0x00 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "Disabled,Enabled" bitfld.long 0x00 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "Disabled,Enabled" bitfld.long 0x00 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "Disabled,Enabled" newline bitfld.long 0x00 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "Disabled,Enabled" bitfld.long 0x00 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "Disabled,Enabled" bitfld.long 0x00 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "Disabled,Enabled" newline bitfld.long 0x00 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "Disabled,Enabled" bitfld.long 0x00 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "Disabled,Enabled" bitfld.long 0x00 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "Disabled,Enabled" newline bitfld.long 0x00 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "Disabled,Enabled" bitfld.long 0x00 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "Disabled,Enabled" bitfld.long 0x00 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "Disabled,Enabled" bitfld.long 0x00 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "Disabled,Enabled" bitfld.long 0x00 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "Disabled,Enabled" newline bitfld.long 0x00 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "Disabled,Enabled" bitfld.long 0x00 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No interrupt,Interrupt" line.long 0x04 "CTRL1_SET,AHB To APBH Bridge Control And Status Set Register 1" bitfld.long 0x04 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Set" bitfld.long 0x04 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Set" newline bitfld.long 0x04 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Set" bitfld.long 0x04 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Set" newline bitfld.long 0x04 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Set" bitfld.long 0x04 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Set" newline bitfld.long 0x04 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Set" bitfld.long 0x04 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Set" newline bitfld.long 0x04 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Set" bitfld.long 0x04 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Set" newline bitfld.long 0x04 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Set" bitfld.long 0x04 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Set" newline bitfld.long 0x04 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x04 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Set" newline bitfld.long 0x04 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Set" bitfld.long 0x04 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Set" newline bitfld.long 0x04 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x04 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Set" newline bitfld.long 0x04 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Set" bitfld.long 0x04 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" newline bitfld.long 0x04 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x04 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Set" line.long 0x08 "CTRL1_CLR,AHB To APBH Bridge Control And Status Clear Register 1" bitfld.long 0x08 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Clear" bitfld.long 0x08 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Clear" newline bitfld.long 0x08 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Clear" bitfld.long 0x08 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Clear" newline bitfld.long 0x08 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Clear" bitfld.long 0x08 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Clear" newline bitfld.long 0x08 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Clear" bitfld.long 0x08 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Clear" newline bitfld.long 0x08 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Clear" bitfld.long 0x08 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Clear" newline bitfld.long 0x08 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Clear" bitfld.long 0x08 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Clear" newline bitfld.long 0x08 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x08 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Clear" newline bitfld.long 0x08 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Clear" bitfld.long 0x08 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Clear" newline bitfld.long 0x08 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x08 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Clear" newline bitfld.long 0x08 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Clear" bitfld.long 0x08 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" newline bitfld.long 0x08 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x08 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x0C "CTRL1_TOG,AHB To APBH Bridge Control And Status Toggle Register 1" bitfld.long 0x0C 31. " CH15_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 30. " CH14_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 14" "No effect,Toggle" bitfld.long 0x0C 29. " CH13_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 13" "No effect,Toggle" newline bitfld.long 0x0C 28. " CH12_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 27. " CH11_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 11" "No effect,Toggle" bitfld.long 0x0C 26. " CH10_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 10" "No effect,Toggle" newline bitfld.long 0x0C 25. " CH9_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 24. " CH8_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 8" "No effect,Toggle" bitfld.long 0x0C 23. " CH7_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 7" "No effect,Toggle" newline bitfld.long 0x0C 22. " CH6_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 21. " CH5_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 5" "No effect,Toggle" bitfld.long 0x0C 20. " CH4_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 4" "No effect,Toggle" newline bitfld.long 0x0C 19. " CH3_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 18. " CH2_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 2" "No effect,Toggle" bitfld.long 0x0C 17. " CH1_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 1" "No effect,Toggle" newline bitfld.long 0x0C 16. " CH0_CMDCMPLT_IRQ_EN ,Enables the generation of an interrupt request for APBH DMA channel 0" "No effect,Toggle" bitfld.long 0x0C 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 14" "No effect,Toggle" newline bitfld.long 0x0C 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Toggle" bitfld.long 0x0C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Toggle" newline bitfld.long 0x0C 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Toggle" bitfld.long 0x0C 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Toggle" newline bitfld.long 0x0C 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Toggle" bitfld.long 0x0C 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Toggle" newline bitfld.long 0x0C 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Toggle" bitfld.long 0x0C 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Toggle" bitfld.long 0x0C 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x20++0x0F line.long 0x00 "CTRL2,AHB To APBH Bridge Control And Status Register 2" rbitfld.long 0x00 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "Early termination,AHB bus error" rbitfld.long 0x00 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "Early termination,AHB bus error" rbitfld.long 0x00 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "Early termination,AHB bus error" newline rbitfld.long 0x00 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "Early termination,AHB bus error" rbitfld.long 0x00 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "Early termination,AHB bus error" rbitfld.long 0x00 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "Early termination,AHB bus error" newline rbitfld.long 0x00 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "Early termination,AHB bus error" rbitfld.long 0x00 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "Early termination,AHB bus error" rbitfld.long 0x00 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "Early termination,AHB bus error" newline rbitfld.long 0x00 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "Early termination,AHB bus error" rbitfld.long 0x00 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "Early termination,AHB bus error" rbitfld.long 0x00 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "Early termination,AHB bus error" newline rbitfld.long 0x00 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "Early termination,AHB bus error" rbitfld.long 0x00 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "Early termination,AHB bus error" rbitfld.long 0x00 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "Early termination,AHB bus error" newline rbitfld.long 0x00 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "Early termination,AHB bus error" bitfld.long 0x00 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No interrupt,Interrupt" line.long 0x04 "CTRL2_SET,AHB To APBH Bridge Control And Status Set Register 2" rbitfld.long 0x04 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Set" rbitfld.long 0x04 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Set" rbitfld.long 0x04 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Set" newline rbitfld.long 0x04 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Set" rbitfld.long 0x04 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Set" rbitfld.long 0x04 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Set" newline rbitfld.long 0x04 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Set" rbitfld.long 0x04 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Set" rbitfld.long 0x04 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Set" newline rbitfld.long 0x04 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Set" rbitfld.long 0x04 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Set" rbitfld.long 0x04 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Set" newline rbitfld.long 0x04 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Set" rbitfld.long 0x04 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Set" rbitfld.long 0x04 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Set" newline rbitfld.long 0x04 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Set" bitfld.long 0x04 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Set" bitfld.long 0x04 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Set" newline bitfld.long 0x04 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x04 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Set" bitfld.long 0x04 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Set" newline bitfld.long 0x04 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Set" bitfld.long 0x04 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x04 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Set" newline bitfld.long 0x04 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x04 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Set" bitfld.long 0x04 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Set" newline bitfld.long 0x04 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Set" bitfld.long 0x04 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x04 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Set" newline bitfld.long 0x04 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x04 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Set" line.long 0x08 "CTRL2_CLR,AHB To APBH Bridge Control And Status Clear Register 2" rbitfld.long 0x08 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Clear" rbitfld.long 0x08 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Clear" rbitfld.long 0x08 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Clear" newline rbitfld.long 0x08 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Clear" rbitfld.long 0x08 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Clear" rbitfld.long 0x08 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Clear" newline rbitfld.long 0x08 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Clear" rbitfld.long 0x08 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Clear" rbitfld.long 0x08 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Clear" newline rbitfld.long 0x08 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Clear" rbitfld.long 0x08 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Clear" rbitfld.long 0x08 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Clear" newline rbitfld.long 0x08 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Clear" rbitfld.long 0x08 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Clear" rbitfld.long 0x08 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Clear" newline rbitfld.long 0x08 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Clear" bitfld.long 0x08 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Clear" bitfld.long 0x08 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Clear" newline bitfld.long 0x08 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x08 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Clear" bitfld.long 0x08 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Clear" newline bitfld.long 0x08 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Clear" bitfld.long 0x08 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x08 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Clear" newline bitfld.long 0x08 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x08 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Clear" bitfld.long 0x08 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Clear" newline bitfld.long 0x08 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Clear" bitfld.long 0x08 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x08 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Clear" newline bitfld.long 0x08 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x08 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x0C "CTRL2_TOG,AHB To APBH Bridge Control And Status Register 2" rbitfld.long 0x0C 31. " CH15_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Toggle" rbitfld.long 0x0C 30. " CH14_ERROR_STATUS ,Error status bit for APBH DMA channel 14" "No effect,Toggle" rbitfld.long 0x0C 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA channel 13" "No effect,Toggle" newline rbitfld.long 0x0C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA channel 12" "No effect,Toggle" rbitfld.long 0x0C 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA channel 11" "No effect,Toggle" rbitfld.long 0x0C 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA channel 10" "No effect,Toggle" newline rbitfld.long 0x0C 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA channel 9" "No effect,Toggle" rbitfld.long 0x0C 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA channel 8" "No effect,Toggle" rbitfld.long 0x0C 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA channel 7" "No effect,Toggle" newline rbitfld.long 0x0C 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA channel 6" "No effect,Toggle" rbitfld.long 0x0C 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA channel 5" "No effect,Toggle" rbitfld.long 0x0C 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA channel 4" "No effect,Toggle" newline rbitfld.long 0x0C 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA channel 3" "No effect,Toggle" rbitfld.long 0x0C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA channel 2" "No effect,Toggle" rbitfld.long 0x0C 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA channel 1" "No effect,Toggle" newline rbitfld.long 0x0C 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA channel 0" "No effect,Toggle" bitfld.long 0x0C 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 14" "No effect,Toggle" newline bitfld.long 0x0C 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 13" "No effect,Toggle" bitfld.long 0x0C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 11" "No effect,Toggle" newline bitfld.long 0x0C 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 10" "No effect,Toggle" bitfld.long 0x0C 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 8" "No effect,Toggle" newline bitfld.long 0x0C 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 7" "No effect,Toggle" bitfld.long 0x0C 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 5" "No effect,Toggle" newline bitfld.long 0x0C 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 4" "No effect,Toggle" bitfld.long 0x0C 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 2" "No effect,Toggle" newline bitfld.long 0x0C 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 1" "No effect,Toggle" bitfld.long 0x0C 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x30++0x0F line.long 0x00 "CHANNEL_CTRL,AHB To APBH Bridge Channel Register" bitfld.long 0x00 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No reset,Reset" bitfld.long 0x00 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No reset,Reset" bitfld.long 0x00 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No reset,Reset" newline bitfld.long 0x00 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No reset,Reset" bitfld.long 0x00 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No reset,Reset" bitfld.long 0x00 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No reset,Reset" newline bitfld.long 0x00 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No reset,Reset" bitfld.long 0x00 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No reset,Reset" bitfld.long 0x00 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No reset,Reset" newline bitfld.long 0x00 8. " FREEZE_SSP ,Freezes the SSP" "Not frozen,Frozen" bitfld.long 0x00 7. " FREEZE_NAND7 ,Freezes the NSND7" "Not frozen,Frozen" bitfld.long 0x00 6. " FREEZE_NAND6 ,Freezes the NSND6" "Not frozen,Frozen" newline bitfld.long 0x00 5. " FREEZE_NAND5 ,Freezes the NSND5" "Not frozen,Frozen" bitfld.long 0x00 4. " FREEZE_NAND4 ,Freezes the NSND4" "Not frozen,Frozen" bitfld.long 0x00 3. " FREEZE_NAND3 ,Freezes the NSND3" "Not frozen,Frozen" newline bitfld.long 0x00 2. " FREEZE_NAND2 ,Freezes the NSND2" "Not frozen,Frozen" bitfld.long 0x00 1. " FREEZE_NAND1 ,Freezes the NSND1" "Not frozen,Frozen" bitfld.long 0x00 0. " FREEZE_NAND0 ,Freezes the NSND0" "Not frozen,Frozen" line.long 0x04 "CHANNEL_CTRL_SET,AHB To APBH Bridge Channel Set Register" bitfld.long 0x04 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Set" bitfld.long 0x04 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Set" bitfld.long 0x04 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Set" newline bitfld.long 0x04 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Set" bitfld.long 0x04 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Set" bitfld.long 0x04 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Set" newline bitfld.long 0x04 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Set" bitfld.long 0x04 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Set" bitfld.long 0x04 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Set" newline bitfld.long 0x04 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Set" bitfld.long 0x04 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Set" bitfld.long 0x04 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Set" newline bitfld.long 0x04 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Set" bitfld.long 0x04 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Set" bitfld.long 0x04 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Set" newline bitfld.long 0x04 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Set" bitfld.long 0x04 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Set" bitfld.long 0x04 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Set" line.long 0x08 "CHANNEL_CTRL_CLR,AHB To APBH Bridge Channel Clear Register" bitfld.long 0x08 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Clear" bitfld.long 0x08 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Clear" bitfld.long 0x08 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Clear" newline bitfld.long 0x08 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Clear" bitfld.long 0x08 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Clear" bitfld.long 0x08 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Clear" newline bitfld.long 0x08 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Clear" bitfld.long 0x08 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Clear" bitfld.long 0x08 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Clear" newline bitfld.long 0x08 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Clear" bitfld.long 0x08 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Clear" bitfld.long 0x08 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Clear" newline bitfld.long 0x08 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Clear" bitfld.long 0x08 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Clear" bitfld.long 0x08 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Clear" newline bitfld.long 0x08 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Clear" bitfld.long 0x08 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Clear" bitfld.long 0x08 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Clear" line.long 0x0C "CHANNEL_CTRL_TOG,AHB To APBH Bridge Channel Toggle Register" bitfld.long 0x0C 24. " RESET_SSP ,Causes the DMA controller to take the SSP through its reset state" "No effect,Toggle" bitfld.long 0x0C 23. " RESET_NAND7 ,Causes the DMA controller to take the NAND7 through its reset state" "No effect,Toggle" bitfld.long 0x0C 22. " RESET_NAND6 ,Causes the DMA controller to take the NAND6 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 21. " RESET_NAND5 ,Causes the DMA controller to take the NAND5 through its reset state" "No effect,Toggle" bitfld.long 0x0C 20. " RESET_NAND4 ,Causes the DMA controller to take the NAND4 through its reset state" "No effect,Toggle" bitfld.long 0x0C 19. " RESET_NAND3 ,Causes the DMA controller to take the NAND3 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 18. " RESET_NAND2 ,Causes the DMA controller to take the NAND2 through its reset state" "No effect,Toggle" bitfld.long 0x0C 17. " RESET_NAND1 ,Causes the DMA controller to take the NAND1 through its reset state" "No effect,Toggle" bitfld.long 0x0C 16. " RESET_NAND0 ,Causes the DMA controller to take the NAND0 through its reset state" "No effect,Toggle" newline bitfld.long 0x0C 8. " FREEZE_SSP ,Freezes the SSP" "No effect,Toggle" bitfld.long 0x0C 7. " FREEZE_NAND7 ,Freezes the NSND7" "No effect,Toggle" bitfld.long 0x0C 6. " FREEZE_NAND6 ,Freezes the NSND6" "No effect,Toggle" newline bitfld.long 0x0C 5. " FREEZE_NAND5 ,Freezes the NSND5" "No effect,Toggle" bitfld.long 0x0C 4. " FREEZE_NAND4 ,Freezes the NSND4" "No effect,Toggle" bitfld.long 0x0C 3. " FREEZE_NAND3 ,Freezes the NSND3" "No effect,Toggle" newline bitfld.long 0x0C 2. " FREEZE_NAND2 ,Freezes the NSND2" "No effect,Toggle" bitfld.long 0x0C 1. " FREEZE_NAND1 ,Freezes the NSND1" "No effect,Toggle" bitfld.long 0x0C 0. " FREEZE_NAND0 ,Freezes the NSND0" "No effect,Toggle" group.long 0x50++0x03 line.long 0x00 "DMA_BURST_SIZE,AHB To APBH DMA Burst Size" bitfld.long 0x00 16.--17. " CH8 ,DMA burst size for SSP" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 14.--15. " CH7 ,DMA burst size for GPMI channel 7" ",BURST4,?..." bitfld.long 0x00 12.--13. " CH6 ,DMA burst size for GPMI channel 6" ",BURST4,?..." newline bitfld.long 0x00 10.--11. " CH5 ,DMA burst size for GPMI channel 5" ",BURST4,?..." bitfld.long 0x00 8.--9. " CH4 ,DMA burst size for GPMI channel 4" ",BURST4,?..." bitfld.long 0x00 6.--7. " CH3 ,DMA burst size for GPMI channel 3" ",BURST4,?..." newline bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for GPMI channel 2" ",BURST4,?..." bitfld.long 0x00 2.--3. " CH1 ,DMA burst size for GPMI channel 1" ",BURST4,?..." bitfld.long 0x00 0.--1. " CH0 ,DMA burst size for GPMI channel 0" ",BURST4,?..." group.long 0x60++0x03 line.long 0x00 "DEBUG,AHB To APBH DMA Debug Register" bitfld.long 0x00 0. " GPMI_ONE_FIFO ,DMA FIFO sharing" "Own,Shared" newline rgroup.long 0x100++0x03 line.long 0x00 "CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x100+0x30)++0x03 line.long 0x00 "CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x100+0x40)++0x03 line.long 0x00 "CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "CH0_DEBUG1,AHB To APBH DMA Channel 0 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x100+0x60)++0x03 line.long 0x00 "CH0_DEBUG2,AHB To APBH DMA Channel 0 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x170++0x03 line.long 0x00 "CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x170+0x30)++0x03 line.long 0x00 "CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0x170+0x40)++0x03 line.long 0x00 "CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "CH1_DEBUG1,AHB To APBH DMA Channel 1 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x170+0x60)++0x03 line.long 0x00 "CH1_DEBUG2,AHB To APBH DMA Channel 1 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x1E0++0x03 line.long 0x00 "CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x1E0+0x30)++0x03 line.long 0x00 "CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x1E0+0x40)++0x03 line.long 0x00 "CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "CH2_DEBUG1,AHB To APBH DMA Channel 2 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "CH2_DEBUG2,AHB To APBH DMA Channel 2 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x250++0x03 line.long 0x00 "CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x250+0x30)++0x03 line.long 0x00 "CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x250+0x40)++0x03 line.long 0x00 "CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "CH3_DEBUG1,AHB To APBH DMA Channel 3 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x250+0x60)++0x03 line.long 0x00 "CH3_DEBUG2,AHB To APBH DMA Channel 3 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x2C0++0x03 line.long 0x00 "CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x2C0+0x30)++0x03 line.long 0x00 "CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x2C0+0x40)++0x03 line.long 0x00 "CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "CH4_DEBUG1,AHB To APBH DMA Channel 4 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "CH4_DEBUG2,AHB To APBH DMA Channel 4 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x330++0x03 line.long 0x00 "CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x330+0x30)++0x03 line.long 0x00 "CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x330+0x40)++0x03 line.long 0x00 "CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "CH5_DEBUG1,AHB To APBH DMA Channel 5 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x330+0x60)++0x03 line.long 0x00 "CH5_DEBUG2,AHB To APBH DMA Channel 5 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x3A0++0x03 line.long 0x00 "CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x3A0+0x30)++0x03 line.long 0x00 "CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x3A0+0x40)++0x03 line.long 0x00 "CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "CH6_DEBUG1,AHB To APBH DMA Channel 6 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "CH6_DEBUG2,AHB To APBH DMA Channel 6 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x410++0x03 line.long 0x00 "CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x410+0x30)++0x03 line.long 0x00 "CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x410+0x40)++0x03 line.long 0x00 "CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "CH7_DEBUG1,AHB To APBH DMA Channel 7 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x410+0x60)++0x03 line.long 0x00 "CH7_DEBUG2,AHB To APBH DMA Channel 7 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x480++0x03 line.long 0x00 "CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "CH8_CMD,APBH DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x480+0x30)++0x03 line.long 0x00 "CH8_BAR,APBH DMA Channel 8 Buffer Address Register" group.long (0x480+0x40)++0x03 line.long 0x00 "CH8_SEMA,APBH DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "CH8_DEBUG1,AHB To APBH DMA Channel 8 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x480+0x60)++0x03 line.long 0x00 "CH8_DEBUG2,AHB To APBH DMA Channel 8 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x4F0++0x03 line.long 0x00 "CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "CH9_CMD,APBH DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x4F0+0x30)++0x03 line.long 0x00 "CH9_BAR,APBH DMA Channel 9 Buffer Address Register" group.long (0x4F0+0x40)++0x03 line.long 0x00 "CH9_SEMA,APBH DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "CH9_DEBUG1,AHB To APBH DMA Channel 9 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "CH9_DEBUG2,AHB To APBH DMA Channel 9 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x560++0x03 line.long 0x00 "CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "CH10_CMD,APBH DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x560+0x30)++0x03 line.long 0x00 "CH10_BAR,APBH DMA Channel 10 Buffer Address Register" group.long (0x560+0x40)++0x03 line.long 0x00 "CH10_SEMA,APBH DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "CH10_DEBUG1,AHB To APBH DMA Channel 10 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x560+0x60)++0x03 line.long 0x00 "CH10_DEBUG2,AHB To APBH DMA Channel 10 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x5D0++0x03 line.long 0x00 "CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "CH11_CMD,APBH DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x5D0+0x30)++0x03 line.long 0x00 "CH11_BAR,APBH DMA Channel 11 Buffer Address Register" group.long (0x5D0+0x40)++0x03 line.long 0x00 "CH11_SEMA,APBH DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "CH11_DEBUG1,AHB To APBH DMA Channel 11 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "CH11_DEBUG2,AHB To APBH DMA Channel 11 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x640++0x03 line.long 0x00 "CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "CH12_CMD,APBH DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x640+0x30)++0x03 line.long 0x00 "CH12_BAR,APBH DMA Channel 12 Buffer Address Register" group.long (0x640+0x40)++0x03 line.long 0x00 "CH12_SEMA,APBH DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "CH12_DEBUG1,AHB To APBH DMA Channel 12 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x640+0x60)++0x03 line.long 0x00 "CH12_DEBUG2,AHB To APBH DMA Channel 12 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x6B0++0x03 line.long 0x00 "CH13_CURCMDAR,APBH DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "CH13_NXTCMDAR,APBH DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "CH13_CMD,APBH DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x6B0+0x30)++0x03 line.long 0x00 "CH13_BAR,APBH DMA Channel 13 Buffer Address Register" group.long (0x6B0+0x40)++0x03 line.long 0x00 "CH13_SEMA,APBH DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "CH13_DEBUG1,AHB To APBH DMA Channel 13 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "CH13_DEBUG2,AHB To APBH DMA Channel 13 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x720++0x03 line.long 0x00 "CH14_CURCMDAR,APBH DMA Channel 14 Current Command Address Register" group.long (0x720+0x10)++0x03 line.long 0x00 "CH14_NXTCMDAR,APBH DMA Channel 14 Next Command Address Register" rgroup.long (0x720+0x20)++0x03 line.long 0x00 "CH14_CMD,APBH DMA Channel 14 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x720+0x30)++0x03 line.long 0x00 "CH14_BAR,APBH DMA Channel 14 Buffer Address Register" group.long (0x720+0x40)++0x03 line.long 0x00 "CH14_SEMA,APBH DMA Channel 14 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x720+0x50)++0x03 line.long 0x00 "CH14_DEBUG1,AHB To APBH DMA Channel 14 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x720+0x60)++0x03 line.long 0x00 "CH14_DEBUG2,AHB To APBH DMA Channel 14 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x790++0x03 line.long 0x00 "CH15_CURCMDAR,APBH DMA Channel 15 Current Command Address Register" group.long (0x790+0x10)++0x03 line.long 0x00 "CH15_NXTCMDAR,APBH DMA Channel 15 Next Command Address Register" rgroup.long (0x790+0x20)++0x03 line.long 0x00 "CH15_CMD,APBH DMA Channel 15 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No other command,Other command" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x790+0x30)++0x03 line.long 0x00 "CH15_BAR,APBH DMA Channel 15 Buffer Address Register" group.long (0x790+0x40)++0x03 line.long 0x00 "CH15_SEMA,APBH DMA Channel 15 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x790+0x50)++0x03 line.long 0x00 "CH15_DEBUG1,AHB To APBH DMA Channel 15 Debug Information" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "0,1" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "0,1" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal from the APB device" "0,1" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "0,1" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x790+0x60)++0x03 line.long 0x00 "CH15_DEBUG2,AHB To APBH DMA Channel 15 Debug Information" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" group.long 0x800++0x03 line.long 0x00 "VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Reflects the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Reflects the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" width 0x0B tree.end tree "BCH (62BIT Correcting ECC Accelerator)" base ad:0x33004000 width 20. group.long 0x00++0x0F line.long 0x00 "CTRL,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x00 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x00 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x00 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x04 "CTRL_SET,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x04 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x04 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x04 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x04 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x08 "CTRL_CLR,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x08 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x08 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x08 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x08 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" line.long 0x0C "CTRL_TOG,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x0C 31. " SFTRST ,Disables clocking with the BCH and hold it in its reset state" "RUN,RESET" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "RUN,NO_CLKS" bitfld.long 0x0C 22. " DEBUGSYNDROME ,Enables write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" newline bitfld.long 0x0C 18.--19. " M2M_LAYOUT ,Selects the flash page format for memory-to-memory operations" "0,1,2,3" bitfld.long 0x0C 17. " M2M_ENCODE ,Selects encode or decode mode for memory-to-memory operations" "Decoded,Encoded" bitfld.long 0x0C 16. " M2M_ENABLE ,Memory-to-memory operation enable" "Disabled,Enabled" newline bitfld.long 0x0C 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x0C 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" bitfld.long 0x0C 3. " BM_ERROR_IRQ ,AHB bus interface error interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 2. " DEBUG_STALL_IRQ ,DEBUG STALL interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 0. " COMPLETE_IRQ ,Indicates the state of the external interrupt line" "No interrupt,Interrupt" rgroup.long 0x10++0x0F line.long 0x00 "STATUS0,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x00 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x00 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x00 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x04 "STATUS0_SET,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x04 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x04 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x04 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x04 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x04 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x08 "STATUS0_CLR,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x08 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x08 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x08 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x08 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x08 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" line.long 0x0C "STATUS0_TOG,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x0C 20.--31. 1. " HANDLE ,A part of the GPMI DMA PIO operation that started the transaction" bitfld.long 0x0C 16.--19. " COMPLETED_CE ,Chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash" newline bitfld.long 0x0C 4. " ALLONES ,Indicates whether all data bits of this transaction are ONE" "No,Yes" bitfld.long 0x0C 3. " CORRECTED ,Indicates whether at least one correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x0C 2. " UNCORRECTABLE ,Indicates whether uncorrectable error encountered during last processing cycle" "No,Yes" group.long 0x20++0x0F line.long 0x00 "MODE,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x04 "MODE_SET,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x04 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x08 "MODE_CLR,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x08 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" line.long 0x0C "MODE_TOG,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x0C 0.--7. 1. " ERASE_THRESHOLD ,Indicates the maximum number of zero bits on a flash subpage for it to be considered erased" group.long 0x30++0x0F line.long 0x00 "ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x04 "ENCODEPTR_SET,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x08 "ENCODEPTR_CLR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x0C "ENCODEPTR_TOG,Hardware BCH ECC Loopback Encode Buffer Register" group.long 0x40++0x0F line.long 0x00 "DATAPTR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x04 "DATAPTR_SET,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x08 "DATAPTR_CLR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x0C "DATAPTR_TOG,Hardware BCH ECC Loopback Data Buffer Register" group.long 0x50++0x0F line.long 0x00 "METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x04 "METAPTR_SET,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x08 "METAPTR_CLR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x0C "METAPTR_TOG,Hardware BCH ECC Loopback Metadata Buffer Register" group.long 0x70++0x0F line.long 0x00 "LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x00 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x00 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x00 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x00 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x00 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x00 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x00 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x00 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x00 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x00 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x00 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x00 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x00 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x00 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x00 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x04 "LAYOUTSELECT_SET,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x04 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x04 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x04 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x04 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x04 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x04 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x04 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x04 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x04 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x04 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x04 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x04 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x04 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x04 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x04 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x04 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x08 "LAYOUTSELECT_CLR,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x08 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x08 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x08 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x08 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x08 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x08 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x08 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x08 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x08 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x08 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x08 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x08 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x08 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x08 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x08 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" line.long 0x0C "LAYOUTSELECT_TOG,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x0C 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x0C 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" bitfld.long 0x0C 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x0C 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" newline bitfld.long 0x0C 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x0C 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" bitfld.long 0x0C 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x0C 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" newline bitfld.long 0x0C 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x0C 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" bitfld.long 0x0C 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x0C 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" newline bitfld.long 0x0C 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x0C 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" bitfld.long 0x0C 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x0C 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" group.long 0x80++0x0F line.long 0x00 "FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH0LAYOUT0_SET,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH0LAYOUT0_CLR,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH0LAYOUT0_TOG,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0x90++0x0F line.long 0x00 "FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH0LAYOUT1_SET,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH0LAYOUT1_CLR,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH0LAYOUT1_TOG,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xA0++0x0F line.long 0x00 "FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH1LAYOUT0_SET,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH1LAYOUT0_CLR,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH1LAYOUT0_TOG,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xB0++0x0F line.long 0x00 "FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH1LAYOUT1_SET,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH1LAYOUT1_CLR,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH1LAYOUT1_TOG,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xC0++0x0F line.long 0x00 "FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH2LAYOUT0_SET,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH2LAYOUT0_CLR,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH2LAYOUT0_TOG,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xD0++0x0F line.long 0x00 "FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH2LAYOUT1_SET,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH2LAYOUT1_CLR,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH2LAYOUT1_TOG,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" group.long 0xE0++0x0F line.long 0x00 "FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x00 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH3LAYOUT0_SET,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x04 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH3LAYOUT0_CLR,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x08 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH3LAYOUT0_TOG,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page (Excluding the data0 block)" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (In bytes) to be stored on a flash page" bitfld.long 0x0C 11.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (In four bytes) to be stored on the flash page" group.long 0xF0++0x0F line.long 0x00 "FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x00 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x04 "FLASH3LAYOUT1_SET,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x04 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x08 "FLASH3LAYOUT1_CLR,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x08 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" line.long 0x0C "FLASH3LAYOUT1_TOG,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (In bytes)" bitfld.long 0x0C 11.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page (Blocks 1-n)" "No ECC,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,Select GF13 or GF14" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (In four bytes) to be stored on the flash page" newline group.long 0x100++0x0F line.long 0x00 "DEBUG0,Hardware BCH ECC Debug Register0" hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x00 12. " KES_DEBUG_KICK ,Toggle to make KES engine FSM start as if kick by the bus master" "0,1" bitfld.long 0x00 11. " KES_STANDALONE ,Bus master address generator's operation mode" "NORMAL,TEST_MODE" newline bitfld.long 0x00 10. " KES_DEBUG_STEP ,Toggle to make KES FSM skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1" bitfld.long 0x00 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "NORMAL,TEST_MODE" newline bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DEBUG0_SET,Hardware BCH ECC Debug Register0" hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x04 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x04 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x04 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DEBUG0_CLR,Hardware BCH ECC Debug Register0" hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x08 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x08 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x08 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "DEBUG0_TOG,Hardware BCH ECC Debug Register0" hexmask.long.word 0x0C 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled" bitfld.long 0x0C 15. " KES_DEBUG_SHIFT_SYND ,Toggle to shift BCH_DEBUG0_KES_SYNDROME_SYMBOL into the syndrome register array" "0,1" bitfld.long 0x0C 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Data,Auxiliary" newline bitfld.long 0x0C 13. " KES_DEBUG_MODE4K ,Input mode" "4K NAND pages,2K NAND pages" bitfld.long 0x0C 12. " KES_DEBUG_KICK ,KES_DEBUG_KICK" "0,1" bitfld.long 0x0C 11. " KES_STANDALONE ,Bus master address generator's operation mode" "Normal,Test" newline bitfld.long 0x0C 10. " KES_DEBUG_STEP ,KES_DEBUG_STEP" "0,1" bitfld.long 0x0C 9. " KES_DEBUG_STALL ,Indicates whether KES FSM proceeds to next block supplied by bus master or waits" "NORMAL,WAIT" bitfld.long 0x0C 8. " BM_KES_TEST_BYPASS ,BM_KES_TEST_BYPASS" "0,1" newline bitfld.long 0x0C 0.--5. " DEBUG_REG_SELECT ,Selects the internal register state view of KES engine or the chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x110++0x0F line.long 0x00 "DBGKESREAD,KES Debug Read Register" line.long 0x04 "DBGKESREAD_SET,KES Debug Read Register" line.long 0x08 "DBGKESREAD_CLR,KES Debug Read Register" line.long 0x0C "DBGKESREAD_TOG,KES Debug Read Register" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")||cpuis("IMX8MQ")||cpuis("IMX8MQ-CM4")) rgroup.long 0x110++0x0F line.long 0x00 "DBGCSFEREAD,Chien Search Debug Read Register" line.long 0x04 "DBGCSFEREAD_SET,Chien Search Debug Read Register" line.long 0x08 "DBGCSFEREAD_CLR,Chien Search Debug Read Register" line.long 0x0C "DBGCSFEREAD_TOG,Chien Search Debug Read Register" rgroup.long 0x130++0x0F line.long 0x00 "DBGSYNDGENREAD,Syndrome Generator Debug Read Register" line.long 0x04 "DBGSYNDGENREAD_SET,Syndrome Generator Debug Read Register" line.long 0x08 "DBGSYNDGENREAD_CLR,Syndrome Generator Debug Read Register" line.long 0x0C "DBGSYNDGENREAD_TOG,Syndrome Generator Debug Read Register" rgroup.long 0x140++0x0F line.long 0x00 "DBGAHBMREAD,Bus Master and ECC Controller Debug Read Register" line.long 0x04 "DBGAHBMREAD_SET,Bus Master and ECC Controller Debug Read Register" line.long 0x08 "DBGAHBMREAD_CLR,Bus Master and ECC Controller Debug Read Register" line.long 0x0C "DBGAHBMREAD_TOG,Bus Master and ECC Controller Debug Read Register" endif rgroup.long 0x150++0x0F line.long 0x00 "BLOCKNAME,Block Name Register" line.long 0x04 "BLOCKNAME_SET,Block Name Register" line.long 0x08 "BLOCKNAME_CLR,Block Name Register" line.long 0x0C "BLOCKNAME_TOG,Block Name Register" rgroup.long 0x160++0x0F line.long 0x00 "VERSION,BCH Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x04 "VERSION_SET,BCH Version Register" hexmask.long.byte 0x04 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x04 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x04 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x08 "VERSION_CLR,BCH Version Register" hexmask.long.byte 0x08 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x08 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x08 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" line.long 0x0C "VERSION_TOG,BCH Version Register" hexmask.long.byte 0x0C 24.--31. 1. " MAJOR ,Indicates the MAJOR field of the RTL version" hexmask.long.byte 0x0C 16.--23. 1. " MINOR ,Indicates the MINOR field of the RTL version" hexmask.long.word 0x0C 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" group.long 0x170++0x0F line.long 0x00 "DEBUG1,Hardware BCH ECC Debug Register 1" bitfld.long 0x00 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x00 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x04 "DEBUG1_SET,Hardware BCH ECC Debug Register 1" bitfld.long 0x04 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x04 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x08 "DEBUG1_CLR,Hardware BCH ECC Debug Register 1" bitfld.long 0x08 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x08 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x0C "DEBUG1_TOG,Hardware BCH ECC Debug Register 1" bitfld.long 0x0C 31. " DEBUG1_PREERASECHK ,Enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x0C 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" width 0x0B tree.end tree "GPMI (General Purpose Media Interface)" base ad:0x33002000 width 13. group.long 0x00++0x13 line.long 0x00 "CTRL0,GPMI Control Register 0" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "RUN,NO_CLKS" bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy" newline bitfld.long 0x00 28. " DEV_IRQ_EN ,DEV IRQ enable" "Disabled,Enabled" bitfld.long 0x00 27. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled" bitfld.long 0x00 26. " UDMA ,ATA-Ultra DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x00 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Address increment" "Not incremented,Incremented" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x04 "CTRL0_SET,GPMI Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set" newline bitfld.long 0x04 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Set" bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set" bitfld.long 0x04 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Set" newline bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x04 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x08 "CTRL0_CLR,GPMI Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Clear" bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Clear" newline bitfld.long 0x08 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,Chip select lock bit" "No effect,Clear" bitfld.long 0x08 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Clear" newline bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x08 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x0C "CTRL0_TOG,GPMI Control Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Soft reset" "No effect,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Clock gate" "No effect,Toggle" bitfld.long 0x0C 29. " RUN ,GPMI busy running" "No effect,Toggle" newline bitfld.long 0x0C 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Toggle" bitfld.long 0x0C 27. " LOCK_CS ,Chip select lock bit" "No effect,Toggle" bitfld.long 0x0C 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Toggle" newline bitfld.long 0x0C 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x0C 23. " WORD_LENGTH ,Data bus mode" ",8-bit" bitfld.long 0x0C 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 17.--19. " ADDRESS ,Address" "NAND data,NAND CLE,NAND ALE,?..." bitfld.long 0x0C 16. " ADDRESS_INCREMENT ,Address increment" "No effect,Toggle" hexmask.long.word 0x0C 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer for this command" line.long 0x10 "COMPARE,GPMI Compare Register Description" hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field" hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device" group.long 0x20++0x13 line.long 0x00 "ECCCTRL,GPMI Integrated ECC Control Register" hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x00 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled" bitfld.long 0x00 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x00 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x04 "ECCCTRL_SET,GPMI Integrated ECC Control Set Register" hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x04 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set" bitfld.long 0x04 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x04 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x04 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x08 "ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x08 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Clear" bitfld.long 0x08 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x08 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x08 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x0C "ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x0C 13.--14. " ECC_CMD ,ECC command information" "DECODE,ENCODE,?..." newline bitfld.long 0x0C 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Toggle" bitfld.long 0x0C 11. " RANDOMIZER_ENABLE ,Enable randomizer function" "Disabled,Enabled" bitfld.long 0x0C 9.--10. " RANDOMIZER_TYPE ,Set randomizer type" "0,1,2,?..." hexmask.long.word 0x0C 0.--8. 1. " BUFFER_MASK ,ECC buffer information" newline line.long 0x10 "ECCCOUNT,GPMI Integrated ECC Transfer Count Register" hexmask.long.byte 0x10 16.--23. 1. " RANDOMIZER_PAGE ,Set NAND page number needed to be randomized" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC" group.long 0x40++0x03 line.long 0x00 "PAYLOAD,GPMI Payload Address Register" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers" group.long 0x50++0x03 line.long 0x00 "AUXILIARY,GPMI Auxiliary Address Register" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to ECC control structure and meta-data storage" group.long 0x60++0x13 line.long 0x00 "CTRL1,GPMI Control Register 1" bitfld.long 0x00 31. " DEV_CLK_STOP ,Device clock stop" "Not stopped,Stopped" bitfld.long 0x00 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not stopped,Stopped" bitfld.long 0x00 29. " WRITE_CLK_STOP ,Stop clock during data write" "Not stopped,Stopped" newline bitfld.long 0x00 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Disabled,Enabled" bitfld.long 0x00 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "Disabled,Enabled" bitfld.long 0x00 26. " UPDATE_CS ,Force CS value update" "Not updated,Updated" newline bitfld.long 0x00 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x00 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "Disabled,Enabled" bitfld.long 0x00 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x00 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "Disabled,Enabled" bitfld.long 0x00 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced" newline bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" ",BCH" bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled" newline bitfld.long 0x00 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "NAND device,HWECC module" bitfld.long 0x00 10. " DEV_IRQ ,ATA device interrupt received" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "No interrupt,Interrupt" bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled" bitfld.long 0x00 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not aborted,Aborted" newline bitfld.long 0x00 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset" bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Low,High" newline bitfld.long 0x00 1. " CAMERA_MODE ,CAMERA mode" "Disabled,Enabled" bitfld.long 0x00 0. " GPMI_MODE ,GPMI mode" "NAND,ATA" line.long 0x04 "CTRL1_SET,GPMI Control Set Register 1" bitfld.long 0x04 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Set" bitfld.long 0x04 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Set" bitfld.long 0x04 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Set" newline bitfld.long 0x04 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Set" bitfld.long 0x04 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Set" bitfld.long 0x04 26. " UPDATE_CS ,Force CS value update" "No effect,Set" newline bitfld.long 0x04 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x04 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Set" bitfld.long 0x04 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x04 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x04 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Set" bitfld.long 0x04 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Set" newline bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Set" bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Set" bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Set" newline bitfld.long 0x04 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Set" bitfld.long 0x04 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Set" newline bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Set" bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Set" bitfld.long 0x04 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Set" newline bitfld.long 0x04 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Set" bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Set" newline bitfld.long 0x04 1. " CAMERA_MODE ,CAMERA mode" "No effect,Set" bitfld.long 0x04 0. " GPMI_MODE ,GPMI mode" "No effect,Set" line.long 0x08 "CTRL1_CLR,GPMI Control Clear Register 1" bitfld.long 0x08 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Clear" bitfld.long 0x08 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Clear" bitfld.long 0x08 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Clear" newline bitfld.long 0x08 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Clear" bitfld.long 0x08 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Clear" bitfld.long 0x08 26. " UPDATE_CS ,Force CS value update" "No effect,Clear" newline bitfld.long 0x08 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x08 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Clear" bitfld.long 0x08 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x08 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x08 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Clear" bitfld.long 0x08 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Clear" newline bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Clear" bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Clear" bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Clear" newline bitfld.long 0x08 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Clear" bitfld.long 0x08 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Clear" newline bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Clear" bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Clear" bitfld.long 0x08 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Clear" newline bitfld.long 0x08 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Clear" bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Clear" newline bitfld.long 0x08 1. " CAMERA_MODE ,CAMERA mode" "No effect,Clear" bitfld.long 0x08 0. " GPMI_MODE ,GPMI mode" "No effect,Clear" line.long 0x0C "CTRL1_TOG,GPMI Control Toggle Register 1" bitfld.long 0x0C 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Toggle" bitfld.long 0x0C 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Toggle" bitfld.long 0x0C 29. " WRITE_CLK_STOP ,Stop clock during data write" "No effect,Toggle" newline bitfld.long 0x0C 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Toggle" bitfld.long 0x0C 27. " GPMI_CLK_DIV2_EN ,GPMI CLK divider enable" "No effect,Toggle" bitfld.long 0x0C 26. " UPDATE_CS ,Force CS value update" "No effect,Toggle" newline bitfld.long 0x0C 25. " SSYNCMODE ,Source synchronous mode 1 or asynchronous mode 0" "ASYNC,SSYNC" bitfld.long 0x0C 24. " DECOUPLE_CS ,Decouple chip select from DMA channel" "No effect,Toggle" bitfld.long 0x0C 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" newline bitfld.long 0x0C 21. " TEST_TRIGGER ,Test trigger enable" "Disabled,Enabled" bitfld.long 0x0C 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and NAND mode" "No effect,Toggle" bitfld.long 0x0C 19. " GANGED_RDYBUSY ,NAND RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Toggle" newline bitfld.long 0x0C 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Toggle" bitfld.long 0x0C 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Toggle" bitfld.long 0x0C 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Toggle" newline bitfld.long 0x0C 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. " DMA2ECC_MODE ,DMA ECC mode. DMA write data to redirected to HWECC module (instead of NAND device) for encoding or decoding" "No effect,Toggle" bitfld.long 0x0C 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Toggle" newline bitfld.long 0x0C 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Toggle" bitfld.long 0x0C 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Toggle" bitfld.long 0x0C 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Toggle" newline bitfld.long 0x0C 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 3. " DEV_RESET ,Device reset" "No effect,Toggle" bitfld.long 0x0C 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Toggle" newline bitfld.long 0x0C 1. " CAMERA_MODE ,CAMERA mode" "No effect,Toggle" bitfld.long 0x0C 0. " GPMI_MODE ,GPMI mode" "No effect,Toggle" line.long 0x10 "TIMING0,GPMI Timing Register 0" hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted" hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles" hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles" group.long 0x80++0x03 line.long 0x00 "TIMING1,GPMI Timing Register 1" hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND ready/busy or ATA IRQ" group.long 0x90++0x03 line.long 0x00 "TIMING2,GPMI Timing Register 2" bitfld.long 0x00 29.--31. " TRPSTH ,NAND timing control delay between CEn_B high and RE_B high" "8,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " TCR ,NAND timing control delay between CEn_B low and RE_B low" "1,2,3,4" bitfld.long 0x00 24.--26. " READ_LATENCY ,Read latency" "0,1,2,3,4,5,3,3" newline bitfld.long 0x00 16.--20. " CE_DELAY ,CE delay" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--15. " PREAMBLE_DELAY ,Pre-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " POSTAMBLE_DELAY ,Post-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " CMDADD_PAUSE ,Delay time from command/address pause to command/address resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DATA_PAUSE ,Delay time from data pause to data resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x03 line.long 0x00 "DATA,GPMI DMA Data Transfer Register" rgroup.long 0xB0++0x03 line.long 0x00 "STAT,GPMI Status Register" hexmask.long.byte 0x00 24.--31. 1. " READY_BUSY ,NAND ready_busy input pins" bitfld.long 0x00 23. " RDY_TIMEOUT[7] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 22. " RDY_TIMEOUT[6] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 21. " RDY_TIMEOUT[5] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 20. " RDY_TIMEOUT[4] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 19. " RDY_TIMEOUT[3] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 18. " RDY_TIMEOUT[2] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 17. " RDY_TIMEOUT[1] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" bitfld.long 0x00 16. " RDY_TIMEOUT[0] ,State of the RDY/BUSY timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 15. " DEV7_ERROR ,Error condition on NAND device accessed by DMA channel 7" "No error,Error" bitfld.long 0x00 14. " DEV6_ERROR ,Error condition on NAND device accessed by DMA channel 6" "No error,Error" bitfld.long 0x00 13. " DEV5_ERROR ,Error condition on NAND device accessed by DMA channel 5" "No error,Error" newline bitfld.long 0x00 12. " DEV4_ERROR ,Error condition on NAND device accessed by DMA channel 4" "No error,Error" bitfld.long 0x00 11. " DEV3_ERROR ,Error condition on NAND device accessed by DMA channel 3" "No error,Error" bitfld.long 0x00 10. " DEV2_ERROR ,Error condition on NAND device accessed by DMA channel 2" "No error,Error" newline bitfld.long 0x00 9. " DEV1_ERROR ,Error condition on NAND device accessed by DMA channel 1" "No error,Error" bitfld.long 0x00 8. " DEV0_ERROR ,Error condition on NAND device accessed by DMA channel 0" "No error,Error" newline bitfld.long 0x00 4. " ATA_IRQ ,Status of ATA_IRQ input pin" "Low,High" bitfld.long 0x00 3. " INVALID_BUFFER_MASK ,ECC buffer mask validity" "Not invalid,Invalid" bitfld.long 0x00 2. " FIFO_EMPTY ,FIFO empty" "Not empty,Empty" newline bitfld.long 0x00 1. " FIFO_FULL ,FIFO full" "Not full,Full" bitfld.long 0x00 0. " PRESENT ,GPMI present" "Not present,Present" rgroup.long 0xC0++0x03 line.long 0x00 "DEBUG,GPMI Debug Information Register" bitfld.long 0x00 31. " WAIT_FOR_READY_END[7] ,WAIT_FOR_READY command end of channel 7" "Not occurred,Occurred" bitfld.long 0x00 30. " WAIT_FOR_READY_END[6] ,WAIT_FOR_READY command end of channel 6" "Not occurred,Occurred" bitfld.long 0x00 29. " WAIT_FOR_READY_END[5] ,WAIT_FOR_READY command end of channel 5" "Not occurred,Occurred" newline bitfld.long 0x00 28. " WAIT_FOR_READY_END[4] ,WAIT_FOR_READY command end of channel 4" "Not occurred,Occurred" bitfld.long 0x00 27. " WAIT_FOR_READY_END[3] ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred" bitfld.long 0x00 26. " WAIT_FOR_READY_END[2] ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred" newline bitfld.long 0x00 25. " WAIT_FOR_READY_END[1] ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred" bitfld.long 0x00 24. " WAIT_FOR_READY_END[0] ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred" bitfld.long 0x00 23. " DMA_SENSE[7] ,Indicates that a read and compare command failed or a timeout occurred for the channel 7" "Not occurred,Occurred" newline bitfld.long 0x00 22. " DMA_SENSE[6] ,Indicates that a read and compare command failed or a timeout occurred for the channel 6" "Not occurred,Occurred" bitfld.long 0x00 21. " DMA_SENSE[5] ,Indicates that a read and compare command failed or a timeout occurred for the channel 5" "Not occurred,Occurred" bitfld.long 0x00 20. " DMA_SENSE[4] ,Indicates that a read and compare command failed or a timeout occurred for the channel 4" "Not occurred,Occurred" newline bitfld.long 0x00 19. " DMA_SENSE[3] ,Indicates that a read and compare command failed or a timeout occurred for the channel 3" "Not occurred,Occurred" bitfld.long 0x00 18. " DMA_SENSE[2] ,Indicates that a read and compare command failed or a timeout occurred for the channel 2" "Not occurred,Occurred" bitfld.long 0x00 17. " DMA_SENSE[1] ,Indicates that a read and compare command failed or a timeout occurred for the channel 1" "Not occurred,Occurred" newline bitfld.long 0x00 16. " DMA_SENSE[0] ,Indicates that a read and compare command failed or a timeout occurred for the channel 0" "Not occurred,Occurred" bitfld.long 0x00 15. " DMAREQ[7] ,DMA request line for channel 7" "Not requested,Requested" bitfld.long 0x00 14. " DMAREQ[6] ,DMA request line for channel 6" "Not requested,Requested" newline bitfld.long 0x00 13. " DMAREQ[5] ,DMA request line for channel 5" "Not requested,Requested" bitfld.long 0x00 12. " DMAREQ[4] ,DMA request line for channel 4" "Not requested,Requested" bitfld.long 0x00 11. " DMAREQ[3] ,DMA request line for channel 3" "Not requested,Requested" newline bitfld.long 0x00 10. " DMAREQ[2] ,DMA request line for channel 2" "Not requested,Requested" bitfld.long 0x00 9. " DMAREQ[1] ,DMA request line for channel 1" "Not requested,Requested" bitfld.long 0x00 8. " DMAREQ[0] ,DMA request line for channel 0" "Not requested,Requested" newline bitfld.long 0x00 7. " CMD_END[7] ,Command end toggle to DMA channel 7" "Not finished,Finished" bitfld.long 0x00 6. " CMD_END[6] ,Command end toggle to DMA channel 6" "Not finished,Finished" bitfld.long 0x00 5. " CMD_END[5] ,Command end toggle to DMA channel 5" "Not finished,Finished" newline bitfld.long 0x00 4. " CMD_END[4] ,Command end toggle to DMA channel 4" "Not finished,Finished" bitfld.long 0x00 3. " CMD_END[3] ,Command end toggle to DMA channel 3" "Not finished,Finished" bitfld.long 0x00 2. " CMD_END[2] ,Command end toggle to DMA channel 2" "Not finished,Finished" newline bitfld.long 0x00 1. " CMD_END[1] ,Command end toggle to DMA channel 1" "Not finished,Finished" bitfld.long 0x00 0. " CMD_END[0] ,Command end toggle to DMA channel 0" "Not finished,Finished" rgroup.long 0xD0++0x03 line.long 0x00 "VERSION,GPMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0xE0++0x03 line.long 0x00 "DEBUG2,GPMI Debug2 Information Register" rbitfld.long 0x00 24.--27. " UDMA_STATE ,UDMA state" "USM_IDLE,USM_DMARQ,USM_ACK,USM_FIFO_E,USM_WPAUSE,USM_TSTRB,USM_CAPTUR,USM_DATOUT,USM_CRC,USM_WAIT_R,USM_END,USM_WAIT_S,USM_RPAUSE,USM_RSTOP,USM_WTERM,USM_RTERM" rbitfld.long 0x00 23. " BUSY ,Asserted GPMI is busy" "Not busy,Busy" rbitfld.long 0x00 20.--22. " PIN_STATE ,Pin state" "PSM_IDLE,PSM_BYTCNT,PSM_ADDR,PSM_STALL,PSM_STROBE,PSM_ATARDY,PSM_DHOLD,PSM_DONE" newline rbitfld.long 0x00 16.--19. " MAIN_STATE ,Main state" "MSM_IDLE,MSM_BYTCNT,MSM_WAITFE,MSM_WAITFR,MSM_DMAREQ,MSM_DMAACK,MSM_WAITFF,MSM_LDFIFO,MSM_LDDMAR,MSM_RDCMP,MSM_DONE,?..." rbitfld.long 0x00 12.--15. " SYND2GPMI_BE ,Data byte enable input from BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 11. " GPMI2SYND_VALID ,Data handshake output to BCH" "Not valid,Valid" newline rbitfld.long 0x00 10. " GPMI2SYND_READY ,Data handshake output to BCH" "Not ready,Ready" rbitfld.long 0x00 9. " SYND2GPMI_VALID ,Data handshake input from BCH" "Not valid,Valid" rbitfld.long 0x00 8. " SYND2GPMI_READY ,Data handshake input from BCH" "Not ready,Ready" newline bitfld.long 0x00 7. " VIEW_DELAYED_RDN ,Feedback RDN to drive the GPMI_ADDR[0]" "No delay,Delay" rbitfld.long 0x00 6. " UPDATE_WINDOW ,DLL is busy generating the required delay" "No,Yes" rbitfld.long 0x00 0.--5. " RDN_TAP ,DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xF0++0x03 line.long 0x00 "DEBUG3,GPMI Debug3 Information Register Description" hexmask.long.word 0x00 16.--31. 1. " APB_WORD_CNTR ,Number of words remains to be transferred on the APB bus" hexmask.long.word 0x00 0.--15. 1. " DEV_WORD_CNTR ,Number of words remains to be transferred on the ATA/NAND bus" width 20. tree "GPMI Double Rate Read DLL Control&Status Register Description" group.long 0x100++0x03 line.long 0x00 "READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register Description" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" newline bitfld.long 0x00 7. " GATE_UPDATE ,Forces the slave delay line is not updated" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Forces the slave delay line to update" "No effect,Updated" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" group.long 0x110++0x03 line.long 0x00 "WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register Description" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" newline bitfld.long 0x00 7. " GATE_UPDATE ,Forces the slave delay line is not updated" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Forces the slave delay line to update" "No effect,Updated" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x120++0x03 line.long 0x00 "READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register Description" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" sif (cpuis("IMX8*")) bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" endif rgroup.long 0x130++0x03 line.long 0x00 "WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register Description" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" tree.end width 0x0B tree.end tree "EIM (External Interface Module)" base ad:0x30BC0000 width 10. tree "CS_0" if (((per.l(ad:0x30BC0000+0x0))&0x06)==0x06) group.long 0x0++0x03 line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x0))&0x06)==0x04) group.long 0x0++0x03 line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x0))&0x06)==0x02) group.long 0x0++0x03 line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x0++0x03 line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x0))&0x06)!=0x06) group.long (0x0+0x04)++0x03 line.long 0x00 "CS0GCR2,Chip Select 0 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x0+0x04)++0x03 line.long 0x00 "CS0GCR2,Chip Select 0 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x0))&0x04)==0x04) group.long (0x0+0x08)++0x03 line.long 0x00 "CS0RCR1,Chip Select 0 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x0+0x08)++0x03 line.long 0x00 "CS0RCR1,Chip Select 0 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x0))&0x3004)==0x00) group.long (0x0+0x0C)++0x03 line.long 0x00 "CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x0))&0x3004)==0x04) group.long (0x0+0x0C)++0x03 line.long 0x00 "CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x0))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x0+0x0C)++0x03 line.long 0x00 "CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x0+0x0C)++0x03 line.long 0x00 "CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x0))&0x02)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "CS0WCR1,Chip Select 0 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x0+0x10)++0x03 line.long 0x00 "CS0WCR1,Chip Select 0 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x0+0x14)++0x03 line.long 0x00 "CS0WCR2,Chip Select 0 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end tree "CS_1" if (((per.l(ad:0x30BC0000+0x18))&0x06)==0x06) group.long 0x18++0x03 line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x18))&0x06)==0x04) group.long 0x18++0x03 line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x18))&0x06)==0x02) group.long 0x18++0x03 line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x18))&0x06)!=0x06) group.long (0x18+0x04)++0x03 line.long 0x00 "CS1GCR2,Chip Select 1 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x18+0x04)++0x03 line.long 0x00 "CS1GCR2,Chip Select 1 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x18))&0x04)==0x04) group.long (0x18+0x08)++0x03 line.long 0x00 "CS1RCR1,Chip Select 1 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x18+0x08)++0x03 line.long 0x00 "CS1RCR1,Chip Select 1 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x18))&0x3004)==0x00) group.long (0x18+0x0C)++0x03 line.long 0x00 "CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x18))&0x3004)==0x04) group.long (0x18+0x0C)++0x03 line.long 0x00 "CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x18))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x18+0x0C)++0x03 line.long 0x00 "CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x18+0x0C)++0x03 line.long 0x00 "CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x18))&0x02)==0x00) group.long (0x18+0x10)++0x03 line.long 0x00 "CS1WCR1,Chip Select 1 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x18+0x10)++0x03 line.long 0x00 "CS1WCR1,Chip Select 1 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x18+0x14)++0x03 line.long 0x00 "CS1WCR2,Chip Select 1 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end tree "CS_2" if (((per.l(ad:0x30BC0000+0x30))&0x06)==0x06) group.long 0x30++0x03 line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x30))&0x06)==0x04) group.long 0x30++0x03 line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x30))&0x06)==0x02) group.long 0x30++0x03 line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x30++0x03 line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x30))&0x06)!=0x06) group.long (0x30+0x04)++0x03 line.long 0x00 "CS2GCR2,Chip Select 2 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x30+0x04)++0x03 line.long 0x00 "CS2GCR2,Chip Select 2 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x30))&0x04)==0x04) group.long (0x30+0x08)++0x03 line.long 0x00 "CS2RCR1,Chip Select 2 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x30+0x08)++0x03 line.long 0x00 "CS2RCR1,Chip Select 2 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x30))&0x3004)==0x00) group.long (0x30+0x0C)++0x03 line.long 0x00 "CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x30))&0x3004)==0x04) group.long (0x30+0x0C)++0x03 line.long 0x00 "CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x30))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x30+0x0C)++0x03 line.long 0x00 "CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x30+0x0C)++0x03 line.long 0x00 "CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x30))&0x02)==0x00) group.long (0x30+0x10)++0x03 line.long 0x00 "CS2WCR1,Chip Select 2 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x30+0x10)++0x03 line.long 0x00 "CS2WCR1,Chip Select 2 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x30+0x14)++0x03 line.long 0x00 "CS2WCR2,Chip Select 2 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end tree "CS_3" if (((per.l(ad:0x30BC0000+0x48))&0x06)==0x06) group.long 0x48++0x03 line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x48))&0x06)==0x04) group.long 0x48++0x03 line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x48))&0x06)==0x02) group.long 0x48++0x03 line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x48))&0x06)!=0x06) group.long (0x48+0x04)++0x03 line.long 0x00 "CS3GCR2,Chip Select 3 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x48+0x04)++0x03 line.long 0x00 "CS3GCR2,Chip Select 3 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x48))&0x04)==0x04) group.long (0x48+0x08)++0x03 line.long 0x00 "CS3RCR1,Chip Select 3 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x48+0x08)++0x03 line.long 0x00 "CS3RCR1,Chip Select 3 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x48))&0x3004)==0x00) group.long (0x48+0x0C)++0x03 line.long 0x00 "CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x48))&0x3004)==0x04) group.long (0x48+0x0C)++0x03 line.long 0x00 "CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x48))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x48+0x0C)++0x03 line.long 0x00 "CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x48+0x0C)++0x03 line.long 0x00 "CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x48))&0x02)==0x00) group.long (0x48+0x10)++0x03 line.long 0x00 "CS3WCR1,Chip Select 3 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x48+0x10)++0x03 line.long 0x00 "CS3WCR1,Chip Select 3 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x48+0x14)++0x03 line.long 0x00 "CS3WCR2,Chip Select 3 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end tree "CS_4" if (((per.l(ad:0x30BC0000+0x60))&0x06)==0x06) group.long 0x60++0x03 line.long 0x00 "CS4GCR1,Chip Select 4 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x60))&0x06)==0x04) group.long 0x60++0x03 line.long 0x00 "CS4GCR1,Chip Select 4 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x60))&0x06)==0x02) group.long 0x60++0x03 line.long 0x00 "CS4GCR1,Chip Select 4 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "CS4GCR1,Chip Select 4 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x60))&0x06)!=0x06) group.long (0x60+0x04)++0x03 line.long 0x00 "CS4GCR2,Chip Select 4 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x60+0x04)++0x03 line.long 0x00 "CS4GCR2,Chip Select 4 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x60))&0x04)==0x04) group.long (0x60+0x08)++0x03 line.long 0x00 "CS4RCR1,Chip Select 4 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x60+0x08)++0x03 line.long 0x00 "CS4RCR1,Chip Select 4 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x60))&0x3004)==0x00) group.long (0x60+0x0C)++0x03 line.long 0x00 "CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x60))&0x3004)==0x04) group.long (0x60+0x0C)++0x03 line.long 0x00 "CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x60))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x60+0x0C)++0x03 line.long 0x00 "CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x60+0x0C)++0x03 line.long 0x00 "CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x60))&0x02)==0x00) group.long (0x60+0x10)++0x03 line.long 0x00 "CS4WCR1,Chip Select 4 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x60+0x10)++0x03 line.long 0x00 "CS4WCR1,Chip Select 4 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x60+0x14)++0x03 line.long 0x00 "CS4WCR2,Chip Select 4 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end tree "CS_5" if (((per.l(ad:0x30BC0000+0x78))&0x06)==0x06) group.long 0x78++0x03 line.long 0x00 "CS5GCR1,Chip Select 5 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x78))&0x06)==0x04) group.long 0x78++0x03 line.long 0x00 "CS5GCR1,Chip Select 5 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x78))&0x06)==0x02) group.long 0x78++0x03 line.long 0x00 "CS5GCR1,Chip Select 5 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" else group.long 0x78++0x03 line.long 0x00 "CS5GCR1,Chip Select 5 General Control Register 1" bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..." bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]" bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous" bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..." bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled" endif if (((per.l(ad:0x30BC0000+0x78))&0x06)!=0x06) group.long (0x78+0x04)++0x03 line.long 0x00 "CS5GCR2,Chip Select 5 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles" bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." else group.long (0x78+0x04)++0x03 line.long 0x00 "CS5GCR2,Chip Select 5 General Control Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..." endif if (((per.l(ad:0x30BC0000+0x78))&0x04)==0x04) group.long (0x78+0x08)++0x03 line.long 0x00 "CS5RCR1,Chip Select 5 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x78+0x08)++0x03 line.long 0x00 "CS5RCR1,Chip Select 5 Read Configuration Register 1" bitfld.long 0x00 24.--29. " RWSC ,Read wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--22. " RADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 19. " RAL ,Read ADV low" "RADVN,Ignored" bitfld.long 0x00 16.--18. " RADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 12.--14. " OEA ,OE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 8.--10. " OEN ,OE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 4.--6. " RCSA ,Read CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RCSN ,Read CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x78))&0x3004)==0x00) group.long (0x78+0x0C)++0x03 line.long 0x00 "CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" elif (((per.l(ad:0x30BC0000+0x78))&0x3004)==0x04) group.long (0x78+0x0C)++0x03 line.long 0x00 "CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1,2,3,4" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" elif (((per.l(ad:0x30BC0000+0x78))&0x3004)==(0x1004||0x2004||0x3004)) group.long (0x78+0x0C)++0x03 line.long 0x00 "CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" else group.long (0x78+0x0C)++0x03 line.long 0x00 "CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x00 15. " APR ,Asynchronous page read" "Word,Page" bitfld.long 0x00 12.--14. " PAT ,Page access time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles" bitfld.long 0x00 8.--9. " RL ,Read latency" "1.5,2.5,3.5,4.5" textline " " bitfld.long 0x00 4.--6. " RBEA ,Read BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RBEN ,Read /BE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif if (((per.l(ad:0x30BC0000+0x78))&0x02)==0x00) group.long (0x78+0x10)++0x03 line.long 0x00 "CS5WCR1,Chip Select 5 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "AWADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 15.--17. " WBEA ,BE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WEN ,WE negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " WCSN ,Write CS negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" else group.long (0x78+0x10)++0x03 line.long 0x00 "CS5WCR1,Chip Select 5 Write Configuration Register 1" bitfld.long 0x00 31. " WAL ,Write ADV low" "WADVN,Ignored" bitfld.long 0x00 30. " WBED ,Write byte enable disable" "No,Yes" bitfld.long 0x00 24.--29. " WWSC ,Write wait state control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21.--23. " WADVA ,ADV assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 18.--20. " WADVN ,ADV negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WEA ,WE assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " WCSA ,Write CS assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" endif group.long (0x78+0x14)++0x03 line.long 0x00 "CS5WCR2,Chip Select 5 Write Configuration Register 2" bitfld.long 0x00 0. " WBCDD ,Write burst clock divisor decrement" "No effect,Preformed" tree.end width 6. textline " " group.long 0x90++0x03 line.long 0x00 "WCR,EIM Configuration Register" bitfld.long 0x00 11. " FRUN_ACLK_EN ,Free run ACLK enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory wdog cycle limit" "128 cycles,256 cycles,512 cycles,1024 cycles" bitfld.long 0x00 8. " WDOG_EN ,Memory wdog enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INTPOL ,Interrupt polarity" "Active low,Active high" bitfld.long 0x00 4. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CONT_BCLK_SEL ,Continuous BCLK select" "BCLK,BCLK continuous" textline " " bitfld.long 0x00 1.--2. " GBCD ,General burst clock divisor" "Div by 1,Div by 2,Div by 3,Div by 4" bitfld.long 0x00 0. " BCM ,Burst clock mode" "Depend on CS config,When ACLK active" if (((per.l(ad:0x30BC0000+0x94))&0x100)==0x100) group.long 0x94++0x03 line.long 0x00 "DCR,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,Reference DLL update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--27. " DLL_CTRL_SLV_UPDATE_INT ,Slave DLL update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--22. 1. " DLL_CTRL_REF_INITIAL_VAL ,Selects the initial value of reference chain before DLL enabled" textline " " hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Physical tap manual select" bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain using SLV_OVERRIDE_VAL enable" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatic,Stopped" textline " " bitfld.long 0x00 4.--6. " DLL_CTRL_SLV_OFFSET ,OFFSET value for DLL_CTRL_SLV_SEL" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DLL_CTRL_SLV_OFFSET_DEC ,Slave chain offset decrease" "Increased,Decreased" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,Immediate update of the slave delay line to the DLL calibrated value" "Not updated,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset bit" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL and delay chain enable" "Disabled,Enabled" else group.long 0x94++0x03 line.long 0x00 "DCR,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,Reference DLL update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--27. " DLL_CTRL_SLV_UPDATE_INT ,Slave DLL update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 16.--22. 1. " DLL_CTRL_REF_INITIAL_VAL ,Selects the initial value of reference chain before DLL enabled" bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain using SLV_OVERRIDE_VAL enable" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatic,Stopped" textline " " bitfld.long 0x00 4.--6. " DLL_CTRL_SLV_OFFSET ,OFFSET value for DLL_CTRL_SLV_SEL" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DLL_CTRL_SLV_OFFSET_DEC ,Slave chain offset decrease" "Increased,Decreased" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,Immediate update of the slave delay line to the DLL calibrated value" "Not updated,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset bit" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL and delay chain enable" "Disabled,Enabled" endif group.long 0x98++0x07 line.long 0x00 "DSR,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Unlocked,Locked" line.long 0x04 "WIAR,IP Access Register" bitfld.long 0x04 4. " ACLK_EN ,ACLK enable" "Disabled,Enabled" bitfld.long 0x04 3. " ERRST ,READY after reset" "Disabled,Enabled" bitfld.long 0x04 2. " INT ,Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " IPS_ACK ,Master can access IPS" "No,Yes" bitfld.long 0x04 0. " IPS_REQ ,IPS request" "No request,Request" rgroup.long 0xA0++0x03 line.long 0x00 "EAR,Error Address Register" width 0x0B tree.end tree.open "ECSPI (Enhanced Configurable Serial Peripheral Interface)" tree "ECSPI_1" base ad:0x30820000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30820000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30820000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30820000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI_2" base ad:0x30830000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30830000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30830000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30830000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI_3" base ad:0x30840000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30840000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30840000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30840000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI_4" base ad:0x30630000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "RXDATA,Receive Data Register" in wgroup.long 0x04++0x03 line.long 0x00 "TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst length" bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select" "0,1,2,3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..." textline " " bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master" textline " " bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start mode control" "Normal,Automatic" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Exchanged/busy" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,SPI module enable control" "Disabled,Enabled" if (((per.l(ad:0x30630000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SS for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SS for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SS for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SS for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x30630000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,An SPI burst is completed by the chip select (SS) signal edges" "SS edge,?..." textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" else group.long 0x0C++0x03 line.long 0x00 "CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL[3] ,Control polarity of SSB for SPI channel 3" "Active low,Active high" bitfld.long 0x00 14. " SS_POL[2] ,Control polarity of SSB for SPI channel 2" "Active low,Active high" bitfld.long 0x00 13. " SS_POL[1] ,Control polarity of SSB for SPI channel 1" "Active low,Active high" bitfld.long 0x00 12. " SS_POL[0] ,Control polarity of SSB for SPI channel 0" "Active low,Active high" textline " " bitfld.long 0x00 11. " SS_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple" bitfld.long 0x00 10. " SS_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple" bitfld.long 0x00 9. " SS_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple" bitfld.long 0x00 8. " SS_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple" textline " " bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK polarity of SPI channel 3" "Active high,Active low" bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK polarity of SPI channel 2" "Active high,Active low" bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK polarity of SPI channel 1" "Active high,Active low" bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK polarity of SPI channel 0" "Active high,Active low" textline " " bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB polarity of SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB polarity of SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB polarity of SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB polarity of SPI channel 0" "Phase 0,Phase 1" endif textline " " group.long 0x10++0x07 line.long 0x00 "INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x30630000+0x14))&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" else group.long 0x18++0x03 line.long 0x00 "STATREG,Status Register" eventfld.long 0x00 7. " TC ,Transfer completed" "In progress,Completed" eventfld.long 0x00 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x00 5. " RF ,RXFIFO full" "Not full,Full" rbitfld.long 0x00 4. " RDR ,RXFIFO data request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA" textline " " rbitfld.long 0x00 3. " RR ,RXFIFO ready" "No valid data,>=1 word" rbitfld.long 0x00 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x00 1. " TDR ,TXFIFO data request" ">TX THRESHOLD,<=TX THRESHOLD" rbitfld.long 0x00 0. " TE ,TXFIFO empty" "Not empty,Empty" endif group.long 0x1C++0x07 line.long 0x00 "PERIODREG,Sample Period Control Register" bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip select delay control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " CSRC ,Clock source control" "SPI clock,Low-Frequency Ref. Clock" hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample period control" line.long 0x04 "TESTREG,Test Control Register" bitfld.long 0x04 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "MSGDATA,Message Data Register" width 0x0B tree.end tree.end tree.open "QuadSPI (Quad Serial Peripheral Interface)" tree "AHB (AHB RX Data Buffer)" base ad:0x34000000 width 8. sif (cpu()=="IMX7ULP-CA7")||(cpu()=="IMX7ULP-CM4") group.long 0x0++0x03 line.long 0x00 "ARDB0,AHB RX Data Buffer Register" group.long 0x4++0x03 line.long 0x00 "ARDB1,AHB RX Data Buffer Register" group.long 0x8++0x03 line.long 0x00 "ARDB2,AHB RX Data Buffer Register" group.long 0xC++0x03 line.long 0x00 "ARDB3,AHB RX Data Buffer Register" group.long 0x10++0x03 line.long 0x00 "ARDB4,AHB RX Data Buffer Register" group.long 0x14++0x03 line.long 0x00 "ARDB5,AHB RX Data Buffer Register" group.long 0x18++0x03 line.long 0x00 "ARDB6,AHB RX Data Buffer Register" group.long 0x1C++0x03 line.long 0x00 "ARDB7,AHB RX Data Buffer Register" group.long 0x20++0x03 line.long 0x00 "ARDB8,AHB RX Data Buffer Register" group.long 0x24++0x03 line.long 0x00 "ARDB9,AHB RX Data Buffer Register" group.long 0x28++0x03 line.long 0x00 "ARDB10,AHB RX Data Buffer Register" group.long 0x2C++0x03 line.long 0x00 "ARDB11,AHB RX Data Buffer Register" group.long 0x30++0x03 line.long 0x00 "ARDB12,AHB RX Data Buffer Register" group.long 0x34++0x03 line.long 0x00 "ARDB13,AHB RX Data Buffer Register" group.long 0x38++0x03 line.long 0x00 "ARDB14,AHB RX Data Buffer Register" group.long 0x3C++0x03 line.long 0x00 "ARDB15,AHB RX Data Buffer Register" else group.long 0x0++0x03 line.long 0x00 "ARDB0,AHB RX Data Buffer Register" group.long 0x4++0x03 line.long 0x00 "ARDB1,AHB RX Data Buffer Register" group.long 0x8++0x03 line.long 0x00 "ARDB2,AHB RX Data Buffer Register" group.long 0xC++0x03 line.long 0x00 "ARDB3,AHB RX Data Buffer Register" group.long 0x10++0x03 line.long 0x00 "ARDB4,AHB RX Data Buffer Register" group.long 0x14++0x03 line.long 0x00 "ARDB5,AHB RX Data Buffer Register" group.long 0x18++0x03 line.long 0x00 "ARDB6,AHB RX Data Buffer Register" group.long 0x1C++0x03 line.long 0x00 "ARDB7,AHB RX Data Buffer Register" group.long 0x20++0x03 line.long 0x00 "ARDB8,AHB RX Data Buffer Register" group.long 0x24++0x03 line.long 0x00 "ARDB9,AHB RX Data Buffer Register" group.long 0x28++0x03 line.long 0x00 "ARDB10,AHB RX Data Buffer Register" group.long 0x2C++0x03 line.long 0x00 "ARDB11,AHB RX Data Buffer Register" group.long 0x30++0x03 line.long 0x00 "ARDB12,AHB RX Data Buffer Register" group.long 0x34++0x03 line.long 0x00 "ARDB13,AHB RX Data Buffer Register" group.long 0x38++0x03 line.long 0x00 "ARDB14,AHB RX Data Buffer Register" group.long 0x3C++0x03 line.long 0x00 "ARDB15,AHB RX Data Buffer Register" group.long 0x40++0x03 line.long 0x00 "ARDB16,AHB RX Data Buffer Register" group.long 0x44++0x03 line.long 0x00 "ARDB17,AHB RX Data Buffer Register" group.long 0x48++0x03 line.long 0x00 "ARDB18,AHB RX Data Buffer Register" group.long 0x4C++0x03 line.long 0x00 "ARDB19,AHB RX Data Buffer Register" group.long 0x50++0x03 line.long 0x00 "ARDB20,AHB RX Data Buffer Register" group.long 0x54++0x03 line.long 0x00 "ARDB21,AHB RX Data Buffer Register" group.long 0x58++0x03 line.long 0x00 "ARDB22,AHB RX Data Buffer Register" group.long 0x5C++0x03 line.long 0x00 "ARDB23,AHB RX Data Buffer Register" group.long 0x60++0x03 line.long 0x00 "ARDB24,AHB RX Data Buffer Register" group.long 0x64++0x03 line.long 0x00 "ARDB25,AHB RX Data Buffer Register" group.long 0x68++0x03 line.long 0x00 "ARDB26,AHB RX Data Buffer Register" group.long 0x6C++0x03 line.long 0x00 "ARDB27,AHB RX Data Buffer Register" group.long 0x70++0x03 line.long 0x00 "ARDB28,AHB RX Data Buffer Register" group.long 0x74++0x03 line.long 0x00 "ARDB29,AHB RX Data Buffer Register" group.long 0x78++0x03 line.long 0x00 "ARDB30,AHB RX Data Buffer Register" group.long 0x7C++0x03 line.long 0x00 "ARDB31,AHB RX Data Buffer Register" endif width 0x0B tree.end tree "QuadSPI_1" base ad:0x30BB0000 width 9. sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if ((per.l(ad:0x30BB0000)&0x4000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" bitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" rbitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" rbitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif else if ((per.l(ad:0x30BB0000)&0x2000040)==0x2000040) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 26. " DQS_PHASE_EN ,Control of internal DQS output phase" "Disabled,Enabled" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB0000)&0x2000040)==0x40) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB0000)&0x2000040)==0x2000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) if ((per.l(ad:0x30BB0000)&0x80)==0x00) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if ((per.l(ad:0x30BB0000)&0x80)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif else if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif newline if (((per.l(ad:0x30BB0000+0x15C))&0x04)==0x00) group.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif cpuis("IMX7ULP*") bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("IMX7ULP*") rgroup.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x30BB0000)&0x4000)==0x4000)) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX buffer" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--12. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--13. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x30BB0000+0x15C))&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Field indicates how many entries of 4 bytes have been written into the TX buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX buffer for the quadspi module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30BB0000+0x15C))&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x158++0x03 line.long 0x00 "TBCT,TX Buffer Control Register" bitfld.long 0x00 0.--3. " WMRK ,TX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" endif rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 26. " TXDMA ,TXFIFO fill via DMA is active" "Not active,Active" newline bitfld.long 0x00 25. " TXWA ,TX buffer watermark available" "Not available,Available" bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" else bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" endif newline bitfld.long 0x00 23. " RXDMA ,RX buffer read out via DMA" "Not active,Active" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" newline bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" newline bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "No,Yes" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "No,Yes" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "No,Yes" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "No,Yes" newline bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not AHB initiated,AHB initiated" newline bitfld.long 0x00 1. " IP_ACC ,IP access" "Not IP bus initiated,IP bus initiated" bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" group.long 0x160++0x07 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 31. " DLPFF ,Data learning pattern failure" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX buffer fulfilment" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun" "Not occurred,Occurred" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error" "Not occurred,Occurred" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 16. " RBDF ,RX buffer drain" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB sequence error" "Not occurred,Occurred" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) eventfld.long 0x00 14. " AITEF ,AHB illegal transaction error" "Not occurred,Occurred" newline eventfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error" "Not occurred,Occurred" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" newline eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" else eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" newline eventfld.long 0x00 11. " IUEF ,IP command usage error" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" newline eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" endif line.long 0x04 "RSER,Interrupt And DMA Request Select And Enable Register" bitfld.long 0x04 31. " DLPFIE ,Data learning pattern failure interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" else bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" endif newline bitfld.long 0x04 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x04 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" bitfld.long 0x04 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 14. " AITIE ,AHB illegal transaction interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " AIBISIE ,AHB illegal burst size interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x04 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " IUEIE ,AIP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30BB0000+0x168))&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 9.--14. " DATLFT ,Data left" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" endif bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" else group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" endif if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif else sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) rgroup.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else rgroup.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x15C)&0x06)==0x00)) group.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" else rgroup.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x0) group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" else hgroup.long 0x200++0x03 hide.long 0x00 "RBDR0,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x100) group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" else hgroup.long 0x204++0x03 hide.long 0x00 "RBDR1,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x200) group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" else hgroup.long 0x208++0x03 hide.long 0x00 "RBDR2,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x300) group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" else hgroup.long 0x20C++0x03 hide.long 0x00 "RBDR3,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x400) group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" else hgroup.long 0x210++0x03 hide.long 0x00 "RBDR4,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x500) group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" else hgroup.long 0x214++0x03 hide.long 0x00 "RBDR5,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x600) group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" else hgroup.long 0x218++0x03 hide.long 0x00 "RBDR6,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x700) group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" else hgroup.long 0x21C++0x03 hide.long 0x00 "RBDR7,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x800) group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" else hgroup.long 0x220++0x03 hide.long 0x00 "RBDR8,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0x900) group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" else hgroup.long 0x224++0x03 hide.long 0x00 "RBDR9,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xA00) group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" else hgroup.long 0x228++0x03 hide.long 0x00 "RBDR10,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xB00) group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" else hgroup.long 0x22C++0x03 hide.long 0x00 "RBDR11,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xC00) group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" else hgroup.long 0x230++0x03 hide.long 0x00 "RBDR12,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xD00) group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" else hgroup.long 0x234++0x03 hide.long 0x00 "RBDR13,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xE00) group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" else hgroup.long 0x238++0x03 hide.long 0x00 "RBDR14,RX Buffer Data Register" endif if (((per.l(ad:0x30BB0000+0x10C))&0x1F00)>0xF00) group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" else hgroup.long 0x23C++0x03 hide.long 0x00 "RBDR15,RX Buffer Data Register" endif else group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" group.long 0x240++0x03 line.long 0x00 "RBDR16,RX Buffer Data Register" group.long 0x244++0x03 line.long 0x00 "RBDR17,RX Buffer Data Register" group.long 0x248++0x03 line.long 0x00 "RBDR18,RX Buffer Data Register" group.long 0x24C++0x03 line.long 0x00 "RBDR19,RX Buffer Data Register" group.long 0x250++0x03 line.long 0x00 "RBDR20,RX Buffer Data Register" group.long 0x254++0x03 line.long 0x00 "RBDR21,RX Buffer Data Register" group.long 0x258++0x03 line.long 0x00 "RBDR22,RX Buffer Data Register" group.long 0x25C++0x03 line.long 0x00 "RBDR23,RX Buffer Data Register" group.long 0x260++0x03 line.long 0x00 "RBDR24,RX Buffer Data Register" group.long 0x264++0x03 line.long 0x00 "RBDR25,RX Buffer Data Register" group.long 0x268++0x03 line.long 0x00 "RBDR26,RX Buffer Data Register" group.long 0x26C++0x03 line.long 0x00 "RBDR27,RX Buffer Data Register" group.long 0x270++0x03 line.long 0x00 "RBDR28,RX Buffer Data Register" group.long 0x274++0x03 line.long 0x00 "RBDR29,RX Buffer Data Register" group.long 0x278++0x03 line.long 0x00 "RBDR30,RX Buffer Data Register" group.long 0x27C++0x03 line.long 0x00 "RBDR31,RX Buffer Data Register" endif group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "No effect,Unlock" bitfld.long 0x04 0. " LOCK ,LUT lock" "No effect,Lock" width 7. tree "Look-up Tables" group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" tree.end width 0x0B tree.end tree "QuadSPI_2" base ad:0x30BB4000 width 9. sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if ((per.l(ad:0x30BB4000)&0x4000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" bitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" rbitfld.long 0x00 17. " ISD3FA ,Idle Signal Drive IOFA[3] Flash A" "Disabled,Enabled" rbitfld.long 0x00 16. " ISD2FA ,Idle Signal Drive IOFA[2] Flash A" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif else if ((per.l(ad:0x30BB4000)&0x2000040)==0x2000040) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 26. " DQS_PHASE_EN ,Control of internal DQS output phase" "Disabled,Enabled" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB4000)&0x2000040)==0x40) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" elif ((per.l(ad:0x30BB4000)&0x2000040)==0x2000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 25. " DQS_LOOPBACK_EN ,DQS loopback sampling enable" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_FROM_PAD ,DQS_LOOPBACK_FROM_PAD" "0,1" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/buffer" "No effect,Clear" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No reset,Reset" endif endif if (((per.l(ad:0x30BB4000+0x15C))&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB4000+0x15C)&0x06)==0x00)) if ((per.l(ad:0x30BB4000)&0x80)==0x00) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if ((per.l(ad:0x30BB4000)&0x80)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" textfld " " bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "POSEDGE of internal ref clk,2x serial flash half clock,4x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif else if (((per.l(ad:0x30BB4000+0x15C)&0x06)==0x00)) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Quadspi's internal ref clock,2x serial flash half clock,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif newline if (((per.l(ad:0x30BB4000+0x15C))&0x04)==0x00) group.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif cpuis("IMX7ULP*") hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif cpuis("IMX7ULP*") hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif cpuis("IMX7ULP*") bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" else hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" endif bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("IMX7ULP*") rgroup.long 0x24++0x03 line.long 0x00 "SOCCR,SOC Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " DQSDLY ,Delay chain tap selection (fine tuning) for QuadSPI DQS clock" newline bitfld.long 0x00 12. " DQSINVSEL ,DQS generation clock inverted" "Not inverted,Inverted" bitfld.long 0x00 10.--11. " DQSPHASE ,Phase shift for the internal DQS generation" "No shift,45 degree,90 degree,135 degree" newline bitfld.long 0x00 9. " DQSPADLPEN ,DQS external loopback enable" "Disabled,Enabled" bitfld.long 0x00 8. " DQSLPEN ,Internal DQS loopback enable" "Disabled,Enabled" endif rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l(ad:0x30BB4000+0x15C))&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB4000+0x15C)&0x06)==0x00)) group.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte addressable,Word addressable" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x30BB4000)&0x4000)==0x4000)) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instruction" "Not inverted,Inverted" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 cycle,2 cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Not inverted,Inverted" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" endif endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX buffer" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--12. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--13. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x30BB4000+0x15C))&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB bus,IP bus" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 0.--3. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" else bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX buffer is triggered" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Field indicates how many entries of 4 bytes have been written into the TX buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX buffer for the quadspi module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x30BB4000+0x15C))&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x158++0x03 line.long 0x00 "TBCT,TX Buffer Control Register" bitfld.long 0x00 0.--3. " WMRK ,TX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes" endif rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 26. " TXDMA ,TXFIFO fill via DMA is active" "Not active,Active" newline bitfld.long 0x00 25. " TXWA ,TX buffer watermark available" "Not available,Available" bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" else bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" endif newline bitfld.long 0x00 23. " RXDMA ,RX buffer read out via DMA" "Not active,Active" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" newline bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" newline bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "No,Yes" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "No,Yes" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "No,Yes" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "No,Yes" newline bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not AHB initiated,AHB initiated" newline bitfld.long 0x00 1. " IP_ACC ,IP access" "Not IP bus initiated,IP bus initiated" bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" group.long 0x160++0x07 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 31. " DLPFF ,Data learning pattern failure" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX buffer fulfilment" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun" "Not occurred,Occurred" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error" "Not occurred,Occurred" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 16. " RBDF ,RX buffer drain" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB sequence error" "Not occurred,Occurred" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) eventfld.long 0x00 14. " AITEF ,AHB illegal transaction error" "Not occurred,Occurred" newline eventfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error" "Not occurred,Occurred" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" newline eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" else eventfld.long 0x00 12. " ABOF ,AHB buffer overflow" "Not occurred,Occurred" newline eventfld.long 0x00 11. " IUEF ,IP command usage error" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed" "Not occurred,Occurred" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant" "Not occurred,Occurred" newline eventfld.long 0x00 0. " TFF ,IP command transaction finished" "Not occurred,Occurred" endif line.long 0x04 "RSER,Interrupt And DMA Request Select And Enable Register" bitfld.long 0x04 31. " DLPFIE ,Data learning pattern failure interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" else bitfld.long 0x04 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" endif newline bitfld.long 0x04 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x04 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" bitfld.long 0x04 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 14. " AITIE ,AHB illegal transaction interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " AIBISIE ,AHB illegal burst size interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x04 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " IUEIE ,AIP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30BB4000+0x168))&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 9.--14. " DATLFT ,Data left" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" endif bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Not suspended,Suspended" endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" else group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" endif if (((per.l(ad:0x30BB4000+0x15C)&0x06)==0x00)) sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) group.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif else sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) rgroup.long 0x180++0x07 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" else rgroup.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB4000+0x15C)&0x06)==0x00)) group.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" else rgroup.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" endif endif sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x0) group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" else hgroup.long 0x200++0x03 hide.long 0x00 "RBDR0,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x100) group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" else hgroup.long 0x204++0x03 hide.long 0x00 "RBDR1,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x200) group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" else hgroup.long 0x208++0x03 hide.long 0x00 "RBDR2,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x300) group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" else hgroup.long 0x20C++0x03 hide.long 0x00 "RBDR3,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x400) group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" else hgroup.long 0x210++0x03 hide.long 0x00 "RBDR4,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x500) group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" else hgroup.long 0x214++0x03 hide.long 0x00 "RBDR5,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x600) group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" else hgroup.long 0x218++0x03 hide.long 0x00 "RBDR6,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x700) group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" else hgroup.long 0x21C++0x03 hide.long 0x00 "RBDR7,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x800) group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" else hgroup.long 0x220++0x03 hide.long 0x00 "RBDR8,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0x900) group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" else hgroup.long 0x224++0x03 hide.long 0x00 "RBDR9,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xA00) group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" else hgroup.long 0x228++0x03 hide.long 0x00 "RBDR10,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xB00) group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" else hgroup.long 0x22C++0x03 hide.long 0x00 "RBDR11,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xC00) group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" else hgroup.long 0x230++0x03 hide.long 0x00 "RBDR12,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xD00) group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" else hgroup.long 0x234++0x03 hide.long 0x00 "RBDR13,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xE00) group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" else hgroup.long 0x238++0x03 hide.long 0x00 "RBDR14,RX Buffer Data Register" endif if (((per.l(ad:0x30BB4000+0x10C))&0x1F00)>0xF00) group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" else hgroup.long 0x23C++0x03 hide.long 0x00 "RBDR15,RX Buffer Data Register" endif else group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register" group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register" group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register" group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register" group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register" group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register" group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register" group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register" group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register" group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register" group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register" group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register" group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register" group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register" group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register" group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register" group.long 0x240++0x03 line.long 0x00 "RBDR16,RX Buffer Data Register" group.long 0x244++0x03 line.long 0x00 "RBDR17,RX Buffer Data Register" group.long 0x248++0x03 line.long 0x00 "RBDR18,RX Buffer Data Register" group.long 0x24C++0x03 line.long 0x00 "RBDR19,RX Buffer Data Register" group.long 0x250++0x03 line.long 0x00 "RBDR20,RX Buffer Data Register" group.long 0x254++0x03 line.long 0x00 "RBDR21,RX Buffer Data Register" group.long 0x258++0x03 line.long 0x00 "RBDR22,RX Buffer Data Register" group.long 0x25C++0x03 line.long 0x00 "RBDR23,RX Buffer Data Register" group.long 0x260++0x03 line.long 0x00 "RBDR24,RX Buffer Data Register" group.long 0x264++0x03 line.long 0x00 "RBDR25,RX Buffer Data Register" group.long 0x268++0x03 line.long 0x00 "RBDR26,RX Buffer Data Register" group.long 0x26C++0x03 line.long 0x00 "RBDR27,RX Buffer Data Register" group.long 0x270++0x03 line.long 0x00 "RBDR28,RX Buffer Data Register" group.long 0x274++0x03 line.long 0x00 "RBDR29,RX Buffer Data Register" group.long 0x278++0x03 line.long 0x00 "RBDR30,RX Buffer Data Register" group.long 0x27C++0x03 line.long 0x00 "RBDR31,RX Buffer Data Register" endif group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "No effect,Unlock" bitfld.long 0x04 0. " LOCK ,LUT lock" "No effect,Lock" width 7. tree "Look-up Tables" group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,8" else bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4,?..." endif hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,8" else bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4,?..." endif hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" tree.end width 0x0B tree.end tree.end tree.open "uSDHC (Ultra Secured Digital Host Controller)" tree "uSDHC_1" base ad:0x30B40000 width 22. if ((((per.l(ad:0x30B40000+0x24))&0x04)==0x04)||(((per.l(ad:0x30B40000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif endif group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" if (((per.l(ad:0x30B40000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7] line 7 signal level" "Low,High" bitfld.long 0x00 30. " [6] ,DAT[6] line 6 signal level" "Low,High" bitfld.long 0x00 29. " [5] ,DAT[5] line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,DAT[4] line 4 signal level" "Low,High" bitfld.long 0x00 27. " [3] ,DAT[4] line 3 signal level" "Low,High" bitfld.long 0x00 26. " [2] ,DAT[2] line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,DAT[1] line 1 signal level" "Low,High" bitfld.long 0x00 24. " [0] ,DAT[0] line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x30B40000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "0,1" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-Tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-Tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x30B40000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" newline rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" newline bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" newline line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" newline bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" newline bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" newline bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" newline wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x30B40000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x30B40000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" textfld " " hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" newline bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" endif newline bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" endif newline bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" newline bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" endif newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" endif line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" else bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" endif line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x08 14. " BUS_RST ,BUS reset" "No reset,Reset" bitfld.long 0x08 13. " PART_DLL_DEBUG ,Debug for part dll" "No debug,Debug" bitfld.long 0x08 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" newline endif bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start dealy cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree "uSDHC_2" base ad:0x30B50000 width 22. if ((((per.l(ad:0x30B50000+0x24))&0x04)==0x04)||(((per.l(ad:0x30B50000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif endif group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" if (((per.l(ad:0x30B50000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7] line 7 signal level" "Low,High" bitfld.long 0x00 30. " [6] ,DAT[6] line 6 signal level" "Low,High" bitfld.long 0x00 29. " [5] ,DAT[5] line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,DAT[4] line 4 signal level" "Low,High" bitfld.long 0x00 27. " [3] ,DAT[4] line 3 signal level" "Low,High" bitfld.long 0x00 26. " [2] ,DAT[2] line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,DAT[1] line 1 signal level" "Low,High" bitfld.long 0x00 24. " [0] ,DAT[0] line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x30B50000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "0,1" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-Tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-Tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x30B50000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" newline rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" newline bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" newline line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" newline bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" newline bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" newline bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" newline wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x30B50000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x30B50000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" textfld " " hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" newline bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" endif newline bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" endif newline bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" newline bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" endif newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" endif line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" else bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" endif line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x08 14. " BUS_RST ,BUS reset" "No reset,Reset" bitfld.long 0x08 13. " PART_DLL_DEBUG ,Debug for part dll" "No debug,Debug" bitfld.long 0x08 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" newline endif bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start dealy cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree "uSDHC_3" base ad:0x30B60000 width 22. if ((((per.l(ad:0x30B60000+0x24))&0x04)==0x04)||(((per.l(ad:0x30B60000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif endif group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" if (((per.l(ad:0x30B60000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7] line 7 signal level" "Low,High" bitfld.long 0x00 30. " [6] ,DAT[6] line 6 signal level" "Low,High" bitfld.long 0x00 29. " [5] ,DAT[5] line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,DAT[4] line 4 signal level" "Low,High" bitfld.long 0x00 27. " [3] ,DAT[4] line 3 signal level" "Low,High" bitfld.long 0x00 26. " [2] ,DAT[2] line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,DAT[1] line 1 signal level" "Low,High" bitfld.long 0x00 24. " [0] ,DAT[0] line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x30B60000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "0,1" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-Tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-Tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x30B60000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" newline rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" newline bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" newline line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" newline bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" newline bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" newline bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" newline wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x30B60000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x30B60000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" textfld " " hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" newline bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" endif newline bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" endif newline bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" newline bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" endif newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" sif (!cpuis("IMX7ULP-CA7")&&!cpuis("IMX7ULP-CM4")) newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" endif line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" else bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" endif line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" sif (cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) bitfld.long 0x08 14. " BUS_RST ,BUS reset" "No reset,Reset" bitfld.long 0x08 13. " PART_DLL_DEBUG ,Debug for part dll" "No debug,Debug" bitfld.long 0x08 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" newline endif bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start dealy cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree.end tree.open "ENET (Ethernet MAC)" tree "ENET_1" base ad:0x30BE0000 width 10. endian.be group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA ring 1 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA ring 0 flush indication" "Not flushed,Flushed" sif cpuis("IMX8DV*") eventfld.long 0x00 10. " PARSERR ,Receive parser error" "No error,Error" textline " " eventfld.long 0x00 9. " PARSRF ,Receive frame rejected" "Not rejected,Rejected" eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt, class 2" "No interrupt,Interrupt" else eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt, class 2" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt, class 1" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt, class 1" "No interrupt,Interrupt" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" sif cpuis("IMX8DV*") eventfld.long 0x04 10. " PARSERR ,Receive parser error interrupt mask" "Masked,Not masked" textline " " eventfld.long 0x04 9. " PARSRF ,Receive frame rejected interrupt mask" "Masked,Not masked" bitfld.long 0x04 7. " TXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" else bitfld.long 0x04 7. " TXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" endif textline " " bitfld.long 0x04 6. " TXB2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 3. " TXF1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" textline " " bitfld.long 0x04 2. " TXB1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 20. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 21. " VLANUSE2ND ,VLAN use second tag" "First tag,Second tag" bitfld.long 0x00 22. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 23. " DBSWP ,Descriptor byte swapping enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPEED ,Selects between 10/100-mbit/s and 1000-mbit/s modes of operation" "10/100 Mbps mode,1000 Mbps mode" bitfld.long 0x00 27. " EN1588 ,Enables enhanced functionality of the MAC" "Disabled,Enabled" bitfld.long 0x00 28. " SLEEP ,Sleep mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 30. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 31. " RESET ,Ethernet MAC reset" "No effect,Reset" group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Extended MDIO,Standard MDIO,?..." bitfld.long 0x00 28.--29. " OP ,Determines the frame operation" "Address write,Write operation,Read inc. Operation,Read operation" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "Busy,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Yes,No" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Not removed,Removed" bitfld.long 0x00 9. " RMII_10T ,Enables 10-mbps mode of the RMII or RGMII" "100 mbps,10 mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" if (((per.l.be(ad:0x30BE0000+0x24))&0x02)==0x00) group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,Not appended" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,Not appended" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" rbitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" endif group.long 0xE4++0x0B line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 0x01 " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" group.long 0xF0++0x03 line.long 0x00 "TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF4++0x03 line.long 0x00 "TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF8++0x03 line.long 0x00 "TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x104++0x03 line.long 0x00 "RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x108++0x03 line.long 0x00 "RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" textline " " group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of transmit buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register - Ring 1" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x0C 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of receive buffer descriptor queue 2" line.long 0x10 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x10 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of transmit buffer descriptor queue 2" line.long 0x14 "MRBR2,Maximum Receive Buffer Size Register - Ring 2" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue 0" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue 0" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register - Ring 0" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX status FIFO section empty threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Not removed,Removed" group.long 0x1C8++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register For Class N" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1CC++0x03 line.long 0x00 "RCMR2,Receive Classification Match Register For Class N" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1DC++0x03 line.long 0x00 "DMA2CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x13 line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" line.long 0x08 "RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x08 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x0C "TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x0C 24. " TDAR ,Transmit descriptor active" "Not active,Active" line.long 0x10 "QOS,QOS Scheme" bitfld.long 0x10 5. " RX_FLUSH2 ,RX flush ring 2" "Disabled,Enabled" bitfld.long 0x10 4. " RX_FLUSH1 ,RX flush ring 1" "Disabled,Enabled" bitfld.long 0x10 3. " RX_FLUSH0 ,RX flush ring 0" "Disabled,Enabled" bitfld.long 0x10 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based,Round-robin,?..." group.long 0x400++0x17 line.long 0x00 "ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No effect,Reset" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" line.long 0x04 "ATVR,Timer Value Register" line.long 0x08 "ATOFF,Timer Offset Register" line.long 0x0C "ATPER,Timer Period Register" textline " " line.long 0x10 "ATCOR,Timer Correction Register" hexmask.long 0x10 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x14 "ATINC,Time-stamping Clock Period Register" hexmask.long.byte 0x14 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" if (((per.l.be(ad:0x30BE0000+0x04))&0x10000)==0x10000) rgroup.long 0x418++0x03 line.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" else hgroup.long 0x418++0x03 hide.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" endif sif cpuis("IMX8DV*") textline " " group.long 0x580++0x17 line.long 0x00 "MDATA,Pattern Match Data Register" line.long 0x04 "MMASK,Match Entry Mask Register" line.long 0x08 "MCONFIG,Match Entry Rules Configuration Register" bitfld.long 0x08 31. " AF ,Accept frame" "Not accepted,Accepted" bitfld.long 0x08 30. " RF ,Reject frame" "Not rejected,Rejected" bitfld.long 0x08 29. " IM ,Invert match" "Not inverted,Inverted" hexmask.long.byte 0x08 16.--23. 1. " OK_INDEX ,Queue index" textline " " bitfld.long 0x08 2.--7. " FRMOFF ,Frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MENTRYRW,Match Entry Read/Write Command Register" bitfld.long 0x0C 9. " RD ,Entry read command" "Not read,Read" bitfld.long 0x0C 8. " WR ,Entry write command" "Not written,Written" hexmask.long.byte 0x0C 0.--7. 0x01 " ENTRYADD ,Entry address" line.long 0x10 "RXPCTL,Receive Parser Control Register" bitfld.long 0x10 24. " ACPTEERR ,Accept end error" "Not accepted,Accepted" hexmask.long.byte 0x10 16.--23. 1. " ENDERRQ ,End error queue" hexmask.long.byte 0x10 8.--15. 1. " MAXINDEX ,Maximum index" bitfld.long 0x10 4. " PRSRSCLR ,Clear parser statistics counter" "Not cleared,Cleared" textline " " bitfld.long 0x10 1. " INVBYTORD ,Inverse frame byte order" "Not inverse,Inverse" bitfld.long 0x10 0. " ENPARSER ,Enable receive parser" "Disabled,Enabled" line.long 0x14 "MXFRMOFF,Maximum Frame Offset Register" bitfld.long 0x14 0.--5. " MXFRMOFF ,Max frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.long 0x598++0x03 hide.long 0x00 "RXPARST,Receive Parser Status Register" in rgroup.long 0x5A0++0x1B line.long 0x00 "PARSDSCD,Parser Discard Count Register" line.long 0x04 "PRSACPT0,Parser Accept Count 0 Register" line.long 0x08 "PRSRJCT0,Parser Reject Count 0 Register" line.long 0x0C "PRSACPT1,Parser Accept Count 1 Register" line.long 0x10 "PRSRJCT1,Parser Reject Count 1 Register" line.long 0x14 "PRSACPT2,Parser Accept Count 2 Register" line.long 0x18 "PRSRJCT2,Parser Reject Count 2 Register" textline " " endif group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register" width 20. tree "Statistic Event Counters" rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,Tx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with crc/align error" line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL Bytes And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "RMON_T_P64,Tx 64-byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "RMON_T_P65TO127,Tx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "RMON_T_P128TO255,Tx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "RMON_T_P256TO511,Tx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "RMON_T_P512TO1023,Tx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted With Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted With Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted After Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted With Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted With Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted With Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted With Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "IEEE_T_SQE,IEEE_T_SQE" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "IEEE_T_OCTETS_OK,Octet Count For Frames Transmitted W/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "RMON_R_CRC_ALIGN,Rx Packets With Crc/align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "RMON_R_UNDERSIZE,Rx Packets With Less Than 64 Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,Rx 64-byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "RMON_R_P65TO127,Rx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "RMON_R_P128TO255,Rx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "RMON_R_P256TO511,Rx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "RMON_R_P512TO1023,Rx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "IEEE_R_DROP,Frames Not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received With CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received With Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count For Frames Received Without Error Statistic Register" tree.end endian.le width 0x0B tree.end sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) tree "ENET_2" base ad:0x30BF0000 width 10. endian.be group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA ring 1 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA ring 0 flush indication" "Not flushed,Flushed" sif cpuis("IMX8DV*") eventfld.long 0x00 10. " PARSERR ,Receive parser error" "No error,Error" textline " " eventfld.long 0x00 9. " PARSRF ,Receive frame rejected" "Not rejected,Rejected" eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt, class 2" "No interrupt,Interrupt" else eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt, class 2" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt, class 2" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt, class 1" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt, class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt, class 1" "No interrupt,Interrupt" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" sif cpuis("IMX8DV*") eventfld.long 0x04 10. " PARSERR ,Receive parser error interrupt mask" "Masked,Not masked" textline " " eventfld.long 0x04 9. " PARSRF ,Receive frame rejected interrupt mask" "Masked,Not masked" bitfld.long 0x04 7. " TXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" else bitfld.long 0x04 7. " TXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" endif textline " " bitfld.long 0x04 6. " TXB2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 3. " TXF1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" textline " " bitfld.long 0x04 2. " TXB1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Determines whether an interrupt condition can generate an interrupt" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 20. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 21. " VLANUSE2ND ,VLAN use second tag" "First tag,Second tag" bitfld.long 0x00 22. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 23. " DBSWP ,Descriptor byte swapping enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPEED ,Selects between 10/100-mbit/s and 1000-mbit/s modes of operation" "10/100 Mbps mode,1000 Mbps mode" bitfld.long 0x00 27. " EN1588 ,Enables enhanced functionality of the MAC" "Disabled,Enabled" bitfld.long 0x00 28. " SLEEP ,Sleep mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 30. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 31. " RESET ,Ethernet MAC reset" "No effect,Reset" group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Extended MDIO,Standard MDIO,?..." bitfld.long 0x00 28.--29. " OP ,Determines the frame operation" "Address write,Write operation,Read inc. Operation,Read operation" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "Busy,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Yes,No" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Not removed,Removed" bitfld.long 0x00 9. " RMII_10T ,Enables 10-mbps mode of the RMII or RGMII" "100 mbps,10 mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" if (((per.l.be(ad:0x30BF0000+0x24))&0x02)==0x00) group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,Not appended" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,Not appended" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" rbitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" endif group.long 0xE4++0x0B line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 0x01 " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" group.long 0xF0++0x03 line.long 0x00 "TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF4++0x03 line.long 0x00 "TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF8++0x03 line.long 0x00 "TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x104++0x03 line.long 0x00 "RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x108++0x03 line.long 0x00 "RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII TX,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" textline " " group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of transmit buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register - Ring 1" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x0C 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of receive buffer descriptor queue 2" line.long 0x10 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x10 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of transmit buffer descriptor queue 2" line.long 0x14 "MRBR2,Maximum Receive Buffer Size Register - Ring 2" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue 0" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue 0" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register - Ring 0" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX status FIFO section empty threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Not removed,Removed" group.long 0x1C8++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register For Class N" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1CC++0x03 line.long 0x00 "RCMR2,Receive Classification Match Register For Class N" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1DC++0x03 line.long 0x00 "DMA2CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x13 line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" line.long 0x08 "RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x08 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x0C "TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x0C 24. " TDAR ,Transmit descriptor active" "Not active,Active" line.long 0x10 "QOS,QOS Scheme" bitfld.long 0x10 5. " RX_FLUSH2 ,RX flush ring 2" "Disabled,Enabled" bitfld.long 0x10 4. " RX_FLUSH1 ,RX flush ring 1" "Disabled,Enabled" bitfld.long 0x10 3. " RX_FLUSH0 ,RX flush ring 0" "Disabled,Enabled" bitfld.long 0x10 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based,Round-robin,?..." group.long 0x400++0x17 line.long 0x00 "ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No effect,Reset" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" line.long 0x04 "ATVR,Timer Value Register" line.long 0x08 "ATOFF,Timer Offset Register" line.long 0x0C "ATPER,Timer Period Register" textline " " line.long 0x10 "ATCOR,Timer Correction Register" hexmask.long 0x10 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x14 "ATINC,Time-stamping Clock Period Register" hexmask.long.byte 0x14 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" if (((per.l.be(ad:0x30BF0000+0x04))&0x10000)==0x10000) rgroup.long 0x418++0x03 line.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" else hgroup.long 0x418++0x03 hide.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" endif sif cpuis("IMX8DV*") textline " " group.long 0x580++0x17 line.long 0x00 "MDATA,Pattern Match Data Register" line.long 0x04 "MMASK,Match Entry Mask Register" line.long 0x08 "MCONFIG,Match Entry Rules Configuration Register" bitfld.long 0x08 31. " AF ,Accept frame" "Not accepted,Accepted" bitfld.long 0x08 30. " RF ,Reject frame" "Not rejected,Rejected" bitfld.long 0x08 29. " IM ,Invert match" "Not inverted,Inverted" hexmask.long.byte 0x08 16.--23. 1. " OK_INDEX ,Queue index" textline " " bitfld.long 0x08 2.--7. " FRMOFF ,Frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MENTRYRW,Match Entry Read/Write Command Register" bitfld.long 0x0C 9. " RD ,Entry read command" "Not read,Read" bitfld.long 0x0C 8. " WR ,Entry write command" "Not written,Written" hexmask.long.byte 0x0C 0.--7. 0x01 " ENTRYADD ,Entry address" line.long 0x10 "RXPCTL,Receive Parser Control Register" bitfld.long 0x10 24. " ACPTEERR ,Accept end error" "Not accepted,Accepted" hexmask.long.byte 0x10 16.--23. 1. " ENDERRQ ,End error queue" hexmask.long.byte 0x10 8.--15. 1. " MAXINDEX ,Maximum index" bitfld.long 0x10 4. " PRSRSCLR ,Clear parser statistics counter" "Not cleared,Cleared" textline " " bitfld.long 0x10 1. " INVBYTORD ,Inverse frame byte order" "Not inverse,Inverse" bitfld.long 0x10 0. " ENPARSER ,Enable receive parser" "Disabled,Enabled" line.long 0x14 "MXFRMOFF,Maximum Frame Offset Register" bitfld.long 0x14 0.--5. " MXFRMOFF ,Max frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.long 0x598++0x03 hide.long 0x00 "RXPARST,Receive Parser Status Register" in rgroup.long 0x5A0++0x1B line.long 0x00 "PARSDSCD,Parser Discard Count Register" line.long 0x04 "PRSACPT0,Parser Accept Count 0 Register" line.long 0x08 "PRSRJCT0,Parser Reject Count 0 Register" line.long 0x0C "PRSACPT1,Parser Accept Count 1 Register" line.long 0x10 "PRSRJCT1,Parser Reject Count 1 Register" line.long 0x14 "PRSACPT2,Parser Accept Count 2 Register" line.long 0x18 "PRSRJCT2,Parser Reject Count 2 Register" textline " " endif group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register" eventfld.long 0x00 7. " TF ,Sets when input capture or output compare occurs" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input/Rising,Input/Falling,Input/Both,Output/Software,Output/Toggle,Output/Clear,Output/Set,,Output/Compare,Output/Clear,Output/Compare,,,Output/Compare pulse low,Output/Compare pulse high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register" width 20. tree "Statistic Event Counters" rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,Tx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with crc/align error" line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL Bytes And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "RMON_T_P64,Tx 64-byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "RMON_T_P65TO127,Tx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "RMON_T_P128TO255,Tx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "RMON_T_P256TO511,Tx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "RMON_T_P512TO1023,Tx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted With Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted With Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted After Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted With Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted With Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted With Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted With Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "IEEE_T_SQE,IEEE_T_SQE" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "IEEE_T_OCTETS_OK,Octet Count For Frames Transmitted W/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "RMON_R_CRC_ALIGN,Rx Packets With Crc/align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "RMON_R_UNDERSIZE,Rx Packets With Less Than 64 Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,Rx 64-byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "RMON_R_P65TO127,Rx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "RMON_R_P128TO255,Rx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "RMON_R_P256TO511,Rx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "RMON_R_P512TO1023,Rx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "IEEE_R_DROP,Frames Not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received With CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received With Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count For Frames Received Without Error Statistic Register" tree.end endian.le width 0x0B tree.end endif tree.end tree.open "SIM (Subscriber Identification Module)" tree "SIM_1" base ad:0x30B90000 width 15. group.long 0x00++0x0F line.long 0x00 "PORT1_CNTL,Port1 Control Register" bitfld.long 0x00 7. " SFPD1 ,Auto power down port1" "No effect,Start" bitfld.long 0x00 6. " VOLT3_1 ,External one wire interface for SIM card port1" "RCV/XMT,XMT" bitfld.long 0x00 5. " SCSP1 ,SIM card clock stop polarity port1" "Low,High" bitfld.long 0x00 4. " SCEN1 ,SIM card clock enable port 1" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SRST1 ,SIM card reset" "No reset,Reset" bitfld.long 0x00 2. " STEN1 ,SIM card transmit enable port 1" "Disabled,Enabled" bitfld.long 0x00 1. " SVEN1 ,SIM card VCC enable port 1" "Disabled,Enabled" bitfld.long 0x00 0. " SAPD1 ,SIM card auto power down port 1" "Disabled,Enabled" line.long 0x04 "SETUP,Setup Register" bitfld.long 0x04 1. " SPS ,SIM card port select" "Port 0,Port 1" bitfld.long 0x04 0. " AMODE ,Alternate SIM card mode enable" "Disabled,Enabled" line.long 0x08 "PORT1_DETECT,Port1 Detect Register" bitfld.long 0x08 3. " SPDS1 ,SIM presence detect select port 1" "Falling edge,Rising edge" bitfld.long 0x08 2. " SPDP1 ,SIMPD1 input pin status" "Low,High" eventfld.long 0x08 1. " SDI1 ,SIM detect interrupt flag port 1" "No interrupt,Interrupt" bitfld.long 0x08 0. " SDIM1 ,SIM detect interrupt mask port 1" "Not masked,Masked" line.long 0x0C "XMT_BUF,Port1 Transmit Buffer Register" hexmask.long.byte 0x0C 0.--7. 1. " XMT ,Transmit buffer" hgroup.long 0x10++0x03 hide.long 0x00 "RCV_BUF,Port1 Receive Buffer Register" in group.long 0x14++0x1F line.long 0x00 "PORT0_CNTL,Port0 Control Register" bitfld.long 0x00 7. " SFPD0 ,Auto power down port0" "No effect,Start" bitfld.long 0x00 6. " VOLT3_0 ,External one wire interface for SIM card port0" "RCV/XMT,XMT" bitfld.long 0x00 5. " SCSP0 ,SIM card clock stop polarity port0" "Low,High" bitfld.long 0x00 4. " SCEN0 ,SIM card clock enable port 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SRST0 ,SIM card reset" "No reset,Reset" bitfld.long 0x00 2. " STEN0 ,SIM card transmit enable port 0" "Disabled,Enabled" bitfld.long 0x00 1. " SVEN0 ,SIM card VCC enable port 0" "Disabled,Enabled" bitfld.long 0x00 0. " SAPD0 ,SIM card auto power down port 0" "Disabled,Enabled" line.long 0x04 "CNTL,Control Register" bitfld.long 0x04 15. " BWTEN ,Block wait time enable" "Disabled,Enabled" bitfld.long 0x04 14. " XMT_CRC_LRC ,Transmit CRC or LRC" "Not transmitted,Transmitted" bitfld.long 0x04 13. " CRCEN ,CRC enable" "Disabled,Enabled" bitfld.long 0x04 12. " LRCEN ,LRC enable" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " CWTEN ,Character wait time counter enable" "Disabled,Enabled" bitfld.long 0x04 9.--10. " GPCNT_CLK_SEL ,General purpose counter clock select" "Disabled,Card,Receive,ETU" bitfld.long 0x04 6.--8. " BAUD_SEL ,SIM baud rate select" "31,32,16,8,4,2,1,DIVISOR Reg" bitfld.long 0x04 5. " SAMPLE12 ,Sets the corresponding sample rate which is the number of times a bit being received is sampled" "/8,/12" textline " " bitfld.long 0x04 3. " ONACK ,Overrun NACK enable" "Disabled,Enabled" bitfld.long 0x04 2. " ANACK ,Automatic NACK enable" "Disabled,Enabled" bitfld.long 0x04 1. " ICM ,Initial character mode" "Disabled,Enabled" line.long 0x08 "CLK_PRESCALER,Clock Prescaler Register" hexmask.long.byte 0x08 0.--7. 1. " CLK_PRESCALER ,Clock prescaler divisor register" line.long 0x0C "RCV_THRESHOLD,Receive Threshold Register" bitfld.long 0x0C 9.--12. " RTH ,Receive NACK threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--8. 1. " RDT ,Receive data threshold" line.long 0x10 "ENABLE,Enable Register" bitfld.long 0x10 7. " RXCL ,Reception data latch disable" "No,Yes" bitfld.long 0x10 6. " ESTOP_EXE ,Enforce reception early stop execution" "Without NACK,All times" bitfld.long 0x10 5. " ESTOP_EN ,Enforce reception early stop enable" "Disabled,Enabled" bitfld.long 0x10 4. " NACK_DD_EN ,NACK delay detection enable" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " TXDMA_EN ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x10 2. " RXDMA_EN ,Receiver DMA enable" "Disabled,Enabled" bitfld.long 0x10 1. " XMT_EN ,SIM transmit enable" "Disabled,Enabled" bitfld.long 0x10 0. " RCV_EN ,SIM receiver enable" "Disabled,Enabled" line.long 0x14 "XMT_STATUS,Transmit Status Register" eventfld.long 0x14 8. " GPCNT ,General purpose counter flag" "Not reached,Reached" eventfld.long 0x14 7. " TDTF ,Transmit FIFO threshold flag" "> TDT | cleared,<= TDT" eventfld.long 0x14 6. " TFO ,Transmit FIFO overfill error" "No error,Error" eventfld.long 0x14 5. " TC ,Transmit complete" "Not completed,Completed" textline " " eventfld.long 0x14 4. " ETC ,Early transmit complete" "Not completed,Completed" eventfld.long 0x14 3. " TFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x14 0. " XTE ,Transmit threshold error" "Not reached,Reached" line.long 0x18 "RCV_STATUS,Receive Status Register" eventfld.long 0x18 11. " BGT ,Block guard time error flag" "No error,Error" eventfld.long 0x18 10. " BWT ,Block wait time error flag" "No error,Error" eventfld.long 0x18 9. " RTE ,Receive NACK threshold error flag" "< RTH,= RTH" eventfld.long 0x18 8. " CWT ,Character wait time counter flag" "Not occurred,Occurred" textline " " rbitfld.long 0x18 7. " CRCOK ,Cyclic redundancy check okay flag" "Not matched,Matched" rbitfld.long 0x18 6. " LRCOK ,Linear redundancy check okay flag" "Not matched,Matched" eventfld.long 0x18 5. " RDRF ,Receive data register full" "< RDT,>= RDT" rbitfld.long 0x18 4. " RFD ,Receive FIFO has unread data" "No,Yes" textline " " eventfld.long 0x18 1. " RFE ,Receive FIFO empty" "Not empty,Empty" eventfld.long 0x18 0. " OEF ,Overrun error flag" "No overrun,Overrun" line.long 0x1C "INT_MASK,Interrupt Mask Register" bitfld.long 0x1C 13. " RFEM ,Receive FIFO empty interrupt mask" "Not masked,Masked" bitfld.long 0x1C 12. " BGTM ,Block guard time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 11. " BWTM ,Block wait time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 10. " RTM ,Receive NACK threshold interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 9. " CWTM ,Character wait time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 8. " GPCNTM ,General purpose counter interrupt mask" "Not masked,Masked" bitfld.long 0x1C 7. " TDTFM ,Transmit data threshold interrupt mask" "Not masked,Masked" bitfld.long 0x1C 6. " TFOM ,Transmit FIFO overfill error interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 5. " XTM ,Transmit threshold interrupt mask" "Not masked,Masked" bitfld.long 0x1C 4. " TFEIM ,Transmit FIFO empty interrupt mask" "Not masked,Masked" bitfld.long 0x1C 3. " ETCIM ,Early transmit complete interrupt mask" "Not masked,Masked" bitfld.long 0x1C 2. " OIM ,Overrun interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 1. " TCIM ,Transmit complete interrupt mask" "Not masked,Masked" bitfld.long 0x1C 0. " RIM ,Receive interrupt mask" "Not masked,Masked" group.long 0x3C++0x2F line.long 0x00 "PORT0_DETECT,Port0 Detect Register" bitfld.long 0x00 3. " SPDS0 ,SIM presence detect select port 0" "Falling edge,Rising edge" rbitfld.long 0x00 2. " SPDP0 ,SIMPD0 input pin status" "Low,High" eventfld.long 0x00 1. " SDI0 ,SIM detect interrupt flag port 0" "No interrupt,Interrupt" bitfld.long 0x00 0. " SDIM0 ,SIM detect interrupt mask port 0" "Not masked,Masked" line.long 0x04 "DATA_FORMAT,Data Format Register" bitfld.long 0x04 0. " IC ,Inverse conversion" "Not inverted,Inverted" line.long 0x08 "XMT_THRESHOLD,Transmit Threshold Register" bitfld.long 0x08 4.--7. " XTH ,Transmit NACK threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " TDT ,Transmit data threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "GUARD_CNTL,Transmit Guard Control Register" bitfld.long 0x0C 8. " RCVR11 ,Receiver use 11 ETUs" "12 ETU,11 ETU" hexmask.long.byte 0x0C 0.--7. 1. " GETU ,Transmit guard ETUs" line.long 0x10 "OD_CONFIG,Open Drain Configuration Control Register" bitfld.long 0x10 1. " OD_P1 ,Open drain control for port 1" "Push-pull,Open-drain" bitfld.long 0x10 0. " OD_P0 ,Open drain control for port 0" "Push-pull,Open-drain" line.long 0x14 "RESET_CNTL,Reset Control Register" bitfld.long 0x14 5. " STOP ,STOP" "All,Except BAUD_CLK" bitfld.long 0x14 4. " DOZE ,DOZE" "No effect,Clocks gated" bitfld.long 0x14 3. " KILL_CLOCK ,Kill SIM clock" "No,Yes" textline " " bitfld.long 0x14 2. " SOFT_RST ,Software reset" "No effect,Reset" bitfld.long 0x14 1. " FLUSH_XMT ,Flush transmitter" "No effect,Reset" bitfld.long 0x14 0. " FLUSH_RCV ,Flush receiver" "No effect,Reset" line.long 0x18 "CHAR_WAIT,Character Wait Time Register" hexmask.long.word 0x18 0.--15. 1. " CWT ,Character wait time" line.long 0x1C "GPCNT,General Purpose Counter Register" hexmask.long.word 0x1C 0.--15. 1. " GPCNT ,General purpose counter" line.long 0x20 "DIVISOR,DIVISOR Register" hexmask.long.byte 0x20 0.--7. 1. " DIVISOR ,Divisor" line.long 0x24 "BWT,Block Wait Time Register" hexmask.long.word 0x24 0.--15. 1. " BWT ,BWT register 16 LSB" line.long 0x28 "BGT,Block Guard Time Register" hexmask.long.word 0x28 0.--15. 1. " BGT ,Block wait guard time" line.long 0x2C "BWT_H,Block Wait Time Register High" hexmask.long.word 0x2C 0.--15. 1. " BWT_H ,BWT register 16 MSB" rgroup.long 0x6C++0x0F line.long 0x00 "XMT_FIFO_STAT,Transmit FIFO Status Register" bitfld.long 0x00 8.--11. " XMT_CNT ,Transmit FIFO byte number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " XMT_WPTR ,Transmit FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " XMT_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RCV_FIFO_CNT,Receive FIFO Counter Register" hexmask.long.word 0x04 0.--8. 1. " RCV_CNT ,Receive FIFO byte number" line.long 0x08 "RCV_FIFO_WPTR,Receive FIFO Write Pointer Register" hexmask.long.word 0x08 0.--8. 1. " RCV_WPTR ,Receive FIFO write pointer" line.long 0x0C "RCV_FIFO_RPTR,Receive FIFO Read Pointer Register" hexmask.long.word 0x0C 0.--8. 1. " RCV_RPTR ,Receive FIFO read pointer" width 0x0B tree.end tree "SIM_2" base ad:0x30BA0000 width 15. group.long 0x00++0x0F line.long 0x00 "PORT1_CNTL,Port1 Control Register" bitfld.long 0x00 7. " SFPD1 ,Auto power down port1" "No effect,Start" bitfld.long 0x00 6. " VOLT3_1 ,External one wire interface for SIM card port1" "RCV/XMT,XMT" bitfld.long 0x00 5. " SCSP1 ,SIM card clock stop polarity port1" "Low,High" bitfld.long 0x00 4. " SCEN1 ,SIM card clock enable port 1" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SRST1 ,SIM card reset" "No reset,Reset" bitfld.long 0x00 2. " STEN1 ,SIM card transmit enable port 1" "Disabled,Enabled" bitfld.long 0x00 1. " SVEN1 ,SIM card VCC enable port 1" "Disabled,Enabled" bitfld.long 0x00 0. " SAPD1 ,SIM card auto power down port 1" "Disabled,Enabled" line.long 0x04 "SETUP,Setup Register" bitfld.long 0x04 1. " SPS ,SIM card port select" "Port 0,Port 1" bitfld.long 0x04 0. " AMODE ,Alternate SIM card mode enable" "Disabled,Enabled" line.long 0x08 "PORT1_DETECT,Port1 Detect Register" bitfld.long 0x08 3. " SPDS1 ,SIM presence detect select port 1" "Falling edge,Rising edge" bitfld.long 0x08 2. " SPDP1 ,SIMPD1 input pin status" "Low,High" eventfld.long 0x08 1. " SDI1 ,SIM detect interrupt flag port 1" "No interrupt,Interrupt" bitfld.long 0x08 0. " SDIM1 ,SIM detect interrupt mask port 1" "Not masked,Masked" line.long 0x0C "XMT_BUF,Port1 Transmit Buffer Register" hexmask.long.byte 0x0C 0.--7. 1. " XMT ,Transmit buffer" hgroup.long 0x10++0x03 hide.long 0x00 "RCV_BUF,Port1 Receive Buffer Register" in group.long 0x14++0x1F line.long 0x00 "PORT0_CNTL,Port0 Control Register" bitfld.long 0x00 7. " SFPD0 ,Auto power down port0" "No effect,Start" bitfld.long 0x00 6. " VOLT3_0 ,External one wire interface for SIM card port0" "RCV/XMT,XMT" bitfld.long 0x00 5. " SCSP0 ,SIM card clock stop polarity port0" "Low,High" bitfld.long 0x00 4. " SCEN0 ,SIM card clock enable port 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SRST0 ,SIM card reset" "No reset,Reset" bitfld.long 0x00 2. " STEN0 ,SIM card transmit enable port 0" "Disabled,Enabled" bitfld.long 0x00 1. " SVEN0 ,SIM card VCC enable port 0" "Disabled,Enabled" bitfld.long 0x00 0. " SAPD0 ,SIM card auto power down port 0" "Disabled,Enabled" line.long 0x04 "CNTL,Control Register" bitfld.long 0x04 15. " BWTEN ,Block wait time enable" "Disabled,Enabled" bitfld.long 0x04 14. " XMT_CRC_LRC ,Transmit CRC or LRC" "Not transmitted,Transmitted" bitfld.long 0x04 13. " CRCEN ,CRC enable" "Disabled,Enabled" bitfld.long 0x04 12. " LRCEN ,LRC enable" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " CWTEN ,Character wait time counter enable" "Disabled,Enabled" bitfld.long 0x04 9.--10. " GPCNT_CLK_SEL ,General purpose counter clock select" "Disabled,Card,Receive,ETU" bitfld.long 0x04 6.--8. " BAUD_SEL ,SIM baud rate select" "31,32,16,8,4,2,1,DIVISOR Reg" bitfld.long 0x04 5. " SAMPLE12 ,Sets the corresponding sample rate which is the number of times a bit being received is sampled" "/8,/12" textline " " bitfld.long 0x04 3. " ONACK ,Overrun NACK enable" "Disabled,Enabled" bitfld.long 0x04 2. " ANACK ,Automatic NACK enable" "Disabled,Enabled" bitfld.long 0x04 1. " ICM ,Initial character mode" "Disabled,Enabled" line.long 0x08 "CLK_PRESCALER,Clock Prescaler Register" hexmask.long.byte 0x08 0.--7. 1. " CLK_PRESCALER ,Clock prescaler divisor register" line.long 0x0C "RCV_THRESHOLD,Receive Threshold Register" bitfld.long 0x0C 9.--12. " RTH ,Receive NACK threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--8. 1. " RDT ,Receive data threshold" line.long 0x10 "ENABLE,Enable Register" bitfld.long 0x10 7. " RXCL ,Reception data latch disable" "No,Yes" bitfld.long 0x10 6. " ESTOP_EXE ,Enforce reception early stop execution" "Without NACK,All times" bitfld.long 0x10 5. " ESTOP_EN ,Enforce reception early stop enable" "Disabled,Enabled" bitfld.long 0x10 4. " NACK_DD_EN ,NACK delay detection enable" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " TXDMA_EN ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x10 2. " RXDMA_EN ,Receiver DMA enable" "Disabled,Enabled" bitfld.long 0x10 1. " XMT_EN ,SIM transmit enable" "Disabled,Enabled" bitfld.long 0x10 0. " RCV_EN ,SIM receiver enable" "Disabled,Enabled" line.long 0x14 "XMT_STATUS,Transmit Status Register" eventfld.long 0x14 8. " GPCNT ,General purpose counter flag" "Not reached,Reached" eventfld.long 0x14 7. " TDTF ,Transmit FIFO threshold flag" "> TDT | cleared,<= TDT" eventfld.long 0x14 6. " TFO ,Transmit FIFO overfill error" "No error,Error" eventfld.long 0x14 5. " TC ,Transmit complete" "Not completed,Completed" textline " " eventfld.long 0x14 4. " ETC ,Early transmit complete" "Not completed,Completed" eventfld.long 0x14 3. " TFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x14 0. " XTE ,Transmit threshold error" "Not reached,Reached" line.long 0x18 "RCV_STATUS,Receive Status Register" eventfld.long 0x18 11. " BGT ,Block guard time error flag" "No error,Error" eventfld.long 0x18 10. " BWT ,Block wait time error flag" "No error,Error" eventfld.long 0x18 9. " RTE ,Receive NACK threshold error flag" "< RTH,= RTH" eventfld.long 0x18 8. " CWT ,Character wait time counter flag" "Not occurred,Occurred" textline " " rbitfld.long 0x18 7. " CRCOK ,Cyclic redundancy check okay flag" "Not matched,Matched" rbitfld.long 0x18 6. " LRCOK ,Linear redundancy check okay flag" "Not matched,Matched" eventfld.long 0x18 5. " RDRF ,Receive data register full" "< RDT,>= RDT" rbitfld.long 0x18 4. " RFD ,Receive FIFO has unread data" "No,Yes" textline " " eventfld.long 0x18 1. " RFE ,Receive FIFO empty" "Not empty,Empty" eventfld.long 0x18 0. " OEF ,Overrun error flag" "No overrun,Overrun" line.long 0x1C "INT_MASK,Interrupt Mask Register" bitfld.long 0x1C 13. " RFEM ,Receive FIFO empty interrupt mask" "Not masked,Masked" bitfld.long 0x1C 12. " BGTM ,Block guard time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 11. " BWTM ,Block wait time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 10. " RTM ,Receive NACK threshold interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 9. " CWTM ,Character wait time interrupt mask" "Not masked,Masked" bitfld.long 0x1C 8. " GPCNTM ,General purpose counter interrupt mask" "Not masked,Masked" bitfld.long 0x1C 7. " TDTFM ,Transmit data threshold interrupt mask" "Not masked,Masked" bitfld.long 0x1C 6. " TFOM ,Transmit FIFO overfill error interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 5. " XTM ,Transmit threshold interrupt mask" "Not masked,Masked" bitfld.long 0x1C 4. " TFEIM ,Transmit FIFO empty interrupt mask" "Not masked,Masked" bitfld.long 0x1C 3. " ETCIM ,Early transmit complete interrupt mask" "Not masked,Masked" bitfld.long 0x1C 2. " OIM ,Overrun interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x1C 1. " TCIM ,Transmit complete interrupt mask" "Not masked,Masked" bitfld.long 0x1C 0. " RIM ,Receive interrupt mask" "Not masked,Masked" group.long 0x3C++0x2F line.long 0x00 "PORT0_DETECT,Port0 Detect Register" bitfld.long 0x00 3. " SPDS0 ,SIM presence detect select port 0" "Falling edge,Rising edge" rbitfld.long 0x00 2. " SPDP0 ,SIMPD0 input pin status" "Low,High" eventfld.long 0x00 1. " SDI0 ,SIM detect interrupt flag port 0" "No interrupt,Interrupt" bitfld.long 0x00 0. " SDIM0 ,SIM detect interrupt mask port 0" "Not masked,Masked" line.long 0x04 "DATA_FORMAT,Data Format Register" bitfld.long 0x04 0. " IC ,Inverse conversion" "Not inverted,Inverted" line.long 0x08 "XMT_THRESHOLD,Transmit Threshold Register" bitfld.long 0x08 4.--7. " XTH ,Transmit NACK threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " TDT ,Transmit data threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "GUARD_CNTL,Transmit Guard Control Register" bitfld.long 0x0C 8. " RCVR11 ,Receiver use 11 ETUs" "12 ETU,11 ETU" hexmask.long.byte 0x0C 0.--7. 1. " GETU ,Transmit guard ETUs" line.long 0x10 "OD_CONFIG,Open Drain Configuration Control Register" bitfld.long 0x10 1. " OD_P1 ,Open drain control for port 1" "Push-pull,Open-drain" bitfld.long 0x10 0. " OD_P0 ,Open drain control for port 0" "Push-pull,Open-drain" line.long 0x14 "RESET_CNTL,Reset Control Register" bitfld.long 0x14 5. " STOP ,STOP" "All,Except BAUD_CLK" bitfld.long 0x14 4. " DOZE ,DOZE" "No effect,Clocks gated" bitfld.long 0x14 3. " KILL_CLOCK ,Kill SIM clock" "No,Yes" textline " " bitfld.long 0x14 2. " SOFT_RST ,Software reset" "No effect,Reset" bitfld.long 0x14 1. " FLUSH_XMT ,Flush transmitter" "No effect,Reset" bitfld.long 0x14 0. " FLUSH_RCV ,Flush receiver" "No effect,Reset" line.long 0x18 "CHAR_WAIT,Character Wait Time Register" hexmask.long.word 0x18 0.--15. 1. " CWT ,Character wait time" line.long 0x1C "GPCNT,General Purpose Counter Register" hexmask.long.word 0x1C 0.--15. 1. " GPCNT ,General purpose counter" line.long 0x20 "DIVISOR,DIVISOR Register" hexmask.long.byte 0x20 0.--7. 1. " DIVISOR ,Divisor" line.long 0x24 "BWT,Block Wait Time Register" hexmask.long.word 0x24 0.--15. 1. " BWT ,BWT register 16 LSB" line.long 0x28 "BGT,Block Guard Time Register" hexmask.long.word 0x28 0.--15. 1. " BGT ,Block wait guard time" line.long 0x2C "BWT_H,Block Wait Time Register High" hexmask.long.word 0x2C 0.--15. 1. " BWT_H ,BWT register 16 MSB" rgroup.long 0x6C++0x0F line.long 0x00 "XMT_FIFO_STAT,Transmit FIFO Status Register" bitfld.long 0x00 8.--11. " XMT_CNT ,Transmit FIFO byte number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " XMT_WPTR ,Transmit FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " XMT_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RCV_FIFO_CNT,Receive FIFO Counter Register" hexmask.long.word 0x04 0.--8. 1. " RCV_CNT ,Receive FIFO byte number" line.long 0x08 "RCV_FIFO_WPTR,Receive FIFO Write Pointer Register" hexmask.long.word 0x08 0.--8. 1. " RCV_WPTR ,Receive FIFO write pointer" line.long 0x0C "RCV_FIFO_RPTR,Receive FIFO Read Pointer Register" hexmask.long.word 0x0C 0.--8. 1. " RCV_RPTR ,Receive FIFO read pointer" width 0x0B tree.end tree.end sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") tree "PCIe (PCI Express Controller)" base ad:0x33800000 width 45. if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,Device ID And Vendor ID Register" hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID ,Device ID" hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Vendor ID" else rgroup.long 0x00++0x03 line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,Device ID And Vendor ID Register" hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID ,Device ID" hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Vendor ID" endif group.long 0x04++0x03 line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Status And Command Register" eventfld.long 0x00 31. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SIGNALED_SYS_ERROR ,Signaled system error" "No error,Error" newline eventfld.long 0x00 29. " RCVD_MASTER_ABORT ,Received master abort" "No abort,Abort" eventfld.long 0x00 28. " RCVD_TARGET_ABORT ,Received target abort" "No abort,Abort" newline eventfld.long 0x00 27. " SIGNALED_TARGET_ABORT ,Signaled target abort" "No abort,Abort" rbitfld.long 0x00 25.--26. " DEV_SEL_TIMING ,Device select timing" "0,?..." newline eventfld.long 0x00 24. " MASTER_DPE ,Master data parity error" "No error,Error" rbitfld.long 0x00 23. " FAST_B2B_CAP ,Fast back-to-back transactions capable" "0,?..." newline rbitfld.long 0x00 21. " FAST_66MHZ_CAP ,66 MHz capable" "0,?..." rbitfld.long 0x00 20. " CAP_LIST ,Capabilities list" ",1" newline rbitfld.long 0x00 19. " INT_STATUS ,Interrupt status" "Disabled,Enabled" bitfld.long 0x00 10. " INT_EN ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SERREN ,Reporting of non-fatal and fatal errors detected enable" "Disabled,Enabled" rbitfld.long 0x00 7. " IDSEL ,IDSEL stepping/wait cycle control" "0,1" newline bitfld.long 0x00 6. " PERREN ,Parity error enable" "Disabled,Enabled" rbitfld.long 0x00 5. " VGAPS ,VGA palette snoop" "Disabled,Enabled" newline rbitfld.long 0x00 4. " MWI_EN ,Memory write and invalidate enable" "Disabled,Enabled" rbitfld.long 0x00 3. " SCO ,Special cycle enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " BME ,Bus master enable" "Disabled,Enabled" bitfld.long 0x00 1. " MSE ,Memory space enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IO_EN ,I/O space enable" "Disabled,Enabled" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code And Revision ID Register" hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE ,Base class-memory controller" hexmask.long.byte 0x00 16.--23. 1. " SUBCLASS_CODE ,Sub class-other memory controller" newline hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTFERFACE ,Register level programming interface" hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,Device revision number" else rgroup.long 0x08++0x03 line.long 0x00 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code And Revision ID Register" hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE ,Base class-memory controller" hexmask.long.byte 0x00 16.--23. 1. " SUBCLASS_CODE ,Sub class-other memory controller" newline hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTFERFACE ,Register level programming interface" hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,Device revision number" endif group.long 0x0C++0x03 line.long 0x00 "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST And Header Type And Latency Timer And Cache Line Size Register" hexmask.long.byte 0x00 24.--31. 1. " BIST ,Built-in self test" rbitfld.long 0x00 23. " MULTI_FUNC ,Multi-function device" "0,1" newline hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE ,Header layout" hexmask.long.byte 0x00 8.--15. 1. " LATENCY_MASTER_TIMER ,Latency master timer" newline hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE ,Device cache line size" group.long 0x18++0x03 line.long 0x00 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer And Subordinate Bus Number And Secondary Bus Number And Primary Bus Number Register" hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER ,Secondary latency timer" hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS ,Subordinate bus number" newline hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS ,Secondary bus number" hexmask.long.byte 0x00 0.--7. 1. " PRIM_BUS ,Primary bus number" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x1C++0x03 line.long 0x00 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status And I/O Limit And Base Register" eventfld.long 0x00 31. " SEC_STAT_DPE ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SEC_STAT_RCVD_SYS_ERR ,Received system error" "No error,Error" newline eventfld.long 0x00 29. " SEC_STAT_RCVD_MSTR_ABRT ,Received master abort" "Not received,Received" eventfld.long 0x00 28. " SEC_STAT_RCVD_TRGT_ABRT ,Received target abort" "Not received,Received" newline eventfld.long 0x00 27. " SEC_STAT_SIG_TRGT_ABRT ,Signaled target abort" "No error,Error" eventfld.long 0x00 24. " SEC_STAT_MDPE ,Master data parity error" "No error,Error" newline bitfld.long 0x00 12.--15. " IO_LIMIT ,I/O limit address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " IO_DECODE_BIT8 ,I/O addressing encode" "16 bit supported,32 bit supported" newline bitfld.long 0x00 4.--7. " IO_BASE ,I/O base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " IO_DECODE ,I/O decode" "16 bit supported,32 bit supported" else group.long 0x1C++0x03 line.long 0x00 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status And I/O Limit And Base Register" eventfld.long 0x00 31. " SEC_STAT_DPE ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SEC_STAT_RCVD_SYS_ERR ,Received system error" "No error,Error" newline eventfld.long 0x00 29. " SEC_STAT_RCVD_MSTR_ABRT ,Received master abort" "Not received,Received" eventfld.long 0x00 28. " SEC_STAT_RCVD_TRGT_ABRT ,Received target abort" "Not received,Received" newline eventfld.long 0x00 27. " SEC_STAT_SIG_TRGT_ABRT ,Signaled target abort" "No error,Error" eventfld.long 0x00 24. " SEC_STAT_MDPE ,Master data parity error" "No error,Error" newline bitfld.long 0x00 12.--15. " IO_LIMIT ,I/O limit address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " IO_DECODE_BIT8 ,I/O addressing encode" "16 bit supported,32 bit supported" newline bitfld.long 0x00 4.--7. " IO_BASE ,I/O base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0. " IO_DECODE ,I/O decode" "16 bit supported,32 bit supported" endif group.long 0x20++0x03 line.long 0x00 "MEM_LIMIT_MEM_BASE_REG,Memory Limit And Base Register" hexmask.long.word 0x00 20.--31. 0x10 " MEM_LIMIT ,Memory limit address" hexmask.long.word 0x00 4.--15. 0x10 " MEM_BASE ,Memory base address" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit And Base Register" hexmask.long.word 0x00 20.--31. 0x10 " PREF_MEM_LIMIT ,Prefetchable memory limit address" rbitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE ,Prefetchable memory limit decode" "32 bit supported,64 bit supported" newline hexmask.long.word 0x00 4.--15. 0x10 " PREF_MEM_BASE ,Prefetchable memory base address" bitfld.long 0x00 0. " PREF_MEM_DECODE ,Prefetchable memory base decode" "32 bit supported,64 bit supported" else group.long 0x24++0x03 line.long 0x00 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit And Base Register" hexmask.long.word 0x00 20.--31. 0x10 " PREF_MEM_LIMIT ,Prefetchable memory limit address" rbitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE ,Prefetchable memory limit decode" "32 bit supported,64 bit supported" newline hexmask.long.word 0x00 4.--15. 0x10 " PREF_MEM_BASE ,Prefetchable memory base address" rbitfld.long 0x00 0. " PREF_MEM_DECODE ,Prefetchable memory base decode" "32 bit supported,64 bit supported" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x28++0x0B line.long 0x00 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x08 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit And Base Upper 16 Bits Register" hexmask.long.word 0x08 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x08 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" else rgroup.long 0x28++0x0B line.long 0x00 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x08 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit And Base Upper 16 Bits Register" hexmask.long.word 0x08 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x08 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x34++0x03 line.long 0x00 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register" hexmask.long.byte 0x00 0.--7. 0x01 " CAP_POINTER ,Capabilities pointer" else group.long 0x34++0x03 line.long 0x00 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register" hexmask.long.byte 0x00 0.--7. 0x01 " CAP_POINTER ,Capabilities pointer" endif group.long 0x38++0x07 line.long 0x00 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " EXP_ROM_BASE_ADDRESS ,Expansion ROM base address" bitfld.long 0x00 0. " ROM_BAR_ENABLE ,Expansion ROM enable" "Disabled,Enabled" line.long 0x04 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control And Interrupt Pin And Interrupt Line Register" bitfld.long 0x04 22. " SBR ,Secondary bus reset" "No effect,Reset" newline rbitfld.long 0x04 21. " MSTR_ABORT_MODE ,Master abort mode" "0,?..." rbitfld.long 0x04 20. " VGA_16B_DEC ,VGA 16-bit decode" "10 bit,16 bit" newline rbitfld.long 0x04 19. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.long 0x04 18. " ISA_EN ,ISA enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.long 0x04 16. " PERE ,Parity error response enable" "Disabled,Enabled" newline hexmask.long.byte 0x04 8.--15. 1. " INT_PIN ,Interrupt PIN" hexmask.long.byte 0x04 0.--7. 1. " INT_LINE ,Interrupt line" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" bitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" newline bitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" bitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" newline rbitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" line.long 0x04 "CON_STATUS_REG,PCI Power Management Control And Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" newline rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support for D3hot" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME status" "0,1" newline rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SELECT ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8. " PME_ENABLE ,PME enable" "Disabled,Enabled" bitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" newline bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" else group.long 0x40++0x07 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" rbitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM event support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 26. " D2_SUPPORT ,D2 state support" "Not supported,Supported" newline rbitfld.long 0x00 25. " D1_SUPPORT ,D1 state support" "Not supported,Supported" rbitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" newline rbitfld.long 0x00 19. " PME_CLK ,PCI clock requirement" "0,1" rbitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Power management capability ID" line.long 0x04 "CON_STATUS_REG,PCI Power Management Control And Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REG_ADD_INFO ,Power data information" rbitfld.long 0x04 23. " BUS_PWR_CLK_CON_EN ,Bus power/clock control enable" "Disabled,Enabled" newline rbitfld.long 0x04 22. " B2_B3_SUPPORT ,B2 B3 support for D3hot" "Not supported,Supported" eventfld.long 0x04 15. " PME_STATUS ,PME status" "0,1" newline rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x04 9.--12. " DATA_SELECT ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8. " PME_ENABLE ,PME enable" "Disabled,Enabled" rbitfld.long 0x04 3. " NO_SOFT_RST ,No soft reset" "Low,High" newline bitfld.long 0x04 0.--1. " POWER_STATE ,Power state" "0,1,2,3" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) if (((per.l(ad:0x33800000+0x50))&0x2000000)==0x2000000) group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID And Next Pointer And Capability/Control Register" bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data capable" "Not capable,Capable" newline rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit address capable" "0,1" newline bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,MSI multiple message enable" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " PCI_MSI_ENABLE ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" newline hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" else group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID And Next Pointer And Capability/Control Register" rbitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data capable" "Not capable,Capable" newline rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit address capable" "0,1" newline bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,MSI multiple message enable" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " PCI_MSI_ENABLE ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" newline hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" endif else if (((per.l(ad:0x33800000+0x50))&0x2000000)==0x2000000) group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID And Next Pointer And Capability/Control Register" bitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Disabled,Enabled" rbitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data capable" "Not capable,Capable" newline rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" rbitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit address capable" "0,1" newline bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,MSI multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " PCI_MSI_ENABLE ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" newline hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" else group.long 0x50++0x03 line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID And Next Pointer And Capability/Control Register" rbitfld.long 0x00 26. " PCI_MSI_EXT_DATA_EN ,Extended message data enable" "Disabled,Enabled" rbitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP ,Extended message data capable" "Not capable,Capable" newline rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,MSI per vector masking capable" "Not supported,Supported" rbitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,MSI 64-bit address capable" "0,1" newline bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,MSI multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,MSI multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " PCI_MSI_ENABLE ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,MSI capability next pointer" newline hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,MSI capability ID" endif endif group.long 0x54++0x0F line.long 0x00 "MSI_CAP_OFF_04H_REG,Capability ID Next Pointer Control 04H Register" hexmask.long 0x00 2.--31. 0x04 " PCI_MSI_CAP_OFF_04H ,MSI message lower address field" line.long 0x04 "MSI_CAP_OFF_08H_REG,Capability ID Next Pointer Control 08H Register" hexmask.long.word 0x04 16.--31. 0x01 " PCI_MSI_CAP_OFF_0AH ,Capability offset 0AH" hexmask.long.word 0x04 0.--15. 0x01 " PCI_MSI_CAP_OFF_08H ,Capability offset 08H" line.long 0x08 "MSI_CAP_OFF_0CH_REG,MSI Capability ID Next Pointer Control 0CH Register" hexmask.long.word 0x08 16.--31. 0x01 " PCI_MSI_CAP_OFF_0EH ,Capability offset 0EH" hexmask.long.word 0x08 0.--15. 0x01 " PCI_MSI_CAP_OFF_0CH ,Capability offset 0CH" line.long 0x0C "MSI_CAP_OFF_10H_REG,Used For MSI When Vector Masking Capable" rgroup.long 0x64++0x03 line.long 0x00 "MSI_CAP_OFF_14H_REG,Used For MSI 64bit Messaging When Vector Masking Capable" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x70++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities And ID And Next Pointer Register" bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,PCIE interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " PCIE_SLOT_IMP ,PCIE slot implemented" "Not valid,Valid" newline rbitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,PCIE device/port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " PCIE_CAP_REG ,PCIE capability version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 0x01 " PCIE_CAP_NEXT_PTR ,PCIE next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,PCIE capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" newline bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size support" "0,1,2,3,4,5,6,7" else rgroup.long 0x70++0x07 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities And ID And Next Pointer Register" bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,PCIE interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " PCIE_SLOT_IMP ,PCIE slot implemented" "Not valid,Valid" newline bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,PCIE device/port type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,PCIE capability version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 0x01 " PCIE_CAP_NEXT_PTR ,PCIE next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,PCIE capability ID" line.long 0x04 "DEVICE_CAPABILITIES_REG,Device Capabilities Register" bitfld.long 0x04 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x04 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "Not supported,Supported" newline bitfld.long 0x04 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT ,Phantom functions support" "0,1,2,3" bitfld.long 0x04 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size support" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x33800000+0x74))&0x38)==0x00) group.long 0x78++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control And Status Register" rbitfld.long 0x00 21. " PCIE_CAP_TRANS_PENDING ,Transactions pending status" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DETECTED ,AUX power detected status" "Not detected,Detected" newline eventfld.long 0x00 19. " PCIE_CAP_UNSUPPORTED_REQ_DETECTED ,Unsupported request detected status" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DETECTED ,Fatal error detected status" "Not detected,Detected" newline eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DETECTED ,Non-fatal error detected status" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DETECTED ,Correctable error detected status" "Not detected,Detected" newline bitfld.long 0x00 15. " PCIE_CAP_INITIATE_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions enable" "Disabled,Enabled" rbitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x74))&0x38)==0x20) group.long 0x78++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control And Status Register" rbitfld.long 0x00 21. " PCIE_CAP_TRANS_PENDING ,Transactions pending status" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DETECTED ,AUX power detected status" "Not detected,Detected" newline eventfld.long 0x00 19. " PCIE_CAP_UNSUPPORTED_REQ_DETECTED ,Unsupported request detected status" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DETECTED ,Fatal error detected status" "Not detected,Detected" newline eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DETECTED ,Non-fatal error detected status" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DETECTED ,Correctable error detected status" "Not detected,Detected" newline bitfld.long 0x00 15. " PCIE_CAP_INITIATE_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions enable" "Disabled,Enabled" bitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x74))&0x18)!=0x00) if (((per.l(ad:0x33800000+0x74))&0x20)==0x00) group.long 0x78++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control And Status Register" rbitfld.long 0x00 21. " PCIE_CAP_TRANS_PENDING ,Transactions pending status" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DETECTED ,AUX power detected status" "Not detected,Detected" newline eventfld.long 0x00 19. " PCIE_CAP_UNSUPPORTED_REQ_DETECTED ,Unsupported request detected status" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DETECTED ,Fatal error detected status" "Not detected,Detected" newline eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DETECTED ,Non-fatal error detected status" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DETECTED ,Correctable error detected status" "Not detected,Detected" newline bitfld.long 0x00 15. " PCIE_CAP_INITIATE_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions enable" "Disabled,Enabled" rbitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" else group.long 0x78++0x03 line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control And Status Register" rbitfld.long 0x00 21. " PCIE_CAP_TRANS_PENDING ,Transactions pending status" "Completed,Not completed" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DETECTED ,AUX power detected status" "Not detected,Detected" newline eventfld.long 0x00 19. " PCIE_CAP_UNSUPPORTED_REQ_DETECTED ,Unsupported request detected status" "Not detected,Detected" eventfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DETECTED ,Fatal error detected status" "Not detected,Detected" newline eventfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DETECTED ,Non-fatal error detected status" "Not detected,Detected" eventfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DETECTED ,Correctable error detected status" "Not detected,Detected" newline bitfld.long 0x00 15. " PCIE_CAP_INITIATE_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions enable" "Disabled,Enabled" bitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error reporting enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE ,ASPM optionality compliance" "Not compliant,Compliant" newline bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "Not capable,Capable" rbitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "Not capable,Capable" newline bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "Not capable,Capable" rbitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LATENCY ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY ,L0s exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM ,Port number" bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE ,ASPM optionality compliance" "Not compliant,Compliant" newline bitfld.long 0x00 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "Not capable,Capable" bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "Not capable,Capable" newline bitfld.long 0x00 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " PCIE_CAP_L1_EXIT_LATENCY ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY ,L0s exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT ,Level of ASPM support" "0,1,2,3" bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x200000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x200000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" bitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" bitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x200000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x200000)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline bitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x40000) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Current link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline bitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x200000)==0x00)&&(((per.l(ad:0x33800000+0x7C))&0x40000)==0x00) group.long 0x80++0x03 line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" eventfld.long 0x00 31. " PCIE_CAP_LINK_AUTO_BW_STATUS ,Link autonomous bandwidth status" "0,1" eventfld.long 0x00 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x00 29. " PCIE_CAP_DLL_ACTIVE ,Data link layer active" "0,1" rbitfld.long 0x00 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x00 27. " PCIE_CAP_LINK_TRAINING ,Current link training" "0,1" rbitfld.long 0x00 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x00 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth management interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " PCIE_CAP_HW_AUTO_WIDTH_DISABLE ,Hardware autonomous width disable" "No,Yes" newline rbitfld.long 0x00 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x00 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x00 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "Asynchronous,Common" bitfld.long 0x00 5. " PCIE_CAP_RETRAIN_LINK ,Initiate link retrain" "0,1" newline bitfld.long 0x00 4. " PCIE_CAP_LINK_DISABLE ,Initiate link disable" "No,Yes" rbitfld.long 0x00 3. " PCIE_CAP_RCB ,Read completion boundary" "0,1" newline bitfld.long 0x00 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL ,Active state link PM control" "Disabled,L0s,L1,L0s/L1" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM ,Physical slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPPORT ,No command completion support" "Not supported,Supported" newline bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "Not present,Present" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" newline hexmask.long.word 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "Not possible,Possible" bitfld.long 0x00 4. " PCIE_CAP_POWER_INDICATOR ,Power indicator present" "Not present,Present" newline bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR ,Attention indicator present" "Not present,Present" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "Not present,Present" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " PCIE_CAP_ATTENTION_INDICATOR_BUTTON ,Attention button present" "Not present,Present" else rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM ,Physical slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPPORT ,No command completion support" "Not supported,Supported" newline bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "Not present,Present" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" newline hexmask.long.word 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise possible" "Not possible,Possible" bitfld.long 0x00 4. " PCIE_CAP_POWER_INDICATOR ,Power indicator present" "Not present,Present" newline bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR ,Attention indicator present" "Not present,Present" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL present" "Not present,Present" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " PCIE_CAP_ATTENTION_INDICATOR_BUTTON ,Attention button present" "Not present,Present" endif if (((per.l(ad:0x33800000+0x84))&0x40000)==0x40000) group.long 0x88++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control And Status Register" eventfld.long 0x00 24. " PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS ,Electromechanical interlock status" "0,1" newline rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DETECT_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" newline eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DETECTED_CHANGED ,Presence detect changed" "Not changed,Changed" newline eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DETECTED ,Power fault detected" "Not detected,Detected" newline eventfld.long 0x00 16. " PCIE_CAP_ATTENTION_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" newline bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_INDICATOR_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATTENTION_INDICATOR_CTRL ,Attention indicator control" ",On,Blink,On" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command completed interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DETECT_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR_CHANGED_EN ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DETECTED_EN ,Power fault detected enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control And Status Register" eventfld.long 0x00 24. " PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS ,Electromechanical interlock status" "0,1" newline rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DETECT_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" newline eventfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command completed" "0,1" eventfld.long 0x00 19. " PCIE_CAP_PRESENCE_DETECTED_CHANGED ,Presence detect changed" "Not changed,Changed" newline eventfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Not changed,Changed" eventfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DETECTED ,Power fault detected" "Not detected,Detected" newline eventfld.long 0x00 16. " PCIE_CAP_ATTENTION_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "No effect,Toggle" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" newline bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_INDICATOR_CTRL ,Power indicator control" ",On,Blink,On" bitfld.long 0x00 6.--7. " PCIE_CAP_ATTENTION_INDICATOR_CTRL ,Attention indicator control" ",On,Blink,On" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command completed interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DETECT_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR_CHANGED_EN ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DETECTED_EN ,Power fault detected enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x10000) group.long 0x8C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control And Capabilities Register" bitfld.long 0x00 16. " PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "Not capable,Capable" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x00) group.long 0x8C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control And Capabilities Register" bitfld.long 0x00 16. " PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "Not capable,Capable" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x10000) group.long 0x8C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control And Capabilities Register" rbitfld.long 0x00 16. " PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "Not capable,Capable" bitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" elif (((per.l(ad:0x33800000+0x8BC))&0x01)==0x00)&&(((per.l(ad:0x33800000+0x8C))&0x10000)==0x00) group.long 0x8C++0x03 line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control And Capabilities Register" rbitfld.long 0x00 16. " PCIE_CAP_CRS_SW_VISIBILITY ,CRS software visibility capable" "Not capable,Capable" rbitfld.long 0x00 4. " PCIE_CAP_CRS_SW_VISIBILITY_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS_REG,Root Status Register" rbitfld.long 0x00 17. " PCIE_CAP_PME_PENDING ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PCIE_CAP_PME_STATUS ,PME status" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " PCIE_CAP_PME_REQ_ID ,PME requester ID" rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register" bitfld.long 0x00 18.--19. " PCIE_CAP_OBFF_SUPPORT ,Optimized buffer flush/fill supported" "Not supported,Msg,WAKE#,Both" bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT ,10-bit tag request supported" "Not supported,Supported" newline bitfld.long 0x00 16. " PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT ,10-bit tag completer supported" "Not supported,Supported" bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPPORT_1 ,TPH completer supported bit 1" "0,1" newline bitfld.long 0x00 12. " PCIE_CAP_TPH_CMPLT_SUPPORT_0 ,TPH completer supported bit 0" "0,1" bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,LTR mechanism supported" "Not supported,Supported" newline bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 bit CAS completer supported" "Not supported,Supported" newline bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 bit atomicOp completer supported" "Not supported,Supported" bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 bit atomicOp completer supported" "Not supported,Supported" newline bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic operation routing supported" "Not supported,Supported" bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT ,ARI forward supported" "Not supported,Supported" newline bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,Completion timeout ranges supported" "A,B,A/B,,,,B/C,A/B/C,,,,,,,B/C/D,A/B/C/D" group.long 0x98++0x03 line.long 0x00 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 And Status 2 Register" bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DISABLE ,Completion timeout disable" "No,Yes" newline bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VALUE ,Completion timeout value" "50us to 50ms,50us to 100us,1ms to 10ms,,,16ms to 55ms,65ms to 210ms,,,260ms to 900ms,1s to 3.5s,,,4s to 13s,17s to 64s,?..." rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register" bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT ,Cross link supported" "Not supported,Supported" hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0xA0++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 And Status 2 Register" eventfld.long 0x00 31. " DRS_MESSAGE_RECEIVED ,DRS message received" "Not received,Received" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" newline bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Sets compliance SOS" "Not set,Set" newline bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "Not entered,Entered" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-6dB,-3.5dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "No,Yes" newline bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "Not entered,Entered" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,?..." else group.long 0xA0++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 And Status 2 Register" eventfld.long 0x00 31. " DRS_MESSAGE_RECEIVED ,DRS message received" "Not received,Received" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6dB,-3.5dB" newline bitfld.long 0x00 12.--15. " PCIE_CAP_COMPLIANCE_PRESET ,Compliance preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " PCIE_CAP_COMPLIANCE_SOS ,Sets compliance SOS" "Not set,Set" newline bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMPILANCE ,Enter modified compliance" "Not entered,Entered" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Controls selectable de-emphasis" "-6dB,-3.5dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DISABLE ,Hardware autonomous speed disable" "No,Yes" newline bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMPLIANCE ,Enter compliance mode" "Not entered,Entered" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",0,1,2,3,4,5,6,?..." endif if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,AER extended capability ID" else rgroup.long 0x100++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,AER extended capability ID" endif group.long 0x104++0x03 line.long 0x00 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register" eventfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_STATUS ,TLP_PRFX blocked error status" "No error,Error" eventfld.long 0x00 22. " INTERNAL_ERR_STATUS ,Uncorrectable internal error status" "No error,Error" newline eventfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_STATUS ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRC_ERR_STATUS ,ECRC error status" "No error,Error" newline eventfld.long 0x00 18. " MALF_TLP_ERR_STATUS ,Malformed TLP error status" "No error,Error" eventfld.long 0x00 17. " REC_OVERFLOW_ERR_STATUS ,Receiver overflow error status" "No overflow,Overflow" newline eventfld.long 0x00 16. " UNEXP_CMPLT_ERR_STATUS ,Unexpected completion error status" "No error,Error" eventfld.long 0x00 15. " CMPLT_ABORT_ERR_STATUS ,Completer abort error status" "No error,Error" newline eventfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_STATUS ,Completion timeout error status" "No error,Error" eventfld.long 0x00 13. " FC_PROTOCOL_ERR_STATUS ,Flow control protocol error status" "No error,Error" newline eventfld.long 0x00 12. " POIS_TLP_ERR_STATUS ,Poisoned TLP error status" "No error,Error" eventfld.long 0x00 5. " SURPRISE_DOWN_ERR_STATUS ,Surprise down error status" "No error,Error" newline eventfld.long 0x00 4. " DL_PROTOCOL_ERR_STATUS ,Data link protocol error status" "No error,Error" if (((per.l(ad:0x33800000+0x7C))&0x80000)==0x80000) group.long 0x108++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp block error mask" "Not masked,Masked" newline bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" newline bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP error mask" "Not masked,Masked" newline bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion error mask" "Not masked,Masked" newline bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" newline bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" newline bitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,AtomicOp egress blocked error severity" "Not occurred,Occurred" newline bitfld.long 0x04 22. " INTERNAL_ERR_SEVERITY ,Uncorrectable internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPPORTED_REQ_ERR_SEVERITY ,Unsupported request error severity" "Not occurred,Occurred" newline bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEVERITY ,Malformed TLP error severity" "Not occurred,Occurred" newline bitfld.long 0x04 17. " REC_OVERFLOW_ERR_SEVERITY ,Receiver overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" newline bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" newline bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" newline bitfld.long 0x04 5. " SURPRISE_DOWN_ERR_SEVERITY ,Surprise down error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" else group.long 0x108++0x07 line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,AtomicOp block error mask" "Not masked,Masked" newline bitfld.long 0x00 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x00 20. " UNSUPPORTED_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" newline bitfld.long 0x00 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x00 18. " MALF_TLP_ERR_MASK ,Malformed TLP error mask" "Not masked,Masked" newline bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK ,Receiver overflow error mask" "Not masked,Masked" bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion error mask" "Not masked,Masked" newline bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK ,Completer abort error mask" "Not masked,Masked" bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout error mask" "Not masked,Masked" newline bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x00 12. " POIS_TLP_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" newline rbitfld.long 0x00 5. " SURPRISE_DOWN_ERR_MASK ,Surprise down error mask" "Not masked,Masked" bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x04 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" bitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_SEVERITY ,TLP prefix blocked error severity" "Not occurred,Occurred" bitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY ,AtomicOp egress blocked error severity" "Not occurred,Occurred" newline bitfld.long 0x04 22. " INTERNAL_ERR_SEVERITY ,Uncorrectable internal error severity" "Not occurred,Occurred" bitfld.long 0x04 20. " UNSUPPORTED_REQ_ERR_SEVERITY ,Unsupported request error severity" "Not occurred,Occurred" newline bitfld.long 0x04 19. " ECRC_ERR_SEVERITY ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x04 18. " MALF_TLP_ERR_SEVERITY ,Malformed TLP error severity" "Not occurred,Occurred" newline bitfld.long 0x04 17. " REC_OVERFLOW_ERR_SEVERITY ,Receiver overflow error severity" "Not occurred,Occurred" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_SEVERITY ,Unexpected completion error severity" "Not occurred,Occurred" newline bitfld.long 0x04 15. " CMPLT_ABORT_ERR_SEVERITY ,Completer abort error severity" "Not occurred,Occurred" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_SEVERITY ,Completion timeout error severity" "Not occurred,Occurred" newline bitfld.long 0x04 13. " FC_PROTOCOL_ERR_SEVERITY ,Flow control protocol error severity" "Not occurred,Occurred" bitfld.long 0x04 12. " POIS_TLP_ERR_SEVERITY ,Poisoned TLP error severity" "Not occurred,Occurred" newline rbitfld.long 0x04 5. " SURPRISE_DOWN_ERR_SEVERITY ,Surprise down error severity" "Not occurred,Occurred" bitfld.long 0x04 4. " DL_PROTOCOL_ERR_SEVERITY ,Data link protocol error severity" "Not occurred,Occurred" endif group.long 0x110++0x0B line.long 0x00 "CORR_ERR_STATUS_OFF,Correctable Error Status Register" eventfld.long 0x00 15. " HEADER_LOG_OVERFLOW_STATUS ,Header log overflow error status" "Not occurred,Occurred" eventfld.long 0x00 14. " CORRECTED_INT_ERR_STATUS ,Corrected internal error status" "Not occurred,Occurred" newline eventfld.long 0x00 13. " ADVISORY_NON_FATAL_ERR_STATUS ,Advisory non-fatal error status" "Not occurred,Occurred" eventfld.long 0x00 12. " RPL_TIMER_TIMEOUT_STATUS ,Replay timer timeout status" "Not occurred,Occurred" newline eventfld.long 0x00 8. " REPLAY_NO_ROLLOVER_STATUS ,Replay number rollover status" "Not occurred,Occurred" eventfld.long 0x00 7. " BAD_DLLP_STATUS ,Bad DLLP status" "Not occurred,Occurred" newline eventfld.long 0x00 6. " BAD_TLP_STATUS ,Bad TLP status" "Not occurred,Occurred" eventfld.long 0x00 0. " RX_ERR_STATUS ,Receiver error status" "Not occurred,Occurred" line.long 0x04 "CORR_ERR_MASK_OFF,Correctable Error Mask Register" bitfld.long 0x04 15. " HEADER_LOG_OVERFLOW_MASK ,Header log overflow error mask" "Not occurred,Occurred" bitfld.long 0x04 14. " CORRECTED_INT_ERR_MASK ,Corrected internal error mask" "Not masked,Masked" newline bitfld.long 0x04 13. " ADVISORY_NON_FATAL_ERR_MASK ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x04 12. " RPL_TIMER_TIMEOUT_MASK ,Replay timer timeout mask" "Not masked,Masked" newline bitfld.long 0x04 8. " REPLAY_NO_ROLLOVER_MASK ,Replay number rollover mask" "Not masked,Masked" bitfld.long 0x04 7. " BAD_DLLP_MASK ,Bad DLLP mask" "Not masked,Masked" newline bitfld.long 0x04 6. " BAD_TLP_MASK ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x04 0. " RX_ERR_MASK ,Receiver error mask" "Not masked,Masked" line.long 0x08 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities And Control Register" rbitfld.long 0x08 10. " MULTIPLE_HEADER_EN ,Multiple header recording enable" "Disabled,Enabled" rbitfld.long 0x08 9. " MULTIPLE_HEADER_CAP ,Multiple header recording capable" "Not capable,Capable" newline bitfld.long 0x08 8. " ECRC_CHECK_EN ,ECRC check enable" "Disabled,Enabled" rbitfld.long 0x08 7. " ECRC_CHECK_CAP ,ECRC check capable" "Not capable,Capable" newline bitfld.long 0x08 6. " ECRC_GEN_EN ,ECRC generation enable" "Disabled,Enabled" rbitfld.long 0x08 5. " ECRC_GEN_CAP ,ECRC generation capable" "Not capable,Capable" newline hexmask.long.byte 0x08 0.--4. 0x01 " FIRST_ERR_POINTER ,First error pointer" rgroup.long 0x11C++0x0F line.long 0x00 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE ,Byte 3 of header log register of first 32 bit data word" hexmask.long.byte 0x00 16.--23. 1. " FIRST_DWORD_THIRD_BYTE ,Byte 2 of header log register of first 32 bit data word" newline hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE ,Byte 1 of header log register of first 32 bit data word" hexmask.long.byte 0x00 0.--7. 1. " FIRST_DWORD_FIRST_BYTE ,Byte 0 of header log register of first 32 bit data word" line.long 0x04 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE ,Byte 3 of header log register of second 32 bit data word" hexmask.long.byte 0x04 16.--23. 1. " SECOND_DWORD_THIRD_BYTE ,Byte 2 of header log register of second 32 bit data word" newline hexmask.long.byte 0x04 8.--15. 1. " SECOND_DWORD_SECOND_BYTE ,Byte 1 of header log register of second 32 bit data word" hexmask.long.byte 0x04 0.--7. 1. " SECOND_DWORD_FIRST_BYTE ,Byte 0 of header log register of second 32 bit data word" line.long 0x08 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE ,Byte 3 of header log register of third 32 bit data word" hexmask.long.byte 0x08 16.--23. 1. " THIRD_DWORD_THIRD_BYTE ,Byte 2 of header log register of third 32 bit data word" newline hexmask.long.byte 0x08 8.--15. 1. " THIRD_DWORD_SECOND_BYTE ,Byte 1 of header log register of third 32 bit data word" hexmask.long.byte 0x08 0.--7. 1. " THIRD_DWORD_FIRST_BYTE ,Byte 0 of header log register of third 32 bit data word" line.long 0x0C "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE ,Byte 3 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 16.--23. 1. " FOURTH_DWORD_THIRD_BYTE ,Byte 2 of header log register of fourth 32 bit data word" newline hexmask.long.byte 0x0C 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE ,Byte 1 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 0.--7. 1. " FOURTH_DWORD_FIRST_BYTE ,Byte 0 of header log register of fourth 32 bit data word" group.long 0x12C++0x03 line.long 0x00 "ROOT_ERR_CMD_OFF,Root Error Command Register" bitfld.long 0x00 2. " FATAL_ERR_REPORTING_EN ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN ,Non-fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CORR_ERR_REPORTING_EN ,Correctable error reporting enable" "Disabled,Enabled" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x130++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" bitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" newline eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal error" "No error,Error" newline eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal error received" "Not received,Received" newline eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received" "Not received,Received" else group.long 0x130++0x03 line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register" rbitfld.long 0x00 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x00 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" newline eventfld.long 0x00 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x00 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal error" "No error,Error" newline eventfld.long 0x00 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple fatal or non-fatal errors received" "Not received,Received" eventfld.long 0x00 2. " ERR_FATAL_NON_FATAL_RX ,Fatal or non-fatal error received" "Not received,Received" newline eventfld.long 0x00 1. " MUL_ERR_COR_RX ,Multiple correctable errors received" "Not received,Received" eventfld.long 0x00 0. " ERR_COR_RX ,Correctable error received" "Not received,Received" endif rgroup.long 0x134++0x13 line.long 0x00 "ERR_SRC_ID_OFF,Error Source Identification Register" hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID ,Source of fatal/non-fatal error" hexmask.long.word 0x00 0.--15. 1. " ERR_COR_SOURCE_ID ,Source of correctable error" line.long 0x04 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE ,Byte 3 of error TLP prefix log 1" hexmask.long.byte 0x04 16.--23. 1. " CFG_TLP_PFX_LOG_1_THIRD_BYTE ,Byte 2 of error TLP prefix log 1" newline hexmask.long.byte 0x04 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE ,Byte 1 of error TLP prefix log 1" hexmask.long.byte 0x04 0.--7. 1. " CFG_TLP_PFX_LOG_1_FIRST_BYTE ,Byte 0 of error TLP prefix log 1" line.long 0x08 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE ,Byte 3 of error TLP prefix log 2" hexmask.long.byte 0x08 16.--23. 1. " CFG_TLP_PFX_LOG_2_THIRD_BYTE ,Byte 2 of error TLP prefix log 2" newline hexmask.long.byte 0x08 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE ,Byte 1 of error TLP prefix log 2" hexmask.long.byte 0x08 0.--7. 1. " CFG_TLP_PFX_LOG_2_FIRST_BYTE ,Byte 0 of error TLP prefix log 2" line.long 0x0C "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE ,Byte 3 of error TLP prefix log 3" hexmask.long.byte 0x0C 16.--23. 1. " CFG_TLP_PFX_LOG_3_THIRD_BYTE ,Byte 2 of error TLP prefix log 3" newline hexmask.long.byte 0x0C 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE ,Byte 1 of error TLP prefix log 3" hexmask.long.byte 0x0C 0.--7. 1. " CFG_TLP_PFX_LOG_3_FIRST_BYTE ,Byte 0 of error TLP prefix log 3" line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE ,Byte 3 of error TLP prefix log 4" hexmask.long.byte 0x10 16.--23. 1. " CFG_TLP_PFX_LOG_4_THIRD_BYTE ,Byte 2 of error TLP prefix log 4" newline hexmask.long.byte 0x10 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE ,Byte 1 of error TLP prefix log 4" hexmask.long.byte 0x10 0.--7. 1. " CFG_TLP_PFX_LOG_4_FIRST_BYTE ,Byte 0 of error TLP prefix log 4" if (((per.l(ad:0x33800000+0x8BC))&0x01)==0x01) group.long 0x148++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB extended capability ID" else rgroup.long 0x148++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAP_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,L1SUB extended capability ID" endif group.long 0x14C++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register" bitfld.long 0x00 19.--23. " PWR_ON_VALUE_SUPPORT ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPPORT ,Port T power on scale" "0,1,2,3" newline hexmask.long.byte 0x00 8.--15. 1. " COME_MODE_SUPPORT ,Port common mode restore time" bitfld.long 0x00 4. " L1_PMSUB_SUPPORT ,L1 PM substates ECN supported" "Not supported,Supported" newline bitfld.long 0x00 3. " L1_1_ASPM_SUPPORT ,ASPM L11 supported" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT ,ASPM L12 supported" "Not supported,Supported" newline bitfld.long 0x00 1. " L1_1_PCIPM_SUPPORT ,PCI-PM L11 supported" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCIPM_SUPPORT ,PCI-PM L12 supported" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 threshold scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 threshold value" newline hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,ASPM L11 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " L1_2_ASPM_EN ,ASPM L12 enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,PCI-PM L11 enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " L1_2_PCIPM_EN ,PCI-PM L12 enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VALUE ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "0,1,2,3" group.long 0x700++0x27 line.long 0x00 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer And Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT ,Replay timer limit" hexmask.long.word 0x00 0.--15. 1. " ROUND_TRIP_LATENCY_TIME_LIMIT ,Ack latency timer limit" line.long 0x04 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register" line.long 0x08 "PORT_FORCE_OFF,Port Force Link Register" bitfld.long 0x08 23. " DO_DESKEW_FOR_SRIS ,Use the transitions from TS2 to logical idle symbol" "0,1" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline eventfld.long 0x08 15. " FORCE_EN ,Force link" "Disabled,Enabled" bitfld.long 0x08 8.--11. " FORCED_LTSSM ,Forced link command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x08 0.--7. 1. " LINK_NUM ,Link number" line.long 0x0C "ACK_F_ASPM_CTRL_OFF,Ack Frequency And L0-L1 ASPM Control Register" bitfld.long 0x0C 30. " ENTER_ASPM ,ASPM L1 entry control" "Not entered,Entered" bitfld.long 0x0C 27.--29. " L1_ENTRANCE_LATENCY ,L1 entrance latency" "1 us,2 us,4 us,8 us,16 us,32 us,64 us,64 us" newline bitfld.long 0x0C 24.--26. " L0S_ENTRANCE_LATENCY ,L0s entrance latency" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,7 us" hexmask.long.byte 0x0C 16.--23. 1. " COMMON_CLK_N_FTS ,Common clock N_FTS" newline hexmask.long.byte 0x0C 8.--15. 1. " ACK_N_FTS ,Number of fast training sequence" hexmask.long.byte 0x0C 0.--7. 1. " ACK_FREQ ,Ack frequency" line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register" bitfld.long 0x10 16.--21. " LINK_CAPABLE ,Link mode enable" ",X1,,X2,,,,X4,,,,,,,,X8,,,,,,,,,,,,,,,,X16,?..." bitfld.long 0x10 7. " FAST_LINK_MODE ,Fast link mode" "No fast mode,Fast mode" newline bitfld.long 0x10 5. " DLL_LINK_EN ,DLL link enable" "Disabled,Enabled" bitfld.long 0x10 3. " RESET_ASSERT ,Reset assert" "No reset,Reset" newline bitfld.long 0x10 2. " LOOPBACK_ENABLE ,Loopback enable" "Disabled,Enabled" bitfld.long 0x10 1. " SCRAMBLE_DISABLE ,Scramble disable" "No,Yes" newline eventfld.long 0x10 0. " VENDOR_SPECIFIC_DLLP_REQ ,Vendor specific DLLP request" "Not requested,Requested" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register" bitfld.long 0x14 31. " DISABLE_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "No,Yes" bitfld.long 0x14 27.--30. " IMPLEMENT_NUM_LANES ,Number of lanes" "1 lane,2 lanes,,4 lanes,,,,8 lanes,,,,,,,,16 lanes" newline bitfld.long 0x14 26. " GEN34_ELASTIC_BUFFER_MODE ,Selects elasticity buffer operating mode in gen3/gen4" "Half full,Empty" bitfld.long 0x14 25. " ACK_NAK_DISABLE ,Ack/nak disable" "No,Yes" newline bitfld.long 0x14 24. " FLOW_CTRL_DISABLE ,Flow control disable" "No,Yes" line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control And Max Function Number Register" bitfld.long 0x18 29.--30. " FAST_LINK_SCALING_FACTOR ,Fast link timer scaling factor" "1024,256,64,16" bitfld.long 0x18 19.--23. " TIMER_MOD_ACK_NAK ,Ack latency timer modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 14.--18. " TIMER_MOD_REPLAY_TIMER ,Replay timer limit modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 0.--7. 1. " MAX_FUNC_NUM ,Maximum function number" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register And Filter Mask 1 Register" bitfld.long 0x1C 31. " CX_FLT_MASK_RC_CFG_DISCARD ,RC CFG discard mask" "Not masked,Masked" bitfld.long 0x1C 30. " CX_FLT_MASK_RC_IO_DISCARD ,RC IO discard mask" "Not masked,Masked" newline bitfld.long 0x1C 29. " CX_FLT_MASK_MSG_DROP ,Drop MSG TLP mask" "Not masked,Masked" bitfld.long 0x1C 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,Mask discarding completions with ECRC errors" "Not masked,Masked" newline bitfld.long 0x1C 27. " CX_FLT_MASK_ECRC_DISCARD ,Mask discarding TLPs with ECRC errors" "Not masked,Masked" bitfld.long 0x1C 26. " CX_FLT_MASK_CPL_LEN_MATCH ,Mask length match for completions" "Not masked,Masked" newline bitfld.long 0x1C 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,Mask attribute match for completions" "Not masked,Masked" bitfld.long 0x1C 24. " CX_FLT_MASK_CPL_TC_MATCH ,Mask traffic class match for completions" "Not masked,Masked" newline bitfld.long 0x1C 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,Mask function match for completions" "Not masked,Masked" bitfld.long 0x1C 22. " CX_FLT_MASK_CPL_REQID_MATCH ,Mask request ID match for completions" "Not masked,Masked" newline bitfld.long 0x1C 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,Mask tag error rules for completions" "Not masked,Masked" bitfld.long 0x1C 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,Mask treating locked read TLPs as UR for EP" "Not masked,Masked" newline bitfld.long 0x1C 19. " CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR ,Mask treating CFG type1 TLPs as UR for EP" "Not masked,Masked" bitfld.long 0x1C 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,Mask treating out-of-bar TLPs as UR" "Not masked,Masked" newline bitfld.long 0x1C 17. " CX_FLT_MASK_UR_POIS ,Mask treating poisoned request TLPs as UR" "Not masked,Masked" bitfld.long 0x1C 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,Mask treating function mismatched TLPs as UR" "Not masked,Masked" newline bitfld.long 0x1C 15. " DISABLE_FC_WD_TIMER ,Disable FC watchdog timer" "No,Yes" hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register" bitfld.long 0x20 7. " CX_FLT_MASK_PRS_DROP ,Drop PRS messages silently" "Not dropped,Dropped" bitfld.long 0x20 6. " CX_FLT_UNMASK_TD ,Unmask TD bit enable" "Disabled,Enabled" newline bitfld.long 0x20 5. " CX_FLT_UNMASK_UR_POIS_TRGT0 ,Unmask CX_FLT_MASK_UR_POIS enable" "Disabled,Enabled" bitfld.long 0x20 4. " CX_FLT_MASK_LN_VENMSG1_DROP ,Drop LN messages silently" "Not dropped,Dropped" newline bitfld.long 0x20 3. " CX_FLT_MASK_HANDLE_FLUSH ,Controller filter to handle flush request enable" "Disabled,Enabled" bitfld.long 0x20 2. " CX_FLT_MASK_DABORT_4UCPL ,DLLP abort for unexpected completion disable" "No,Yes" newline bitfld.long 0x20 1. " CX_FLT_MASK_VENMSG1_DROP ,Vendor MSG type 1 not dropped" "Dropped,Not dropped" bitfld.long 0x20 0. " CX_FLT_MASK_VENMSG0_DROP ,Vendor MSG type 0 not dropped" "Dropped,Not dropped" line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register" bitfld.long 0x24 0. " OB_RD_SPLIT_BURST_EN ,Enable AMBA multiple outbound decomposed NP SubRequests" "Disabled,Enabled" rgroup.long 0x728++0x13 line.long 0x00 "PL_DEBUG0_OFF,Debug Register 0" line.long 0x04 "PL_DEBUG1_OFF,Debug Register 1" line.long 0x08 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x08 12.--19. 1. " TX_P_HEADER_FC_CREDIT ,Transmit posted header FC credits" hexmask.long.word 0x08 0.--11. 1. " TX_P_DATA_FC_CREDIT ,Transmit posted data FC credits" line.long 0x0C "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.byte 0x0C 12.--19. 1. " TX_NP_HEADER_FC_CREDIT ,Transmit non-posted header FC credits" hexmask.long.word 0x0C 0.--11. 1. " TX_NP_DATA_FC_CREDIT ,Transmit non-posted data FC credits" line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.byte 0x10 12.--19. 1. " TX_CPL_HEADER_FC_CREDIT ,Transmit completion header FC credits" hexmask.long.word 0x10 0.--11. 1. " TX_CPL_DATA_FC_CREDIT ,Transmit completion data FC credits" group.long 0x73C++0x03 line.long 0x00 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x00 31. " TIMER_MOD_FLOW_CONTROL_EN ,FC latency timer override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " TIMER_MOD_FLOW_CONTROL ,FC latency timer override value" newline eventfld.long 0x00 15. " RX_SERIALIZATION_Q_READ_ERR ,Received serialization read error" "No error,Error" eventfld.long 0x00 14. " RX_SERIALIZATION_Q_WRITE_ERR ,Received serialization queue write error" "No error,Error" newline rbitfld.long 0x00 13. " RX_SERIALIZATION_Q_NON_EMPTY ,Received serialization queue not empty" "Empty,Not empty" eventfld.long 0x00 3. " RX_QUEUE_OVERFLOW ,Received credit queue overflow" "No overflow,Overflow" newline rbitfld.long 0x00 2. " RX_QUEUE_NON_EMPTY ,Received credit queue not empty" "Empty,Not empty" rbitfld.long 0x00 1. " TX_RETRY_BUFFER_NE ,Transmit retry buffer not empty" "Empty,Not empty" newline rbitfld.long 0x00 0. " RX_TLP_FC_CREDIT_NON_RETURN ,Received TLP FC credits not returned" "Returned,Not returned" rgroup.long 0x740++0x07 line.long 0x00 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3 ,WRR weight for VC3" hexmask.long.byte 0x00 16.--23. 1. " WRR_WEIGHT_VC_2 ,WRR weight for VC2" newline hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1 ,WRR weight for VC1" hexmask.long.byte 0x00 0.--7. 1. " WRR_WEIGHT_VC_0 ,WRR weight for VC0" line.long 0x04 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x04 24.--31. 1. " WRR_WEIGHT_VC_7 ,WRR weight for VC7" hexmask.long.byte 0x04 16.--23. 1. " WRR_WEIGHT_VC_6 ,WRR weight for VC6" newline hexmask.long.byte 0x04 8.--15. 1. " WRR_WEIGHT_VC_5 ,WRR weight for VC5" hexmask.long.byte 0x04 0.--7. 1. " WRR_WEIGHT_VC_4 ,WRR weight for VC4" group.long 0x748++0x0B line.long 0x00 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x00 31. " VC_ORDERING_RX_Q ,VC ordering for receive queues" "Round-robin,Strict" bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC0 ,TLP type ordering for VC0" "Strict,PCIe" newline bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE ,VC0 scale posted data credits" "0,1,2,3" bitfld.long 0x00 24.--25. " VC0_P_HDR_SCALE ,VC0 scale posted header credits" "0,1,2,3" newline hexmask.long.byte 0x00 12.--19. 1. " VC0_P_HEADER_CREDIT ,VC0 posted header credits" hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CREDIT ,VC0 posted data credits" line.long 0x04 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" bitfld.long 0x04 26.--27. " VC0_NP_DATA_SCALE ,VC0 scale non-posted data credits" "0,1,2,3" bitfld.long 0x04 24.--25. " VC0_NP_HDR_SCALE ,VC0 scale non-posted header credits" "0,1,2,3" newline hexmask.long.byte 0x04 12.--19. 1. " VC0_NP_HEADER_CREDIT ,VC0 non-posted header credits" hexmask.long.word 0x04 0.--11. 1. " VC0_NP_DATA_CREDIT ,VC0 non-posted data credits" line.long 0x08 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" bitfld.long 0x08 26.--27. " VC0_CPL_DATA_SCALE ,VC0 scale CPL data credits" "0,1,2,3" bitfld.long 0x08 24.--25. " VC0_CPL_HDR_SCALE ,VC0 scale CPL header credits" "0,1,2,3" newline hexmask.long.byte 0x08 12.--19. 1. " VC0_CPL_HEADER_CREDIT ,VC0 completion header credits" hexmask.long.word 0x08 0.--11. 1. " VC0_CPL_DATA_CREDIT ,VC0 completion data credits" group.long 0x80C++0x03 line.long 0x00 "GEN2_CTRL_OFF,Link Width And Speed Change Control Register" bitfld.long 0x00 21. " GEN1_EI_INFERENCE ,Electrical idle inference mode at gen1 rate" "RxElecIdle,RxValid" bitfld.long 0x00 20. " SEL_DEEMPHASIS ,Select de-emphasis" "-6 dB,-3.5 dB" newline bitfld.long 0x00 19. " CONFIG_TX_COMP_RX ,Config TX compliance receive bit" "No effect,LTSSM signaled" bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE ,Config PHY TX swing" "Full,Low" newline bitfld.long 0x00 17. " DIRECT_SPEED_CHANGE ,Directed speed change" "No effect,Speed change" bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN ,Enable auto flipping of the lanes" "Disabled,Enabled" newline bitfld.long 0x00 13.--15. " PRE_DET_LANE ,Predetermined lane for auto flip" "Phy L0,Phy L1,Phy L3,Phy L7,Phy L15,?..." bitfld.long 0x00 8.--12. " NUM_OF_LANES ,Predetermined number of lanes" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x00 0.--7. 1. " FAST_TRAINING_SEQ ,Number of fast training sequences" rgroup.long 0x810++0x03 line.long 0x00 "PHY_STATUS_OFF,PHY Status Register" group.long 0x814++0x03 line.long 0x00 "PHY_CONTROL_OFF,PHY Control Register" group.long 0x81C++0x0B line.long 0x00 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register" bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX ,The number of the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " TARGET_MAP_ROM ,Target value for the ROM page of the PF function" "0,1" newline bitfld.long 0x00 0.--5. " TARGET_MAP_PF ,Target values for each BAR on the PF function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register" line.long 0x08 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register" newline width 27. group.long 0x828++0x0B line.long 0x00 "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 0" bitfld.long 0x00 31. " MSI_CTRL_INT_0_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 0" bitfld.long 0x04 31. " MSI_CTRL_INT_0_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 0" eventfld.long 0x08 31. " MSI_CTRL_INT_0_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x834++0x0B line.long 0x00 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 1" bitfld.long 0x00 31. " MSI_CTRL_INT_1_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 1" bitfld.long 0x04 31. " MSI_CTRL_INT_1_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 1" eventfld.long 0x08 31. " MSI_CTRL_INT_1_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x840++0x0B line.long 0x00 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 2" bitfld.long 0x00 31. " MSI_CTRL_INT_2_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 2" bitfld.long 0x04 31. " MSI_CTRL_INT_2_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 2" eventfld.long 0x08 31. " MSI_CTRL_INT_2_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x84C++0x0B line.long 0x00 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 3" bitfld.long 0x00 31. " MSI_CTRL_INT_3_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 3" bitfld.long 0x04 31. " MSI_CTRL_INT_3_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 3" eventfld.long 0x08 31. " MSI_CTRL_INT_3_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x858++0x0B line.long 0x00 "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 4" bitfld.long 0x00 31. " MSI_CTRL_INT_4_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 4" bitfld.long 0x04 31. " MSI_CTRL_INT_4_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 4" eventfld.long 0x08 31. " MSI_CTRL_INT_4_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x864++0x0B line.long 0x00 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 5" bitfld.long 0x00 31. " MSI_CTRL_INT_5_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 5" bitfld.long 0x04 31. " MSI_CTRL_INT_5_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 5" eventfld.long 0x08 31. " MSI_CTRL_INT_5_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x870++0x0B line.long 0x00 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 6" bitfld.long 0x00 31. " MSI_CTRL_INT_6_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 6" bitfld.long 0x04 31. " MSI_CTRL_INT_6_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 6" eventfld.long 0x08 31. " MSI_CTRL_INT_6_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" group.long 0x87C++0x0B line.long 0x00 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt Enable Register 7" bitfld.long 0x00 31. " MSI_CTRL_INT_7_EN[31] ,MSI interrupt 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,MSI interrupt 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,MSI interrupt 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,MSI interrupt 28 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,MSI interrupt 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,MSI interrupt 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,MSI interrupt 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,MSI interrupt 24 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,MSI interrupt 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,MSI interrupt 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,MSI interrupt 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,MSI interrupt 20 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,MSI interrupt 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,MSI interrupt 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,MSI interrupt 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,MSI interrupt 16 enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,MSI interrupt 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,MSI interrupt 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,MSI interrupt 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,MSI interrupt 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,MSI interrupt 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,MSI interrupt 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,MSI interrupt 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,MSI interrupt 8 enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,MSI interrupt 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,MSI interrupt 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,MSI interrupt 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,MSI interrupt 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,MSI interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,MSI interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,MSI interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,MSI interrupt 0 enable" "Disabled,Enabled" line.long 0x04 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt Mask Register 7" bitfld.long 0x04 31. " MSI_CTRL_INT_7_MASK[31] ,MSI interrupt 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,MSI interrupt 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,MSI interrupt 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,MSI interrupt 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,MSI interrupt 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,MSI interrupt 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,MSI interrupt 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,MSI interrupt 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,MSI interrupt 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,MSI interrupt 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,MSI interrupt 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,MSI interrupt 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,MSI interrupt 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,MSI interrupt 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,MSI interrupt 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,MSI interrupt 16 mask" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,MSI interrupt 15 mask" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,MSI interrupt 14 mask" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,MSI interrupt 13 mask" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,MSI interrupt 12 mask" "Not masked,Masked" newline bitfld.long 0x04 11. " [11] ,MSI interrupt 11 mask" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,MSI interrupt 10 mask" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,MSI interrupt 9 mask" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,MSI interrupt 8 mask" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,MSI interrupt 7 mask" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,MSI interrupt 6 mask" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,MSI interrupt 5 mask" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,MSI interrupt 4 mask" "Not masked,Masked" newline bitfld.long 0x04 3. " [3] ,MSI interrupt 3 mask" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,MSI interrupt 2 mask" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,MSI interrupt 1 mask" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,MSI interrupt 0 mask" "Not masked,Masked" line.long 0x08 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt Status Register 7" eventfld.long 0x08 31. " MSI_CTRL_INT_7_STATUS[31] ,MSI interrupt 31 status" "Not detected,Detected" eventfld.long 0x08 30. " [30] ,MSI interrupt 30 status" "Not detected,Detected" eventfld.long 0x08 29. " [29] ,MSI interrupt 29 status" "Not detected,Detected" eventfld.long 0x08 28. " [28] ,MSI interrupt 28 status" "Not detected,Detected" newline eventfld.long 0x08 27. " [27] ,MSI interrupt 27 status" "Not detected,Detected" eventfld.long 0x08 26. " [26] ,MSI interrupt 26 status" "Not detected,Detected" eventfld.long 0x08 25. " [25] ,MSI interrupt 25 status" "Not detected,Detected" eventfld.long 0x08 24. " [24] ,MSI interrupt 24 status" "Not detected,Detected" newline eventfld.long 0x08 23. " [23] ,MSI interrupt 23 status" "Not detected,Detected" eventfld.long 0x08 22. " [22] ,MSI interrupt 22 status" "Not detected,Detected" eventfld.long 0x08 21. " [21] ,MSI interrupt 21 status" "Not detected,Detected" eventfld.long 0x08 20. " [20] ,MSI interrupt 20 status" "Not detected,Detected" newline eventfld.long 0x08 19. " [19] ,MSI interrupt 19 status" "Not detected,Detected" eventfld.long 0x08 18. " [18] ,MSI interrupt 18 status" "Not detected,Detected" eventfld.long 0x08 17. " [17] ,MSI interrupt 17 status" "Not detected,Detected" eventfld.long 0x08 16. " [16] ,MSI interrupt 16 status" "Not detected,Detected" newline eventfld.long 0x08 15. " [15] ,MSI interrupt 15 status" "Not detected,Detected" eventfld.long 0x08 14. " [14] ,MSI interrupt 14 status" "Not detected,Detected" eventfld.long 0x08 13. " [13] ,MSI interrupt 13 status" "Not detected,Detected" eventfld.long 0x08 12. " [12] ,MSI interrupt 12 status" "Not detected,Detected" newline eventfld.long 0x08 11. " [11] ,MSI interrupt 11 status" "Not detected,Detected" eventfld.long 0x08 10. " [10] ,MSI interrupt 10 status" "Not detected,Detected" eventfld.long 0x08 9. " [9] ,MSI interrupt 9 status" "Not detected,Detected" eventfld.long 0x08 8. " [8] ,MSI interrupt 8 status" "Not detected,Detected" newline eventfld.long 0x08 7. " [7] ,MSI interrupt 7 status" "Not detected,Detected" eventfld.long 0x08 6. " [6] ,MSI interrupt 6 status" "Not detected,Detected" eventfld.long 0x08 5. " [5] ,MSI interrupt 5 status" "Not detected,Detected" eventfld.long 0x08 4. " [4] ,MSI interrupt 4 status" "Not detected,Detected" newline eventfld.long 0x08 3. " [3] ,MSI interrupt 3 status" "Not detected,Detected" eventfld.long 0x08 2. " [2] ,MSI interrupt 2 status" "Not detected,Detected" eventfld.long 0x08 1. " [1] ,MSI interrupt 1 status" "Not detected,Detected" eventfld.long 0x08 0. " [0] ,MSI interrupt 0 status" "Not detected,Detected" newline width 39. group.long 0x888++0x07 line.long 0x00 "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register" line.long 0x04 "CLOCK_GATING_CTRL_OFF,RADM Clock Gating Enable Control Register" bitfld.long 0x04 0. " RADM_CLK_GATING_EN ,Enable RADM clock gating feature" "Disabled,Enabled" group.long 0x8B4++0x27 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" line.long 0x04 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register" bitfld.long 0x04 31. " PIPE_LOOPBACK ,PIPE loopback enable" "Disabled,Enabled" line.long 0x08 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x08 5. " ARI_DEVICE_NUMBER ,Enables use of the device ID" "Disabled,Enabled" bitfld.long 0x08 3. " SIMPLIFIED_REPLAY_TIMER ,Enables simplified replay timer" "Disabled,Enabled" newline bitfld.long 0x08 2. " UR_CA_MASK_4_TRGT1 ,Suppresses error logging" "No effect,Suppressed" bitfld.long 0x08 1. " DEFAULT_TARGET ,Default target" "Drop,Forward" newline bitfld.long 0x08 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" line.long 0x0C "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-Lane Control Register" bitfld.long 0x0C 7. " UPCONFIGURE_SUPPORT ,Upconfigure support" "No support,Support" bitfld.long 0x0C 6. " DIRECT_LINK_WIDTH_CHANGE ,Directed link width change" "0,1" newline bitfld.long 0x0C 0.--5. " TARGET_LINK_WIDTH ,Target link width" "No start,X1,X2,,X4,,,,X8,,,,,,,,X16,,,,,,,,,,,,,,,,X32,?..." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register" bitfld.long 0x10 10. " L1_CLK_SEL ,L1 clock control bit" "Requested,Not requested" bitfld.long 0x10 9. " L1_NOWAIT_P1 ,L1 entry control bit" "Wait,No wait" newline bitfld.long 0x10 8. " L1SUB_EXIT_MODE ,L1 exit control" "Wait,Exit" hexmask.long.byte 0x10 0.--6. 1. " RXSTANDBY_CONTROL ,RX standby control" line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control Register" eventfld.long 0x14 31. " DELETE_EN ,Delete enable" "Disabled,Enabled" hexmask.long 0x14 0.--30. 1. " LOOK_UP_ID ,Selects one entry to delete of the TRGT_CPL_LUT" line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register" bitfld.long 0x18 0. " AUTO_FLUSH_EN ,Enables automatic flushing" "Disabled,Enabled" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register" bitfld.long 0x1C 15. " AMBA_ERROR_RESPONSE_MAP[UR] ,AXI slave response error map - unsupported request" "DECERR,SLVERR" newline bitfld.long 0x1C 14. " AMBA_ERROR_RESPONSE_MAP[CRS] ,AXI slave response error map - configuration retry status" "DECERR,SLVERR" bitfld.long 0x1C 13. " AMBA_ERROR_RESPONSE_MAP[CA] ,AXI slave response error map - completer abort" "DECERR,SLVERR" newline bitfld.long 0x1C 10. " AMBA_ERROR_RESPONSE_MAP[CT] ,AXI slave response error map - complete timeout" "DECERR,SLVERR" newline bitfld.long 0x1C 3.--4. " AMBA_ERROR_RESPONSE_CRS ,CRS slave error response mapping" "OKAY,FFFF_FFFF all,FFFF_0001 vendor / FFFF_FFFF others,SLVERR/DECERR" newline bitfld.long 0x1C 2. " AMBA_ERROR_RESPONSE_VENDORID ,Vendor ID non-existent slave error response mapping" "OKAY,ERROR AXI / (SLVERR/DECERR)" bitfld.long 0x1C 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "OKAY,ERROR / (SLVERR/DECERR)" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register" bitfld.long 0x20 8. " LINK_TIMEOUT_ENABLE_DEFAULT ,Disable flush" "No,Yes" hexmask.long.byte 0x20 0.--7. 1. " LINK_TIMEOUT_PERIOD_DEFAULT ,Timeout value (ms)" line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x24 7. " AX_MSTR_ZEROLREAD_FW ,AXI master zero length read forward to the application" "Terminated,Forwarded" bitfld.long 0x24 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B last,AW last,W last,?..." newline bitfld.long 0x24 1. " AX_SNP_EN ,AXI serialize non-posted requests enable" "Disabled,Enabled" group.long 0x8E0++0x0B line.long 0x00 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type for the lower and upper parts of the address space" "L:Periph UP:Mem,L:Mem UP:Periph" line.long 0x04 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" line.long 0x08 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" bitfld.long 0x08 27.--30. " CFG_MSTR_AWCACHE_VALUE ,Master write CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19.--22. " CFG_MSTR_ARCACHE_VALUE ,Master read CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 11.--14. " CFG_MSTR_AWCACHE_MODE ,Master write CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3.--6. " CFG_MSTR_ARCACHE_MODE ,Master read CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8F0++0x07 line.long 0x00 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 Bits Of The Programmable AXI Address Where Messages Coming From Wire Are Mapped To" hexmask.long.tbyte 0x00 12.--31. 0x10 " CFG_AXIMSTR_MSG_ADDR_LOW ,Lower 20 bits of the programmable AXI address for messages" line.long 0x04 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 Bits Of The Programmable AXI Address Where Messages Coming From Wire Are Mapped To" rgroup.long 0x8F8++0x07 line.long 0x00 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number" line.long 0x04 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type" group.long 0xB40++0x07 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The aux_clk frequency in MHz" line.long 0x04 "L1_SUBSTATES_OFF,L1 Substates Timing Register" bitfld.long 0x04 6.--7. " L1SUB_T_PCLKACK ,Max delay" "0 us,1 us,2 us,3 us" bitfld.long 0x04 2.--5. " L1SUB_T_L1_2 ,Duration of L1.2" "0 us,1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us" newline bitfld.long 0x04 0.--1. " L1SUB_T_POWER_OFF ,Duration of L1.2.entry" "0 us,1 us,2 us,3 us" base ad:0x33800000+0x80000000 group.long 0x0++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register 0" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register 0" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" newline bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Not inhibited,Inhibited" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not serialized,Serialized" newline bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "No bypass,Bypass" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" newline hexmask.long.byte 0x04 8.--15. 1. " TAG ,Substituted TAG field" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register 0" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register 0" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register 0" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Lower Target Address Register 0" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register 0" group.long (0x0+0x100)++0x17 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register 0" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register 0" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" newline bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode" newline bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" newline bitfld.long 0x04 27. " FUZZY_TYPE_MATCH_CODE ,Fuzzy type match mode" "No match mode,Match mode" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter,Unsupported request (UR),Completer abort (CA),?..." newline bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,Message code match enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " ATTR_MATCH_EN ,ATTR match enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "No match mode,Match mode" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register 0" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register 0" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register 0" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Lower Target Address Register 0" hexmask.long.word 0x14 16.--31. 0x01 " LWR_TARGET_RW ,Forms MSB's of the lower target part of the new address of the translated region" hexmask.long.word 0x14 0.--15. 0x01 " LWR_TARGET_HW ,Forms the LSB's of the lower target part of the new address of the translated region" group.long 0x200++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,IATU Region Control 1 Register 1" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,IATU Region Control 2 Register 1" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" newline bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Not inhibited,Inhibited" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not serialized,Serialized" newline bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "No bypass,Bypass" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" newline hexmask.long.byte 0x04 8.--15. 1. " TAG ,Substituted TAG field" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,IATU Lower Base Address Register 1" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,IATU Upper Base Address Register 1" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,IATU Limit Address Register 1" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,IATU Lower Target Address Register 1" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,IATU Upper Target Address Register 1" group.long (0x200+0x100)++0x17 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_1,IATU Region Control 1 Register 1" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_1,IATU Region Control 2 Register 1" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" newline bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode" newline bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" newline bitfld.long 0x04 27. " FUZZY_TYPE_MATCH_CODE ,Fuzzy type match mode" "No match mode,Match mode" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter,Unsupported request (UR),Completer abort (CA),?..." newline bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,Message code match enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " ATTR_MATCH_EN ,ATTR match enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "No match mode,Match mode" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,IATU Lower Base Address Register 1" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,IATU Upper Base Address Register 1" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,IATU Limit Address Register 1" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,IATU Lower Target Address Register 1" hexmask.long.word 0x14 16.--31. 0x01 " LWR_TARGET_RW ,Forms MSB's of the lower target part of the new address of the translated region" hexmask.long.word 0x14 0.--15. 0x01 " LWR_TARGET_HW ,Forms the LSB's of the lower target part of the new address of the translated region" group.long 0x400++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,IATU Region Control 1 Register 2" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,IATU Region Control 2 Register 2" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" newline bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Not inhibited,Inhibited" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not serialized,Serialized" newline bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "No bypass,Bypass" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" newline hexmask.long.byte 0x04 8.--15. 1. " TAG ,Substituted TAG field" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,IATU Lower Base Address Register 2" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,IATU Upper Base Address Register 2" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,IATU Limit Address Register 2" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,IATU Lower Target Address Register 2" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,IATU Upper Target Address Register 2" group.long (0x400+0x100)++0x17 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_2,IATU Region Control 1 Register 2" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_2,IATU Region Control 2 Register 2" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" newline bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode" newline bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" newline bitfld.long 0x04 27. " FUZZY_TYPE_MATCH_CODE ,Fuzzy type match mode" "No match mode,Match mode" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter,Unsupported request (UR),Completer abort (CA),?..." newline bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,Message code match enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " ATTR_MATCH_EN ,ATTR match enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "No match mode,Match mode" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,IATU Lower Base Address Register 2" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,IATU Upper Base Address Register 2" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,IATU Limit Address Register 2" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,IATU Lower Target Address Register 2" hexmask.long.word 0x14 16.--31. 0x01 " LWR_TARGET_RW ,Forms MSB's of the lower target part of the new address of the translated region" hexmask.long.word 0x14 0.--15. 0x01 " LWR_TARGET_HW ,Forms the LSB's of the lower target part of the new address of the translated region" group.long 0x600++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,IATU Region Control 1 Register 3" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,IATU Region Control 2 Register 3" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" newline bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" bitfld.long 0x04 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Not inhibited,Inhibited" bitfld.long 0x04 20. " SNP ,Serialize non-posted requests" "Not serialized,Serialized" newline bitfld.long 0x04 19. " FUNC_BYPASS ,Function number translation bypass" "No bypass,Bypass" bitfld.long 0x04 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" newline hexmask.long.byte 0x04 8.--15. 1. " TAG ,Substituted TAG field" hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,IATU Lower Base Address Register 3" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,IATU Upper Base Address Register 3" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,IATU Limit Address Register 3" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,IATU Lower Target Address Register 3" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,IATU Upper Target Address Register 3" group.long (0x600+0x100)++0x17 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_3,IATU Region Control 1 Register 3" bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "Not increased,Increased" newline bitfld.long 0x00 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x00 8. " TD ,TD" "0,1" newline bitfld.long 0x00 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_3,IATU Region Control 2 Register 3" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" newline bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID match mode,BAR/Accept/Vendor ID match mode" newline bitfld.long 0x04 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "No shift mode,Shift mode" newline bitfld.long 0x04 27. " FUZZY_TYPE_MATCH_CODE ,Fuzzy type match mode" "No match mode,Match mode" bitfld.long 0x04 24.--25. " RESPONSE_CODE ,Response code" "Normal RADM filter,Unsupported request (UR),Completer abort (CA),?..." newline bitfld.long 0x04 23. " SINGLE_ADDR_LOC_TRANS_EN ,Single address location translate enable" "Disabled,Enabled" bitfld.long 0x04 21. " MSG_CODE_MATCH_EN ,Message code match enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 16. " ATTR_MATCH_EN ,ATTR match enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TD_MATCH_EN ,TD match enable" "Disabled,Enabled" bitfld.long 0x04 14. " TC_MATCH_EN ,TC match enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " MSG_TYPE_MATCH_MODE ,Massage type match mode" "No match mode,Match mode" bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,MSG TLPs (message code)" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,IATU Lower Base Address Register 3" hexmask.long.word 0x08 16.--31. 0x01 " LWR_BASE_RW ,Upper bits of the start address" hexmask.long.word 0x08 0.--15. 0x01 " LWR_BASE_HW ,Lower bits of the start address" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,IATU Upper Base Address Register 3" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,IATU Limit Address Register 3" hexmask.long.word 0x10 16.--31. 0x01 " LIMIT_ADDR_RW ,Upper bits of the end address" hexmask.long.word 0x10 0.--15. 0x01 " LIMIT_ADDR_HW ,Lower bits of the end address" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,IATU Lower Target Address Register 3" hexmask.long.word 0x14 16.--31. 0x01 " LWR_TARGET_RW ,Forms MSB's of the lower target part of the new address of the translated region" hexmask.long.word 0x14 0.--15. 0x01 " LWR_TARGET_HW ,Forms the LSB's of the lower target part of the new address of the translated region" base ad:0x33800000+0x80080000 group.long 0x00++0x03 line.long 0x00 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme For TRGT1 Interface" bitfld.long 0x00 9.--11. " RDBUFF_TRGT_WEIGHT ,DMA read channel MWr requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " RD_CTRL_TRGT_WEIGHT ,DMA read channel MRd requests" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " WR_CTRL_TRGT_WEIGHT ,DMA write channel MRd requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " RTRGT1_WEIGHT ,Non-DMA RX requests" "0,1,2,3,4,5,6,7" group.long 0x08++0x0B line.long 0x00 "DMA_CTRL_OFF,DMA Number Of Channels Register" bitfld.long 0x00 25. " DIS_C2W_CAC_HE_RD ,Disable DMA read channels" "No,Yes" bitfld.long 0x00 24. " DIS_C2W_CAC_HE_WR ,Disable DMA write channels" "No,Yes" newline bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register" bitfld.long 0x04 0. " DMA_WRITE_ENGINE ,DMA write engine enable" "Disabled,Enabled" line.long 0x08 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register" bitfld.long 0x08 31. " WR_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x08 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "0,1,2,3,4,5,6,7" group.long 0x18++0x07 line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " WRITE_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " WRITE_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " WRITE_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " WRITE_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " WRITE_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " WRITE_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 5.--9. " WRITE_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " WRITE_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x07 line.long 0x00 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register" bitfld.long 0x00 0. " DMA_READ_ENGINE ,DMA read engine enable" "Disabled,Enabled" line.long 0x04 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register" bitfld.long 0x04 31. " RD_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x04 0.--2. " RD_DOORBELL_NUM ,Doorbell number" "0,1,2,3,4,5,6,7" group.long 0x38++0x07 line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " READ_CHANNEL3_WEIGHT ,Channel 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " READ_CHANNEL2_WEIGHT ,Channel 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " READ_CHANNEL1_WEIGHT ,Channel 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " READ_CHANNEL0_WEIGHT ,Channel 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " READ_CHANNEL7_WEIGHT ,Channel 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10.--14. " READ_CHANNEL6_WEIGHT ,Channel 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 5.--9. " READ_CHANNEL5_WEIGHT ,Channel 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " READ_CHANNEL4_WEIGHT ,Channel 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x03 line.long 0x00 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register" bitfld.long 0x00 23. " WR_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" newline bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" newline bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" newline bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" newline bitfld.long 0x00 7. " WR_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not done,Done" newline bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not done,Done" newline bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not done,Done" newline bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not done,Done" group.long 0x54++0x07 line.long 0x00 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register" bitfld.long 0x00 16. " WR_ABORT_INT_MASK ,Abort interrupt mask for channel 0" "Not masked,Masked" bitfld.long 0x00 0. " WR_DONE_INT_MASK ,Done interrupt mask for channel 0" "Not masked,Masked" line.long 0x04 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register" eventfld.long 0x04 16. " WR_ABORT_INT_CLEAR ,Abort interrupt clear for channel 0" "No effect,Clear" eventfld.long 0x04 0. " WR_DONE_INT_CLEAR ,Done interrupt clear for channel 0" "No effect,Clear" rgroup.long 0x5C++0x03 line.long 0x00 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" bitfld.long 0x00 23. " LINKLIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "No error,Error" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "No error,Error" newline bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "No error,Error" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "No error,Error" newline bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "No error,Error" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "No error,Error" newline bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "No error,Error" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "No error,Error" newline bitfld.long 0x00 7. " APP_READ_ERR_DETECT[7] ,Application read error detected for channel 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Application read error detected for channel 6" "No error,Error" newline bitfld.long 0x00 5. " [5] ,Application read error detected for channel 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Application read error detected for channel 4" "No error,Error" newline bitfld.long 0x00 3. " [3] ,Application read error detected for channel 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Application read error detected for channel 2" "No error,Error" newline bitfld.long 0x00 1. " [1] ,Application read error detected for channel 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Application read error detected for channel 0" "No error,Error" group.long 0x60++0x1F line.long 0x00 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register" line.long 0x04 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register" line.long 0x08 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register" line.long 0x0C "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 And 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " WR_CHANNEL_1_DATA ,Write channel 1 data" hexmask.long.word 0x10 0.--15. 1. " WR_CHANNEL_0_DATA ,Write channel 0 data" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 And 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " WR_CHANNEL_3_DATA ,Write channel 3 data" hexmask.long.word 0x14 0.--15. 1. " WR_CHANNEL_2_DATA ,Write channel 2 data" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 And 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " WR_CHANNEL_5_DATA ,Write channel 5 data" hexmask.long.word 0x18 0.--15. 1. " WR_CHANNEL_4_DATA ,Write channel 4 data" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 And 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " WR_CHANNEL_7_DATA ,Write channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " WR_CHANNEL_6_DATA ,Write channel 6 data" if (((per.l(ad:0x33800000+0x80080200))&0x200)==0x200) group.long 0x90++0x03 line.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" bitfld.long 0x00 16. " WR_CHANNEL_LLLAIE ,Write channel LL local abort interrupt enable for channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " WR_CHANNEL_LLRAIE ,Write channel LL remote abort interrupt enable for channel 0" "Disabled,Enabled" else hgroup.long 0x90++0x03 hide.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" endif group.long 0xA0++0x03 line.long 0x00 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register" bitfld.long 0x00 23. " RD_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" newline bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" newline bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" newline bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" newline bitfld.long 0x00 7. " RD_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not done,Done" newline bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not done,Done" newline bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not done,Done" newline bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not done,Done" group.long 0xA8++0x03 line.long 0x00 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register" bitfld.long 0x00 16. " RD_ABORT_INT_MASK ,Abort interrupt mask for channel 0" "Not masked,Masked" bitfld.long 0x00 0. " RD_DONE_INT_MASK ,Done interrupt mask for channel 0" "Not masked,Masked" wgroup.long 0xAC++0x03 line.long 0x00 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register" bitfld.long 0x00 23. " RD_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "No effect,Clear" bitfld.long 0x00 22. " [6] ,Abort interrupt clear for channel 6" "No effect,Clear" newline bitfld.long 0x00 21. " [5] ,Abort interrupt clear for channel 5" "No effect,Clear" bitfld.long 0x00 20. " [4] ,Abort interrupt clear for channel 4" "No effect,Clear" newline bitfld.long 0x00 19. " [3] ,Abort interrupt clear for channel 3" "No effect,Clear" bitfld.long 0x00 18. " [2] ,Abort interrupt clear for channel 2" "No effect,Clear" newline bitfld.long 0x00 17. " [1] ,Abort interrupt clear for channel 1" "No effect,Clear" bitfld.long 0x00 16. " [0] ,Abort interrupt clear for channel 0" "No effect,Clear" newline bitfld.long 0x00 7. " RD_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Done interrupt clear for channel 6" "No effect,Clear" newline bitfld.long 0x00 5. " [5] ,Done interrupt clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Done interrupt clear for channel 4" "No effect,Clear" newline bitfld.long 0x00 3. " [3] ,Done interrupt clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Done interrupt clear for channel 2" "No effect,Clear" newline bitfld.long 0x00 1. " [1] ,Done interrupt clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Done interrupt clear for channel 0" "No effect,Clear" rgroup.long 0xB4++0x07 line.long 0x00 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register" bitfld.long 0x00 23. " LINK_LIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "No error,Error" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "No error,Error" newline bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "No error,Error" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "No error,Error" newline bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "No error,Error" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "No error,Error" newline bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "No error,Error" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "No error,Error" newline bitfld.long 0x00 7. " APP_WR_ERR_DETECT[7] ,Application write error detected for channel 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Application write error detected for channel 6" "No error,Error" newline bitfld.long 0x00 5. " [5] ,Application write error detected for channel 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Application write error detected for channel 4" "No error,Error" newline bitfld.long 0x00 3. " [3] ,Application write error detected for channel 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Application write error detected for channel 2" "No error,Error" newline bitfld.long 0x00 1. " [1] ,Application write error detected for channel 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Application write error detected for channel 0" "No error,Error" line.long 0x04 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register" bitfld.long 0x04 31. " DATA_POISIONING[7] ,Data poisoning for channel 7" "No error,Error" bitfld.long 0x04 30. " [6] ,Data poisoning for channel 6" "No error,Error" newline bitfld.long 0x04 29. " [5] ,Data poisoning for channel 5" "No error,Error" bitfld.long 0x04 28. " [4] ,Data poisoning for channel 4" "No error,Error" newline bitfld.long 0x04 27. " [3] ,Data poisoning for channel 3" "No error,Error" bitfld.long 0x04 26. " [2] ,Data poisoning for channel 2" "No error,Error" newline bitfld.long 0x04 25. " [1] ,Data poisoning for channel 1" "No error,Error" bitfld.long 0x04 24. " [0] ,Data poisoning for channel 0" "No error,Error" newline bitfld.long 0x04 23. " CPL_TIMEOUT[7] ,Completion time out for channel 7" "No error,Error" bitfld.long 0x04 22. " [6] ,Completion time out for channel 6" "No error,Error" newline bitfld.long 0x04 21. " [5] ,Completion time out for channel 5" "No error,Error" bitfld.long 0x04 20. " [4] ,Completion time out for channel 4" "No error,Error" newline bitfld.long 0x04 19. " [3] ,Completion time out for channel 3" "No error,Error" bitfld.long 0x04 18. " [2] ,Completion time out for channel 2" "No error,Error" newline bitfld.long 0x04 17. " [1] ,Completion time out for channel 1" "No error,Error" bitfld.long 0x04 16. " [0] ,Completion time out for channel 0" "No error,Error" newline bitfld.long 0x04 15. " CPL_ABORT[7] ,Completer abort for channel 7" "No error,Error" bitfld.long 0x04 14. " [6] ,Completer abort for channel 6" "No error,Error" newline bitfld.long 0x04 13. " [5] ,Completer abort for channel 5" "No error,Error" bitfld.long 0x04 12. " [4] ,Completer abort for channel 4" "No error,Error" newline bitfld.long 0x04 11. " [3] ,Completer abort for channel 3" "No error,Error" bitfld.long 0x04 10. " [2] ,Completer abort for channel 2" "No error,Error" newline bitfld.long 0x04 9. " [1] ,Completer abort for channel 1" "No error,Error" bitfld.long 0x04 8. " [0] ,Completer abort for channel 0" "No error,Error" newline bitfld.long 0x04 7. " UNSUPPORTED_REQ[7] ,Unsupported request for channel 7" "No error,Error" bitfld.long 0x04 6. " [6] ,Unsupported request for channel 6" "No error,Error" newline bitfld.long 0x04 5. " [5] ,Unsupported request for channel 5" "No error,Error" bitfld.long 0x04 4. " [4] ,Unsupported request for channel 4" "No error,Error" newline bitfld.long 0x04 3. " [3] ,Unsupported request for channel 3" "No error,Error" bitfld.long 0x04 2. " [2] ,Unsupported request for channel 2" "No error,Error" newline bitfld.long 0x04 1. " [1] ,Unsupported request for channel 1" "No error,Error" bitfld.long 0x04 0. " [0] ,Unsupported request for channel 0" "No error,Error" if (((per.l(ad:0x33800000+0x80080300))&0x200)==0x200) group.long 0xC4++0x03 line.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" bitfld.long 0x00 16. " RD_CHANNEL_LLLAIE ,Read channel LL local abort interrupt enable for channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " RD_CHANNEL_LLRAIE ,Read channel LL remote abort interrupt enable for channel 0" "Disabled,Enabled" else hgroup.long 0xC4++0x03 hide.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" endif group.long 0xCC++0x1F line.long 0x00 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register" line.long 0x04 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register" line.long 0x08 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register" line.long 0x0C "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 And 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " RD_CHANNEL_1_DATA ,Read channel 1 data" hexmask.long.word 0x10 0.--15. 1. " RD_CHANNEL_0_DATA ,Read channel 0 data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 And 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " RD_CHANNEL_3_DATA ,Read channel 3 data" hexmask.long.word 0x14 0.--15. 1. " RD_CHANNEL_2_DATA ,Read channel 2 data" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 And 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " RD_CHANNEL_5_DATA ,Read channel 5 data" hexmask.long.word 0x18 0.--15. 1. " RD_CHANNEL_4_DATA ,Read channel 4 data" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 And 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " RD_CHANNEL_7_DATA ,Read channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " RD_CHANNEL_6_DATA ,Read channel 6 data" if (((per.l(ad:0x33800000+0x80080200))&0x200)==0x200) group.long 0x200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" newline rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" newline bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x200++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" newline rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x208++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" if (((per.l(ad:0x33800000+0x80080300))&0x200)==0x200) group.long 0x300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_RDCH_0,DMA Read Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" newline rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" newline bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x300++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_RDCH_0,DMA Read Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" newline rbitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x308++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_RDCH_0,DMA Read Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_RDCH_0,DMA Read SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_RDCH_0,DMA Read SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_RDCH_0,DMA Read DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_0,DMA Read DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_0,DMA Read Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_0,DMA Read Linked List Pointer High Register" width 0x0B tree.end endif sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) tree.open "PCIe_PHY (PCI Express PHY)" tree "PCIE_PHY_CMN (PHY Register for CMN Block)" base ad:0x306D0000 width 7. group.long 0x04++0x07 line.long 0x00 "REG01,Impedance Calibration Register" bitfld.long 0x00 4.--7. " RCODE ,Manual RX impedance control" "Large,,,,,,,,,,,,,,,Small" bitfld.long 0x00 0.--3. " TCODE ,Manual TX impedance control" "Large,,,,,,,,,,,,,,,Small" line.long 0x04 "REG02,REG02" bitfld.long 0x04 4.--7. " PDIV ,PLL pre-divider ratio control" "GND,1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/11,/11,/11,/11" bitfld.long 0x04 0. " FORCE ,Manual impedance control enable" "Disabled,Enabled" group.long 0x12++0x07 line.long 0x00 "REG03,REG03" bitfld.long 0x00 0.--3. " CTRL_CP ,PLL bias control" ",Default for SATA,,Default for PCIE,?..." line.long 0x04 "REG04,REG04" bitfld.long 0x04 4.--7. " CTRL_R ,PLL loop filter res control" ",,,Default for SATA,,,,,,,,Default for PCIE,?..." bitfld.long 0x04 1.--3. " CTRL_C ,PLL loop filter cap control" ",,Default for SATA,,Default for PCIE,?..." group.long 0x20++0x0F line.long 0x00 "REG05,REG05" bitfld.long 0x00 7. " CKFB_MON_EN ,PLL clock monitoring enable" "Disabled,Enabled" bitfld.long 0x00 6. " DCC_FB_EN ,PLL DCC feedback enable" "Disabled,Enabled" line.long 0x04 "REG06,REG06" bitfld.long 0x04 7. " MDIV_HS ,PLL main-divider ratio control" "/1,/2" bitfld.long 0x04 4. " CK100M_EN ,CK100M enable" "Disabled,Enabled" bitfld.long 0x04 0.--2. " SD_DIV ,Sigma delta CLK control" ",,,,Default for PCIE,?..." line.long 0x08 "REG07,REG07" hexmask.long.byte 0x08 0.--7. 1. " MDIV_MS ,PLL main-divider ratio control" line.long 0x0C "REG0B,REG0B" hexmask.long.byte 0x0C 0.--6. 1. " SSC ,SSC amount control" group.long 0x32++0x07 line.long 0x00 "REG08,REG08" rbitfld.long 0x00 1.--4. " PI_STR ,PI buffer strength control" ",,,Default for PCIE,,,,,,,,,,,,Default for SATA" bitfld.long 0x00 0. " PI_EN ,PI enable" "Disabled,Enabled" line.long 0x04 "REG09,REG09" bitfld.long 0x04 5.--6. " SSC_CNTL ,SSC control" "1,2,4,8" group.long 0x40++0x03 line.long 0x00 "REG11,REG11" hexmask.long.byte 0x00 0.--7. 1. " PREF ,PLL reference control" group.long 0x60++0x0B line.long 0x00 "REG15,REG15" bitfld.long 0x00 7. " PHY_CMNPD_EN ,CMN sub-block PD control" "Disabled,Enabled" bitfld.long 0x00 5.--6. " PD_SCMN ,CMN sub-block powerdown" "Common block enabled,Fine control,Fine control,Fine control" bitfld.long 0x00 4. " MON_EN ,Clock monitoring enable" "Disabled,Enabled" line.long 0x04 "REG16,REG16" bitfld.long 0x04 2.--3. " PHY_SSC_EN ,SSC enable" "Controlled by port,Controlled by port,Disabled by register,Enabled by register" line.long 0x08 "REG17,REG17" bitfld.long 0x08 7. " TG_CODE_EN ,PLL frequency control enable" "Disabled,Enabled" bitfld.long 0x08 4. " RDIV_EN ,PLL ref-divider enable" "Disabled,Enabled" bitfld.long 0x08 0.--3. " RDIV ,PLL ref-divider ratio control" "< 1/2,< 1/2,1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2,> 1/2" group.long 0x72++0x07 line.long 0x00 "REG18,REG18" hexmask.long.byte 0x00 0.--7. 1. " TG_CODE ,PLL frequency control" line.long 0x04 "REG19,REG19" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) bitfld.long 0x04 4.--7. " RTOL ,PLL tolerance control" ",,,,Default,?..." else bitfld.long 0x04 4.--7. " RTOL ,PLL tolerance control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x04 3. " PD_CMN ,CMN all block powerdown" "Disabled,Enabled" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) bitfld.long 0x04 0.--2. " TOL ,PLL tolerance control" ",,,Default,?..." else bitfld.long 0x04 0.--2. " TOL ,PLL tolerance control" "0,1,2,3,4,5,6,7" endif group.long 0x80++0x03 line.long 0x00 "REG1A,REG1A" hexmask.long.byte 0x00 0.--7. 1. " CMNRST ,CMN reset control" width 0x0B tree.end tree "PCIE_PHY_TRSV (PHY Register for Transceiver Block)" base ad:0x306D0000 width 7. group.long 0x84++0x07 line.long 0x00 "REG21,REG21" bitfld.long 0x00 7. " DRVR_PDH ,TX driver option" "Default for PCIE,Reduce power consumption" bitfld.long 0x00 0.--4. " EMP_LVL ,TX de-emphasis level control" "None,,,,Default for SATA,,,,,,,,,,,,,,,,3.5 dB,,,,,,,,,,-6 dB,Max" line.long 0x04 "REG22,REG22" bitfld.long 0x04 0.--5. " DRV_LVL ,TX differential output (PCIE_TX_P/PCIE_TX_N) amplitude control" "Minimum swing,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Default for SATA,,,,,,,,,,Default for PCIE,,,,,,,,,,,,,,,,,,,,,Maximum swing" group.long 0x96++0x03 line.long 0x00 "REG24,REG24" bitfld.long 0x00 7. " RX_SS_PD ,RX sense powerdown" "Disabled,Enabled" bitfld.long 0x00 6. " RX_EQS ,RX equalizer select" "0,1" sif cpuis("IMX8DX*")||cpuis("IMX8QXP*") bitfld.long 0x00 4.--5. " RX_SS ,RX sense control" "Default,?..." else bitfld.long 0x00 4.--5. " RX_SS ,RX sense control" "0,1,2,3" textfld " " endif bitfld.long 0x00 3. " RX_EQ_SEL ,RX equalizer select enable" "Disabled,Enabled" group.long 0xAC++0x03 line.long 0x00 "REG2B,REG2B" bitfld.long 0x00 0.--3. " RXCDR ,RX CDR BW control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE8++0x03 line.long 0x00 "REG3A,REG3A" bitfld.long 0x00 3. " COMDET_EN ,Comma detection enable" "Disabled,Enabled" bitfld.long 0x00 1. " RDIMODE ,RX bitwidth select" "20-bit mode,40-bit mode" bitfld.long 0x00 0. " TDIMODE ,TX bitwidth select" "20-bit mode,40-bit mode" group.long 0xF8++0x03 line.long 0x00 "REG3E,REG3E" bitfld.long 0x00 0.--3. " DET_CNT ,RX detection control" "No detection,,,,Four K28.5,?..." group.long 0x100++0x07 line.long 0x00 "REG25,REG25" sif cpuis("IMX8DX*")||cpuis("IMX8QXP*") bitfld.long 0x00 4.--7. " RXEQ ,RX equalizer control" ",,,,Default,?..." bitfld.long 0x00 0.--2. " RXEQS ,RX equalizer setting" ",,,,Default,?..." else bitfld.long 0x00 4.--7. " RXEQ ,RX equalizer control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " RXEQS ,RX equalizer setting" "0,1,2,3,4,5,6,7" endif line.long 0x04 "REG26,REG26" bitfld.long 0x04 4.--6. " SQTH ,RX squelch detect threshold control" "Min,,,Default,,,,Max" group.long 0x116++0x03 line.long 0x00 "REG29,REG29" hexmask.long.byte 0x00 0.--7. 1. " BIAS ,TRSV bias current control" group.long 0x124++0x03 line.long 0x00 "REG31,REG31" bitfld.long 0x00 7. " PD_TSV ,Transceiver block all powerdown enable" "Disabled,Enabled" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) hgroup.long 0x132++0x03 hide.long 0x00 "REG33,REG33" endif group.long 0x144++0x03 line.long 0x00 "REG36,REG36" bitfld.long 0x00 4.--5. " DRVR_CNT ,TX driver common mode control" "Default for SATA,,,Default for PCIE" bitfld.long 0x00 3. " TX_SWING ,TX driver control" "Full-swing,Half-swing" bitfld.long 0x00 0.--2. " SR_LVL ,TX slew-rate control" "~60pS,~90pS,~120pS,~150pS,Max,Max,Max,Max" sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) hgroup.long 0x148++0x03 hide.long 0x00 "REG37,REG37" endif group.long 0x152++0x07 line.long 0x00 "REG38,REG38" bitfld.long 0x00 5. " TX_INV ,TX inversion control" "Not inverted,Inverted" bitfld.long 0x00 4. " RX_INV ,RX inversion control" "Not inverted,Inverted" bitfld.long 0x00 3. " ADD_ALIGN ,Align primitive control" "Not added,Added" line.long 0x04 "REG39,REG39" bitfld.long 0x04 6.--7. " RD_ORD ,RX bit order control" "Not reversed,Bit reverse,Byte reverse,Bit & byte reverse" bitfld.long 0x04 4.--5. " TD_ORD ,TX bit order control" "Not reversed,Bit reverse,Byte reverse,Bit & byte reverse" group.long 0x160++0x03 line.long 0x00 "REG40,REG40" bitfld.long 0x00 7. " PHY_TRSV_EN ,TRSV sub-block PD control" "Disabled,Enabled" bitfld.long 0x00 6. " PD_TRAS[6] ,TRSV sub-block powerdown 6(RX Deserializer)" "Powered up,Powered down" bitfld.long 0x00 5. " [5] ,TRSV sub-block powerdown 5(TX serializer)" "Powered up,Powered down" newline bitfld.long 0x00 4. " [4] ,TRSV sub-block powerdown 4(RXAFE)" "Powered up,Powered down" bitfld.long 0x00 3. " [3] ,TRSV sub-block powerdown 3(TX DRVR)" "Powered up,Powered down" bitfld.long 0x00 2. " [2] ,TRSV sub-block powerdown 2(RX TERM)" "Powered up,Powered down" group.long 0x168++0x03 line.long 0x00 "REG42,REG42" hexmask.long.byte 0x00 0.--7. 1. " TRSVRST ,TRSV reset control" width 0x0B tree.end tree.end endif tree.open "USB (Universal Serial Bus Controller)" tree "USBNC (USB Non-Core)" base ad:0x30B10200 width 18. group.long 0x200++0x03 line.long 0x00 "OTG1_CTRL1,OTG1_CTRL1" rbitfld.long 0x00 31. " WIR ,Wake-up interrupt request" "Not requested,Requested" bitfld.long 0x00 29. " WKUP_DPDM_EN ,DPDM changes wakeup enable" "Disabled,Enabled" bitfld.long 0x00 17. " WKUP_VBUS_EN ,VBUS changes wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " WKUP_ID_EN ,Wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x00 15. " WKUP_SW ,Software force Wake-up" "Not forced,Forced" bitfld.long 0x00 14. " WKUP_SW_EN ,Software Wake-up enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WIE ,Wake-up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " PWR_POL ,Power polarity" "Low,High" textline " " bitfld.long 0x00 8. " OVER_CUR_POL ,Polarity of overcurrent" "High,Low" bitfld.long 0x00 7. " OVER_CUR_DIS ,Disable overcurrent detection" "No,Yes" if (((per.l(ad:0x30B10200+0x20240))&0x0C)==0x0C) group.long (0x200+0x04)++0x03 line.long 0x00 "OTG1_CTRL2,OTG1_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,FS transceiver,LS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 2. " AUTURESUME_EN ,Auto resume enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" else group.long (0x200+0x04)++0x03 line.long 0x00 "OTG1_CTRL2,OTG1_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,FS transceiver,LS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" endif group.long (0x200+0x30)++0x03 line.long 0x00 "OTG1_PHY_CFG1,PHY_CFG1" bitfld.long 0x00 31. " CHRGDET_MEGAMIX ,USB_OTG1_CHD_B output control" "CHRGDET,Forced low" bitfld.long 0x00 30. " TXPREEMPPULSETUNE0 ,HS transmitter Pre-Emphasis duration control" "Long,Short" bitfld.long 0x00 28.--29. " TXPREEMPAMPTUNE0 ,HS transmitter Pre-Emphasis current control" "Disabled,1x pre-emphasis,2x pre-emphasis,3x pre-emphasis" textline " " bitfld.long 0x00 26.--27. " TXRESTUNE0 ,USB source impedance adjustment" "Increased by 1.5 ohm,Default,Decreased by 2 ohm,Decreased by 4 ohm" bitfld.long 0x00 24.--25. " TXRISETUNE0 ,HS transmitter rise/fall time adjustment" "-10%,Default,+15%,+20%" bitfld.long 0x00 20.--23. " TXVREFTUNE0 ,HS DC voltage level adjustment" "-6%,-4%,-2%,Default,+2%,+4%,+6%,+8%,+10%,+12%,+14%,+16%,+18%,+20%,+22%,+24%" textline " " bitfld.long 0x00 16.--19. " TXFSLSTUNE0 ,Full speed/low speed source impedance adjustment" "+5%,+2.5%,,Default,,,,-2.5%,,,,,,,,-5%" bitfld.long 0x00 13.--14. " TXHSXVTUNE0 ,Transmitter High-Speed crossover adjustment" ",-15mv,+15mv,Default" bitfld.long 0x00 10.--12. " OTGTUNE0 ,VBUS valid threshold adjustment" "-6%,-4.5%,-3%,-1.5%,Default,+1.5%,+3%,+4.5%" textline " " bitfld.long 0x00 7.--9. " SQRXTUNE0 ,Squelch threshold adjustment" "+15%,+10%,+5%,Default,-5%,-10%,-15%,-20%" bitfld.long 0x00 4.--6. " COMPDISTUNE0 ,Disconnect threshold adjustment" "-6%,-4.5%,-3%,-1.5%,Default,+1.5%,+3%,+4.5%" bitfld.long 0x00 1.--3. " FSEL ,Reference clock frequency select" "9.6 MHz,10 MHz,12 MHz,19.2 MHz,20 MHz,24 MHz,,50 MHz" textline " " bitfld.long 0x00 0. " COMMONONN ,Common block Power-Down control" "Remained powered,Powered down" if (((per.l(ad:0x30B10200+0x20240)&0x08)==0x08)&&((per.l(ad:0x30B10200+0x20240)&0x04)==0x04)) group.long (0x200+0x34)++0x03 line.long 0x00 "OTG1_PHY_CFG2,PHY_CFG2" bitfld.long 0x00 16. " DRVVBUS0 ,VBUS valid comparator enable" "Disabled,Enabled" bitfld.long 0x00 14. " VBUSVLDEXTSEL0 ,External VBUS valid select" "Internal,External" textline " " bitfld.long 0x00 13. " ADPPRBENB0 ,ADP probe enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADPDISCHRG0 ,VBUS input ADP discharge enable" "Disabled,Enabled" bitfld.long 0x00 11. " ADPCHRG0 ,VBUS input ADP charge enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OTGDISABLE0 ,OTG block disable" "No,Yes" bitfld.long 0x00 9. " TXBITSTUFFENH0 ,High-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXBITSTUFFEN0 ,Low-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " LOOPBACKENB0 ,Loopback test enable" "Disabled,Enabled" bitfld.long 0x00 5. " SLEEPM0 ,Sleep mode assertion" "Sleep mode,Normal mode" bitfld.long 0x00 4. " ACAENB0 ,ACA USB_OTG*_ID pin resistance detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DCDENB ,Data contact detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " VDATSRCENB0 ,Enable the VD*_SRC voltage source" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VDATDETENB0 ,Battery charging attach / connect detection enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHRGSEL ,Determines which of USB_OTG*_DP / USB_OTG*_DN has the VD*_SRC voltage source and which has the ID*_SINK current sink" "USB_OTG*_DP & USB_OTG*_DN,USB_OTG*_DN & USB_OTG*_DP" else group.long (0x200+0x34)++0x03 line.long 0x00 "OTG1_PHY_CFG2,PHY_CFG2" bitfld.long 0x00 16. " DRVVBUS0 ,VBUS valid comparator enable" "Disabled,Enabled" bitfld.long 0x00 15. " VBUSVLDEXT ,External VBUS valid indicator" "Invalid,Valid" bitfld.long 0x00 14. " VBUSVLDEXTSEL0 ,External VBUS valid select" "Internal,External" textline " " bitfld.long 0x00 13. " ADPPRBENB0 ,ADP probe enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADPDISCHRG0 ,VBUS input ADP discharge enable" "Disabled,Enabled" bitfld.long 0x00 11. " ADPCHRG0 ,VBUS input ADP charge enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OTGDISABLE0 ,OTG block disable" "No,Yes" bitfld.long 0x00 9. " TXBITSTUFFENH0 ,High-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXBITSTUFFEN0 ,Low-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " LOOPBACKENB0 ,Loopback test enable" "Disabled,Enabled" bitfld.long 0x00 5. " SLEEPM0 ,Sleep mode assertion" "Sleep mode,Normal mode" bitfld.long 0x00 4. " ACAENB0 ,ACA USB_OTG*_ID pin resistance detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DCDENB ,Data contact detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " VDATSRCENB0 ,Enable the VD*_SRC voltage source" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VDATDETENB0 ,Battery charging attach / connect detection enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHRGSEL ,Determines which of USB_OTG*_DP / USB_OTG*_DN has the VD*_SRC voltage source and which has the ID*_SINK current sink" "USB_OTG*_DP & USB_OTG*_DN,USB_OTG*_DN & USB_OTG*_DP" endif textline " " rgroup.long (0x200+0x3C)++0x03 line.long 0x00 "OTG1_PHY_STATUS,USB OTG PHY Status Register" bitfld.long 0x00 31. " ADPSNS0 ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the ADP sensing voltage" "Below,Above" bitfld.long 0x00 30. " ADPPRB0 ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the ADP probing voltage" "Below,Above" textline " " bitfld.long 0x00 29. " CHRGDET ,Battery charger detection output" "VD*VDAT_REF" bitfld.long 0x00 28. " RIDFLOAT0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is floating" "<=rid_a(max),>=rid_float(min)" textline " " bitfld.long 0x00 27. " RIDGND0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is grounded" ">=rid_c(min),<=rid_gnd(max)" bitfld.long 0x00 26. " RIDA0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_A range" ">=rid_float(Min) & <=rid_b(Max),>=rid_a(Min) & <=rid_a(Max)" textline " " bitfld.long 0x00 25. " RIDB0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_B range" ">=rid_a(Min) & <=rid_c(Max),>=rid_b(Min) & <=rid_b(Max)" bitfld.long 0x00 24. " RIDC0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_C range" ">=rid_b(Min) & <=rid_gnd(Max),>=rid_c(Min) & <=rid_c(Max)" textline " " bitfld.long 0x00 5. " HOST_DISCONNECT ,Peripheral disconnect indicator" "Connected,Disconnected" bitfld.long 0x00 4. " ID_DIG ,Micro- or Mini- A/B plug indicator" "A plug,B plug" textline " " bitfld.long 0x00 3. " VBUS_VLD ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the VBUS valid threshold" "Below,Above" bitfld.long 0x00 2. " SESS_VLD ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the OTG device session valid threshold" "Below,Above" textline " " bitfld.long 0x00 0.--1. " LINE_STATE ,Line state indicator outputs from USB OTG PHY" "DP low & DN low,DP high & DN low,DP low & DN high,DP high & DN high" textline " " group.long (0x200+0x50)++0x07 line.long 0x00 "ADP_CFG1,ADP_CFG1" bitfld.long 0x00 23. " ADP_PRB_EN ,Set to enable the ADP probe sequence" "Disabled,Enabled" bitfld.long 0x00 22. " ADP_PRB_INT_EN ,ADP probe interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " ADP_SNS_INT_EN ,ADP sense interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TIMER_EN ,ADP timer test enable" "Disabled,Enabled" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " ADP_WAIT ,Delay between 2 ADP probe" line.long 0x04 "ADP_CFG2,ADP_CFG2" hexmask.long.byte 0x04 16.--23. 1. " ADP_DISCHG_TIME ,ADP discharge time" hexmask.long.byte 0x04 8.--15. 1. " ADP_CHRG_SWTIME ,ADP charge time assigned by software" bitfld.long 0x04 7. " ADP_CHRG_SWCMP ,HW uses ADP_CHRG_SWTIME to compare" "No,Yes" hexmask.long.byte 0x04 0.--6. 1. " ADP_CHRG_DELTA ,ADP charge time compare" rgroup.long (0x200+0x58)++0x03 line.long 0x00 "ADP_STATUS,USBNC_ADP_STATUS" bitfld.long 0x00 27. " ADP_PRB_INT ,ADP probe interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 26. " ADP_SNS_INT ,ADP sense interrupt status" "No interrupt,Interrupt" hexmask.long.tbyte 0x00 8.--25. 1. " ADP_CNT ,ADP internal 18-bit counter" hexmask.long.byte 0x00 0.--7. 1. " ADP_PRB_TIMR ,ADP probe time" textline " " group.long 0x10200++0x03 line.long 0x00 "OTG2_CTRL1,OTG2_CTRL1" rbitfld.long 0x00 31. " WIR ,Wake-up interrupt request" "Not requested,Requested" bitfld.long 0x00 29. " WKUP_DPDM_EN ,DPDM changes wakeup enable" "Disabled,Enabled" bitfld.long 0x00 17. " WKUP_VBUS_EN ,VBUS changes wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " WKUP_ID_EN ,Wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x00 15. " WKUP_SW ,Software force Wake-up" "Not forced,Forced" bitfld.long 0x00 14. " WKUP_SW_EN ,Software Wake-up enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WIE ,Wake-up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " PWR_POL ,Power polarity" "Low,High" textline " " bitfld.long 0x00 8. " OVER_CUR_POL ,Polarity of overcurrent" "High,Low" bitfld.long 0x00 7. " OVER_CUR_DIS ,Disable overcurrent detection" "No,Yes" if (((per.l(ad:0x30B10200+0x20240))&0x0C)==0x0C) group.long (0x10200+0x04)++0x03 line.long 0x00 "OTG2_CTRL2,OTG2_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,FS transceiver,LS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 2. " AUTURESUME_EN ,Auto resume enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" else group.long (0x10200+0x04)++0x03 line.long 0x00 "OTG2_CTRL2,OTG2_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,FS transceiver,LS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" endif group.long (0x10200+0x30)++0x03 line.long 0x00 "OTG2_PHY_CFG1,PHY_CFG1" bitfld.long 0x00 31. " CHRGDET_MEGAMIX ,USB_OTG1_CHD_B output control" "CHRGDET,Forced low" bitfld.long 0x00 30. " TXPREEMPPULSETUNE0 ,HS transmitter Pre-Emphasis duration control" "Long,Short" bitfld.long 0x00 28.--29. " TXPREEMPAMPTUNE0 ,HS transmitter Pre-Emphasis current control" "Disabled,1x pre-emphasis,2x pre-emphasis,3x pre-emphasis" textline " " bitfld.long 0x00 26.--27. " TXRESTUNE0 ,USB source impedance adjustment" "Increased by 1.5 ohm,Default,Decreased by 2 ohm,Decreased by 4 ohm" bitfld.long 0x00 24.--25. " TXRISETUNE0 ,HS transmitter rise/fall time adjustment" "-10%,Default,+15%,+20%" bitfld.long 0x00 20.--23. " TXVREFTUNE0 ,HS DC voltage level adjustment" "-6%,-4%,-2%,Default,+2%,+4%,+6%,+8%,+10%,+12%,+14%,+16%,+18%,+20%,+22%,+24%" textline " " bitfld.long 0x00 16.--19. " TXFSLSTUNE0 ,Full speed/low speed source impedance adjustment" "+5%,+2.5%,,Default,,,,-2.5%,,,,,,,,-5%" bitfld.long 0x00 13.--14. " TXHSXVTUNE0 ,Transmitter High-Speed crossover adjustment" ",-15mv,+15mv,Default" bitfld.long 0x00 10.--12. " OTGTUNE0 ,VBUS valid threshold adjustment" "-6%,-4.5%,-3%,-1.5%,Default,+1.5%,+3%,+4.5%" textline " " bitfld.long 0x00 7.--9. " SQRXTUNE0 ,Squelch threshold adjustment" "+15%,+10%,+5%,Default,-5%,-10%,-15%,-20%" bitfld.long 0x00 4.--6. " COMPDISTUNE0 ,Disconnect threshold adjustment" "-6%,-4.5%,-3%,-1.5%,Default,+1.5%,+3%,+4.5%" bitfld.long 0x00 1.--3. " FSEL ,Reference clock frequency select" "9.6 MHz,10 MHz,12 MHz,19.2 MHz,20 MHz,24 MHz,,50 MHz" textline " " bitfld.long 0x00 0. " COMMONONN ,Common block Power-Down control" "Remained powered,Powered down" if (((per.l(ad:0x30B10200+0x20240)&0x08)==0x08)&&((per.l(ad:0x30B10200+0x20240)&0x04)==0x04)) group.long (0x10200+0x34)++0x03 line.long 0x00 "OTG2_PHY_CFG2,PHY_CFG2" bitfld.long 0x00 16. " DRVVBUS0 ,VBUS valid comparator enable" "Disabled,Enabled" bitfld.long 0x00 14. " VBUSVLDEXTSEL0 ,External VBUS valid select" "Internal,External" textline " " bitfld.long 0x00 13. " ADPPRBENB0 ,ADP probe enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADPDISCHRG0 ,VBUS input ADP discharge enable" "Disabled,Enabled" bitfld.long 0x00 11. " ADPCHRG0 ,VBUS input ADP charge enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OTGDISABLE0 ,OTG block disable" "No,Yes" bitfld.long 0x00 9. " TXBITSTUFFENH0 ,High-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXBITSTUFFEN0 ,Low-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " LOOPBACKENB0 ,Loopback test enable" "Disabled,Enabled" bitfld.long 0x00 5. " SLEEPM0 ,Sleep mode assertion" "Sleep mode,Normal mode" bitfld.long 0x00 4. " ACAENB0 ,ACA USB_OTG*_ID pin resistance detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DCDENB ,Data contact detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " VDATSRCENB0 ,Enable the VD*_SRC voltage source" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VDATDETENB0 ,Battery charging attach / connect detection enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHRGSEL ,Determines which of USB_OTG*_DP / USB_OTG*_DN has the VD*_SRC voltage source and which has the ID*_SINK current sink" "USB_OTG*_DP & USB_OTG*_DN,USB_OTG*_DN & USB_OTG*_DP" else group.long (0x10200+0x34)++0x03 line.long 0x00 "OTG2_PHY_CFG2,PHY_CFG2" bitfld.long 0x00 16. " DRVVBUS0 ,VBUS valid comparator enable" "Disabled,Enabled" bitfld.long 0x00 15. " VBUSVLDEXT ,External VBUS valid indicator" "Invalid,Valid" bitfld.long 0x00 14. " VBUSVLDEXTSEL0 ,External VBUS valid select" "Internal,External" textline " " bitfld.long 0x00 13. " ADPPRBENB0 ,ADP probe enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADPDISCHRG0 ,VBUS input ADP discharge enable" "Disabled,Enabled" bitfld.long 0x00 11. " ADPCHRG0 ,VBUS input ADP charge enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OTGDISABLE0 ,OTG block disable" "No,Yes" bitfld.long 0x00 9. " TXBITSTUFFENH0 ,High-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXBITSTUFFEN0 ,Low-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " LOOPBACKENB0 ,Loopback test enable" "Disabled,Enabled" bitfld.long 0x00 5. " SLEEPM0 ,Sleep mode assertion" "Sleep mode,Normal mode" bitfld.long 0x00 4. " ACAENB0 ,ACA USB_OTG*_ID pin resistance detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DCDENB ,Data contact detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " VDATSRCENB0 ,Enable the VD*_SRC voltage source" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VDATDETENB0 ,Battery charging attach / connect detection enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHRGSEL ,Determines which of USB_OTG*_DP / USB_OTG*_DN has the VD*_SRC voltage source and which has the ID*_SINK current sink" "USB_OTG*_DP & USB_OTG*_DN,USB_OTG*_DN & USB_OTG*_DP" endif textline " " rgroup.long (0x10200+0x3C)++0x03 line.long 0x00 "OTG2_PHY_STATUS,USB OTG PHY Status Register" bitfld.long 0x00 31. " ADPSNS0 ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the ADP sensing voltage" "Below,Above" bitfld.long 0x00 30. " ADPPRB0 ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the ADP probing voltage" "Below,Above" textline " " bitfld.long 0x00 29. " CHRGDET ,Battery charger detection output" "VD*VDAT_REF" bitfld.long 0x00 28. " RIDFLOAT0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is floating" "<=rid_a(max),>=rid_float(min)" textline " " bitfld.long 0x00 27. " RIDGND0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is grounded" ">=rid_c(min),<=rid_gnd(max)" bitfld.long 0x00 26. " RIDA0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_A range" ">=rid_float(Min) & <=rid_b(Max),>=rid_a(Min) & <=rid_a(Max)" textline " " bitfld.long 0x00 25. " RIDB0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_B range" ">=rid_a(Min) & <=rid_c(Max),>=rid_b(Min) & <=rid_b(Max)" bitfld.long 0x00 24. " RIDC0 ,Indicates whether the USB_OTG*_ID pin connected to an ACA is within the RID_C range" ">=rid_b(Min) & <=rid_gnd(Max),>=rid_c(Min) & <=rid_c(Max)" textline " " bitfld.long 0x00 5. " HOST_DISCONNECT ,Peripheral disconnect indicator" "Connected,Disconnected" bitfld.long 0x00 4. " ID_DIG ,Micro- or Mini- A/B plug indicator" "A plug,B plug" textline " " bitfld.long 0x00 3. " VBUS_VLD ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the VBUS valid threshold" "Below,Above" bitfld.long 0x00 2. " SESS_VLD ,Indicates whether the voltage on the USB_OTG*_VBUS pin is below the OTG device session valid threshold" "Below,Above" textline " " bitfld.long 0x00 0.--1. " LINE_STATE ,Line state indicator outputs from USB OTG PHY" "DP low & DN low,DP high & DN low,DP low & DN high,DP high & DN high" textline " " group.long 0x20200++0x03 line.long 0x00 "HSIC_CTRL1,HSIC_CTRL1" rbitfld.long 0x00 31. " WIR ,Wake-up interrupt request" "Not requested,Requested" bitfld.long 0x00 29. " WKUP_DPDM_EN ,DPDM changes wakeup enable" "Disabled,Enabled" bitfld.long 0x00 17. " WKUP_VBUS_EN ,VBUS changes wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " WKUP_ID_EN ,Wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x00 15. " WKUP_SW ,Software force Wake-up" "Not forced,Forced" bitfld.long 0x00 14. " WKUP_SW_EN ,Software Wake-up enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WIE ,Wake-up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " PWR_POL ,Power polarity" "Low,High" textline " " bitfld.long 0x00 8. " OVER_CUR_POL ,Polarity of overcurrent" "High,Low" bitfld.long 0x00 7. " OVER_CUR_DIS ,Disable overcurrent detection" "No,Yes" if (((per.l(ad:0x30B10200+0x20240))&0x0C)==0x0C) group.long (0x20200+0x04)++0x03 line.long 0x00 "HSIC_CTRL2,HSIC_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 2. " AUTURESUME_EN ,Auto resume enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" else group.long (0x20200+0x04)++0x03 line.long 0x00 "HSIC_CTRL2,HSIC_CTRL2" eventfld.long 0x00 31. " UTMI_CLK_VLD ,Indicate whether PHY clock is valid" "Invalid,Valid" bitfld.long 0x00 20. " DIG_ID_SEL ,Selects whether the USB OTG ID pin function is connected to the phy's USB_OTG*_ID pin or a GPIO pin" "USB_OTG*_ID,GPIO" bitfld.long 0x00 15. " DMPULLDOWN_OVERRIDEEN ,Enables override of control of the DM pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMPULLDOWN_OVERRIDE ,DM pulldown resistor enable" "Disabled,Enabled" bitfld.long 0x00 13. " DPPULLDOWN_OVERRIDEEN ,Enables override of control of the DP pulldown resistor instead of the state set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 12. " DPPULLDOWN_OVERRIDE ,DP pulldown resistor enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " XCVRSEL_OVERRIDEEN ,Enables override of control of the UTMI xcvrselect signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 9.--10. " XCVRSEL_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "HS transceiver,?..." bitfld.long 0x00 8. " OPMODE_OVERRIDEEN ,Enables override of control of the UTMI opmode signals to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " OPMODE_OVERRIDE ,Controls the state of the UTMI xcvrselect signals to the USB OTG PHY" "Normal operation,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP" bitfld.long 0x00 5. " TERMSEL_OVERRIDEEN ,Enables override of control of the UTMI termselect signal to the USB OTG PHY instead of using the state normally set by the USB controller" "Disabled,Enabled" bitfld.long 0x00 4. " TERMSEL_OVERRIDE ,Controls the state of the UTMI termselect signal to the USB OTG PHY" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LOWSPEED_EN ,Low speed enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VBUS_SOURCE_SEL ,VBUS source select" "VBUS_VALID,SESS_VALID,SESS_VALID,SESS_VALID" endif textline " " group.long (0x20200+0x40)++0x03 line.long 0x00 "UH_HSIC_PHY_CFG1,USB Host HSIC PHY Configuration Register" bitfld.long 0x00 24.--25. " REFCLKSEL ,Reference clock select" ",,2,?..." hexmask.long.byte 0x00 16.--22. 1. " REFCLKDIV ,Reference clock frequency select" bitfld.long 0x00 12.--15. " TXSRTUNE ,Driver slew rate adjustment for USB_H_DATA and USB_H_STROBE pins" "-20%,-10%,,Default,,,,+10%,,,,,,,,+20%" bitfld.long 0x00 10.--11. " TXRPDTUNE ,Driver pull-down single-ended source impedance adjustment for USB_H_DATA and USB_H_STROBE pins when driving low" "+11%,+5%,Default,-5%" textline " " bitfld.long 0x00 8.--9. " TXRPUTUNE ,Driver pull-up single-ended source impedance adjustment for USB_H_DATA and USB_H_STROBE pins when driving high" "+11%,+5%,Default,-5%" bitfld.long 0x00 6. " TXBITSTUFFENH ,High-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 5. " TXBITSTUFFEN ,Low-Byte transmit Bit-Stuffing enable" "Disabled,Enabled" bitfld.long 0x00 4. " SLEEPM ,Sleep mode assertion" "Sleep mode,Normal mode" textline " " bitfld.long 0x00 3. " DMPULLDOWN ,Bus keeper resistors enable" "Disabled,Enabled" bitfld.long 0x00 2. " DPPULLDOWN ,Bus keeper resistors enable" "Disabled,Enabled" bitfld.long 0x00 1. " LOOPBACKENB ,Loopback test enable" "Disabled,Enabled" bitfld.long 0x00 0. " COMMONONN ,Clock configuration setting" ",1" width 0x0B tree.end tree.open "USB (USB Core)" tree "USB_OTG1 (USB_OTG1)" base ad:0x30B10000 width 23. rgroup.long 0x00++0x07 line.long 0x00 "OTG1_OTG1_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the controller core" bitfld.long 0x00 8.--13. " NID ,Complement version of ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "OTG1_HWGENERAL,Hardware General" bitfld.long 0x04 10.--11. " SM ,Serial interface mode capability" "No serial engine,?..." bitfld.long 0x04 6.--9. " PHYM ,Transceiver type" "UTMI/UMTI+,,,,,,,,,,,Reset to HSIC,?..." bitfld.long 0x04 4.--5. " PHYW ,Data width of the transciever connected to the controller core" ",,,16 bit" if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x03) rgroup.long 0x08++0x03 line.long 0x00 "OTG1_HWHOST,Host Hardware Parameters" bitfld.long 0x00 1.--3. " NPORT ,The number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host capable" "Not supported,Supported" else hgroup.long 0x08++0x03 hide.long 0x00 "OTG1_HWHOST,Host Hardware Parameters" endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) rgroup.long 0x0C++0x03 line.long 0x00 "OTG1_HWDEVICE,Device Hardware Parameters" bitfld.long 0x00 1.--5. " DEVEP ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device capable" "Not supported,Supported" else hgroup.long 0x0C++0x03 hide.long 0x00 "HWDEVICE,Device Hardware Parameters" endif rgroup.long 0x10++0x07 line.long 0x00 "OTG1_HWTXBUF,TX Buffer Hardware Parameters" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,TX FIFO Buffer size" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "OTG1_HWRXBUF,RX Buffer Hardware Parameters" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Single receive FIFO buffer in the USB controller" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" group.long 0x80++0x13 line.long 0x00 "OTG1_GPTIMER0LD,General Purpose Timer #0 Load" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "OTG1_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "OTG1_GPTIMER1LD,General Purpose Timer #1 Load" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x10 "OTG1_SBUSCFG,System Bus Config" bitfld.long 0x10 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Capability Register Length" if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x03) rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version" rgroup.long 0x104++0x07 line.long 0x00 "OTG1_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Indicates the number of embedded transaction translators associated with the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Indicates the number of ports assigned to each transaction translator within the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Indicates whether the ports support port indicator control" "Not supported,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Indicates the number of ports supported per internal companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS ,Specifies the number of physical downstream ports implemented on this host controller" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "OTG1_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" textline " " bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" else hgroup.word 0x102++0x01 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long 0x104++0x07 hide.long 0x00 "OTG1_HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "OTG1_HCCPARAMS,Host Controller Capability Parameters" endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Controller Interface Version" else hgroup.word 0x120++0x01 hide.word 0x00 "DCIVERSION,Device Controller Interface Version" endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) rgroup.long 0x124++0x03 line.long 0x00 "OTG1_DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 8. " HC ,EHCI host capable" "Incapable,Capable" bitfld.long 0x00 7. " DC ,Device capable" "Incapable,Capable" bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." else hgroup.long 0x124++0x03 hide.long 0x00 "OTG1_DCCPARAMS,Device Controller Capability Parameters" endif textline " " if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) if (((per.l(ad:0x30B10000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B10000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B10000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "OTG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "OTG1_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " URE ,USB reset interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" group.long 0x154++0x07 line.long 0x00 "OTG1_DEVICEADDR,Device Address" hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "Instantaneous,Staged and held in hidden register" line.long 0x04 "OTG1_ENDPTLISTADDR,Endpoint List Address" hexmask.long.tbyte 0x04 11.--31. 0x08 " EPBASE ,Endpoint list Pointer(Low)" elif (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x03) if (((per.l(ad:0x30B10000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B10000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B10000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "OTG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "OTG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "OTG1_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " AAE ,Async advance interrupt enable" "Disabled,Enabled" bitfld.long 0x04 4. " SEE ,System error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 3. " FRE ,Frame list rollover interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30B10000+0x144))&0x1000)==0x1000) group.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" else rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" endif group.long 0x154++0x07 line.long 0x00 "OTG1_PERIODICLISTBASE,Frame List Base Address" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "OTG1_ASYNCLISTADDR,Next Asynch. Address" hexmask.long 0x04 5.--31. 0x20 " ASYBASE ,Link pointer low" else hgroup.long 0x140++0x0F hide.long 0x00 "OTG1_USBCMD,USB Command Register" textline " " textline " " hide.long 0x04 "OTG1_USBSTS,USB Status Register" textline " " textline " " textline " " textline " " hide.long 0x08 "OTG1_USBINTR,Interrupt Enable Register" textline " " textline " " textline " " hide.long 0x0C "FRINDEX,USB Frame Index" hgroup.long 0x154++0x07 hide.long 0x00 "OTG1_DEVICEADDR,Device Address" hide.long 0x04 "OTG1_ENDPTLISTADDR,Endpoint List Address" endif group.long 0x160++0x07 line.long 0x00 "OTG1_BURSTSIZE,Programmable Burst Size" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst size" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst size" line.long 0x04 "OTG1_TXFILLTUNING,TX FIFO Fill Tuning" bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" textline " " group.long 0x178++0x07 line.long 0x00 "OTG1_ENDPTNAK,Endpoint NAK" bitfld.long 0x00 23. " EPTN[7] ,TX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 22. " EPTN[6] ,TX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 21. " EPTN[5] ,TX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 20. " EPTN[4] ,TX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 18. " EPTN[2] ,TX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 17. " EPTN[1] ,TX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 16. " EPTN[0] ,TX endpoint 0 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 6. " EPRN[6] ,RX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 5. " EPRN[5] ,RX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 4. " EPRN[4] ,RX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 2. " EPRN[2] ,RX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 1. " EPRN[1] ,RX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 0. " EPRN[0] ,RX endpoint 0 NAK" "Not sent,Sent" line.long 0x04 "OTG1_ENDPTNAKEN,Endpoint NAK Enable" bitfld.long 0x04 23. " EPTNE[7] ,TX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 22. " EPTNE[6] ,TX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 21. " EPTNE[5] ,TX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 20. " EPTNE[4] ,TX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTNE[3] ,TX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 18. " EPTNE[2] ,TX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 17. " EPTNE[1] ,TX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 16. " EPTNE[0] ,TX endpoint 0 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRNE[7] ,RX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 6. " EPRNE[6] ,RX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 5. " EPRNE[5] ,RX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 1. " EPRNE[1] ,RX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX endpoint 0 NAK" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "OTG1_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Controls the default port-routing control logic (To which host controller ports are routed)" "Classic,This" textline " " if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B10000+0x104))&0x10)==0x10) group.long 0x184++0x03 line.long 0x00 "OTG1_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " bitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" elif (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B10000+0x104))&0x10)==0x00) group.long 0x184++0x03 line.long 0x00 "OTG1_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " rbitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" elif (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02)&&(((per.l(ad:0x30B10000+0x104))&0x10)==0x10) group.long 0x184++0x03 line.long 0x00 "OTG1_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " bitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" rbitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,?..." bitfld.long 0x00 2. " PE ,Port enabled/disabled" ",Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not present,Present" elif (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02)&&(((per.l(ad:0x30B10000+0x104))&0x10)==0x00) group.long 0x184++0x03 line.long 0x00 "OTG1_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " rbitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" rbitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,?..." bitfld.long 0x00 2. " PE ,Port enabled/disabled" ",Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not present,Present" else hgroup.long 0x184++0x03 hide.long 0x00 "OTG1_PORTSC1,Port Status & Control" textline " " textline " " textline " " textline " " textline " " endif textline " " group.long 0x1A4++0x03 line.long 0x00 "OTG1_OTGSC,On-The-Go Status & Control" bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " EN_1MS ,1 millisecond timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " STATUS_1MS ,1 millisecond timer interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected" rbitfld.long 0x00 13. " TOG_1MS ,1 millisecond timer toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B session end" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B session valid" "Invalid,Valid" rbitfld.long 0x00 10. " ASV ,A session valid" "Invalid,Valid" rbitfld.long 0x00 9. " AVV ,A VBUS valid" "Invalid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID pullup" "Off,On" bitfld.long 0x00 4. " DP ,Data pulsing" "Not pulled-up,Pulled-up" bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,Vbus_discharge" "Not discharged,Discharged" group.long 0x1A8++0x03 line.long 0x00 "OTG1_USBMODE,USB Device Mode" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device controller,Host controller" textline " " if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1AC++0x03 line.long 0x00 "OTG1_ENDPTSETUPSTAT,Endpoint Setup Status" hexmask.long.word 0x00 0.--15. 1. " ENDPTSETUPSTAT ,Setup endpoint status" group.long 0x1B0++0x07 line.long 0x00 "OTG1_ENDPTPRIME,Endpoint Prime" bitfld.long 0x00 23. " PETB[7] ,Prime endpoint 7 transmit buffer" "Not requested,Requested" bitfld.long 0x00 22. " PETB[6] ,Prime endpoint 6 transmit buffer" "Not requested,Requested" bitfld.long 0x00 21. " PETB[5] ,Prime endpoint 5 transmit buffer" "Not requested,Requested" bitfld.long 0x00 20. " PETB[4] ,Prime endpoint 4 transmit buffer" "Not requested,Requested" textline " " bitfld.long 0x00 19. " PETB[3] ,Prime endpoint 3 transmit buffer" "Not requested,Requested" bitfld.long 0x00 18. " PETB[2] ,Prime endpoint 2 transmit buffer" "Not requested,Requested" bitfld.long 0x00 17. " PETB[1] ,Prime endpoint 1 transmit buffer" "Not requested,Requested" bitfld.long 0x00 16. " PETB[0] ,Prime endpoint 0 transmit buffer" "Not requested,Requested" textline " " bitfld.long 0x00 7. " PERB[7] ,Prime endpoint 7 receive buffer" "Not requested,Requested" bitfld.long 0x00 6. " PERB[6] ,Prime endpoint 6 receive buffer" "Not requested,Requested" bitfld.long 0x00 5. " PERB[5] ,Prime endpoint 5 receive buffer" "Not requested,Requested" bitfld.long 0x00 4. " PERB[4] ,Prime endpoint 4 receive buffer" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PERB[3] ,Prime endpoint 3 receive buffer" "Not requested,Requested" bitfld.long 0x00 2. " PERB[2] ,Prime endpoint 2 receive buffer" "Not requested,Requested" bitfld.long 0x00 1. " PERB[1] ,Prime endpoint 1 receive buffer" "Not requested,Requested" bitfld.long 0x00 0. " PERB[0] ,Prime endpoint 0 receive buffer" "Not requested,Requested" line.long 0x04 "OTG1_ENDPTFLUSH,Endpoint Flush" bitfld.long 0x04 23. " FETB[7] ,Flush endpoint 7 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 22. " FETB[6] ,Flush endpoint 6 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 21. " FETB[5] ,Flush endpoint 5 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 20. " FETB[4] ,Flush endpoint 4 transmit buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 19. " FETB[3] ,Flush endpoint 3 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 18. " FETB[2] ,Flush endpoint 2 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 17. " FETB[1] ,Flush endpoint 1 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 16. " FETB[0] ,Flush endpoint 0 transmit buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 7. " FERB[7] ,Flush endpoint 7 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 6. " FERB[6] ,Flush endpoint 6 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 5. " FERB[5] ,Flush endpoint 5 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 4. " FERB[4] ,Flush endpoint 4 receive buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " FERB[3] ,Flush endpoint 3 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 2. " FERB[2] ,Flush endpoint 2 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 1. " FERB[1] ,Flush endpoint 1 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 0. " FERB[0] ,Flush endpoint 0 receive buffer" "Not cleared,Cleared" rgroup.long 0x1B8++0x03 line.long 0x00 "OTG1_ENDPTSTAT,Endpoint Status" bitfld.long 0x00 23. " ETBR[7] ,Endpoint 7 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR[6] ,Endpoint 6 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR[5] ,Endpoint 5 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR[4] ,Endpoint 4 transmit buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR[3] ,Endpoint 3 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR[2] ,Endpoint 2 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR[1] ,Endpoint 1 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR[0] ,Endpoint 0 transmit buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR[7] ,Endpoint 7 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR[6] ,Endpoint 6 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR[5] ,Endpoint 5 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR[4] ,Endpoint 4 receive buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR[3] ,Endpoint 3 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR[2] ,Endpoint 2 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR[1] ,Endpoint 1 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR[0] ,Endpoint 0 receive buffer ready" "Not ready,Ready" group.long 0x1BC++0x03 line.long 0x00 "OTG1_ENDPTCOMPLETE,Endpoint Complete" eventfld.long 0x00 23. " ETCE[7] ,Endpoint 7 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE[6] ,Endpoint 6 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE[5] ,Endpoint 5 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE[4] ,Endpoint 4 transmit complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE[3] ,Endpoint 3 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE[2] ,Endpoint 2 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE[1] ,Endpoint 1 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE[0] ,Endpoint 0 transmit complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE[7] ,Endpoint 7 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE[6] ,Endpoint 6 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE[5] ,Endpoint 5 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE[4] ,Endpoint 4 receive complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE[3] ,Endpoint 3 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE[2] ,Endpoint 2 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE[1] ,Endpoint 1 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE[0] ,Endpoint 0 receive complete event" "Not occurred,Occurred" else hgroup.long 0x1AC++0x13 hide.long 0x00 "OTG1_ENDPTSETUPSTAT,Endpoint Setup Status" hide.long 0x04 "OTG1_ENDPTPRIME,Endpoint Prime" textline " " textline " " textline " " hide.long 0x08 "OTG1_ENDPTFLUSH,Endpoint Flush" textline " " textline " " textline " " hide.long 0x0C "OTG1_ENDPTSTAT,Endpoint Status" textline " " textline " " textline " " hide.long 0x10 "OTG1_ENDPTCOMPLETE,Endpoint Complete" textline " " textline " " textline " " endif textline " " group.long 0x1C0++0x03 line.long 0x00 "OTG1_ENDPTCTRL0,Endpoint Control0" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint" "Control,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" textline " " if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1C4++0x03 line.long 0x00 "OTG1_ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C4++0x03 hide.long 0x00 "OTG1_ENDPTCTRL1,Endpoint Control 1" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1C8++0x03 line.long 0x00 "OTG1_ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C8++0x03 hide.long 0x00 "OTG1_ENDPTCTRL2,Endpoint Control 2" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1CC++0x03 line.long 0x00 "OTG1_ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1CC++0x03 hide.long 0x00 "OTG1_ENDPTCTRL3,Endpoint Control 3" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1D0++0x03 line.long 0x00 "OTG1_ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D0++0x03 hide.long 0x00 "OTG1_ENDPTCTRL4,Endpoint Control 4" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1D4++0x03 line.long 0x00 "OTG1_ENDPTCTRL5,Endpoint Control 5" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D4++0x03 hide.long 0x00 "OTG1_ENDPTCTRL5,Endpoint Control 5" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1D8++0x03 line.long 0x00 "OTG1_ENDPTCTRL6,Endpoint Control 6" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D8++0x03 hide.long 0x00 "OTG1_ENDPTCTRL6,Endpoint Control 6" textline " " textline " " endif if (((per.l(ad:0x30B10000+0x1A8))&0x03)==0x02) group.long 0x1DC++0x03 line.long 0x00 "OTG1_ENDPTCTRL7,Endpoint Control 7" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1DC++0x03 hide.long 0x00 "OTG1_ENDPTCTRL7,Endpoint Control 7" textline " " textline " " endif width 0x0B tree.end sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) tree "USB_OTG2 (USB_OTG2)" base ad:0x30B20000 width 23. rgroup.long 0x00++0x07 line.long 0x00 "OTG2_OTG2_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the controller core" bitfld.long 0x00 8.--13. " NID ,Complement version of ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "OTG2_HWGENERAL,Hardware General" bitfld.long 0x04 10.--11. " SM ,Serial interface mode capability" "No serial engine,?..." bitfld.long 0x04 6.--9. " PHYM ,Transceiver type" "UTMI/UMTI+,,,,,,,,,,,Reset to HSIC,?..." bitfld.long 0x04 4.--5. " PHYW ,Data width of the transciever connected to the controller core" ",,,16 bit" if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x03) rgroup.long 0x08++0x03 line.long 0x00 "OTG2_HWHOST,Host Hardware Parameters" bitfld.long 0x00 1.--3. " NPORT ,The number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host capable" "Not supported,Supported" else hgroup.long 0x08++0x03 hide.long 0x00 "OTG2_HWHOST,Host Hardware Parameters" endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) rgroup.long 0x0C++0x03 line.long 0x00 "OTG2_HWDEVICE,Device Hardware Parameters" bitfld.long 0x00 1.--5. " DEVEP ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device capable" "Not supported,Supported" else hgroup.long 0x0C++0x03 hide.long 0x00 "HWDEVICE,Device Hardware Parameters" endif rgroup.long 0x10++0x07 line.long 0x00 "OTG2_HWTXBUF,TX Buffer Hardware Parameters" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,TX FIFO Buffer size" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "OTG2_HWRXBUF,RX Buffer Hardware Parameters" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Single receive FIFO buffer in the USB controller" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" group.long 0x80++0x13 line.long 0x00 "OTG2_GPTIMER0LD,General Purpose Timer #0 Load" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "OTG2_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "OTG2_GPTIMER1LD,General Purpose Timer #1 Load" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x10 "OTG2_SBUSCFG,System Bus Config" bitfld.long 0x10 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Capability Register Length" if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x03) rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version" rgroup.long 0x104++0x07 line.long 0x00 "OTG2_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Indicates the number of embedded transaction translators associated with the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Indicates the number of ports assigned to each transaction translator within the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Indicates whether the ports support port indicator control" "Not supported,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Indicates the number of ports supported per internal companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS ,Specifies the number of physical downstream ports implemented on this host controller" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "OTG2_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" textline " " bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" else hgroup.word 0x102++0x01 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long 0x104++0x07 hide.long 0x00 "OTG2_HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "OTG2_HCCPARAMS,Host Controller Capability Parameters" endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Controller Interface Version" else hgroup.word 0x120++0x01 hide.word 0x00 "DCIVERSION,Device Controller Interface Version" endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) rgroup.long 0x124++0x03 line.long 0x00 "OTG2_DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 8. " HC ,EHCI host capable" "Incapable,Capable" bitfld.long 0x00 7. " DC ,Device capable" "Incapable,Capable" bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." else hgroup.long 0x124++0x03 hide.long 0x00 "OTG2_DCCPARAMS,Device Controller Capability Parameters" endif textline " " if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) if (((per.l(ad:0x30B20000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B20000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B20000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "OTG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "OTG2_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " URE ,USB reset interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" group.long 0x154++0x07 line.long 0x00 "OTG2_DEVICEADDR,Device Address" hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "Instantaneous,Staged and held in hidden register" line.long 0x04 "OTG2_ENDPTLISTADDR,Endpoint List Address" hexmask.long.tbyte 0x04 11.--31. 0x08 " EPBASE ,Endpoint list Pointer(Low)" elif (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x03) if (((per.l(ad:0x30B20000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B20000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B20000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "OTG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "OTG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "OTG2_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " AAE ,Async advance interrupt enable" "Disabled,Enabled" bitfld.long 0x04 4. " SEE ,System error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 3. " FRE ,Frame list rollover interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30B20000+0x144))&0x1000)==0x1000) group.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" else rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" endif group.long 0x154++0x07 line.long 0x00 "OTG2_PERIODICLISTBASE,Frame List Base Address" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "OTG2_ASYNCLISTADDR,Next Asynch. Address" hexmask.long 0x04 5.--31. 0x20 " ASYBASE ,Link pointer low" else hgroup.long 0x140++0x0F hide.long 0x00 "OTG2_USBCMD,USB Command Register" textline " " textline " " hide.long 0x04 "OTG2_USBSTS,USB Status Register" textline " " textline " " textline " " textline " " hide.long 0x08 "OTG2_USBINTR,Interrupt Enable Register" textline " " textline " " textline " " hide.long 0x0C "FRINDEX,USB Frame Index" hgroup.long 0x154++0x07 hide.long 0x00 "OTG2_DEVICEADDR,Device Address" hide.long 0x04 "OTG2_ENDPTLISTADDR,Endpoint List Address" endif group.long 0x160++0x07 line.long 0x00 "OTG2_BURSTSIZE,Programmable Burst Size" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst size" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst size" line.long 0x04 "OTG2_TXFILLTUNING,TX FIFO Fill Tuning" bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" textline " " group.long 0x178++0x07 line.long 0x00 "OTG2_ENDPTNAK,Endpoint NAK" bitfld.long 0x00 23. " EPTN[7] ,TX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 22. " EPTN[6] ,TX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 21. " EPTN[5] ,TX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 20. " EPTN[4] ,TX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 18. " EPTN[2] ,TX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 17. " EPTN[1] ,TX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 16. " EPTN[0] ,TX endpoint 0 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 6. " EPRN[6] ,RX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 5. " EPRN[5] ,RX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 4. " EPRN[4] ,RX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 2. " EPRN[2] ,RX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 1. " EPRN[1] ,RX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 0. " EPRN[0] ,RX endpoint 0 NAK" "Not sent,Sent" line.long 0x04 "OTG2_ENDPTNAKEN,Endpoint NAK Enable" bitfld.long 0x04 23. " EPTNE[7] ,TX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 22. " EPTNE[6] ,TX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 21. " EPTNE[5] ,TX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 20. " EPTNE[4] ,TX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTNE[3] ,TX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 18. " EPTNE[2] ,TX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 17. " EPTNE[1] ,TX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 16. " EPTNE[0] ,TX endpoint 0 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRNE[7] ,RX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 6. " EPRNE[6] ,RX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 5. " EPRNE[5] ,RX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 1. " EPRNE[1] ,RX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX endpoint 0 NAK" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "OTG2_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Controls the default port-routing control logic (To which host controller ports are routed)" "Classic,This" textline " " if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B20000+0x104))&0x10)==0x10) group.long 0x184++0x03 line.long 0x00 "OTG2_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " bitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" elif (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B20000+0x104))&0x10)==0x00) group.long 0x184++0x03 line.long 0x00 "OTG2_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " rbitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" elif (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02)&&(((per.l(ad:0x30B20000+0x104))&0x10)==0x10) group.long 0x184++0x03 line.long 0x00 "OTG2_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " bitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" rbitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,?..." bitfld.long 0x00 2. " PE ,Port enabled/disabled" ",Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not present,Present" elif (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02)&&(((per.l(ad:0x30B20000+0x104))&0x10)==0x00) group.long 0x184++0x03 line.long 0x00 "OTG2_PORTSC1,Port Status & Control" rbitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" rbitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " rbitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" rbitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,?..." bitfld.long 0x00 2. " PE ,Port enabled/disabled" ",Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not present,Present" else hgroup.long 0x184++0x03 hide.long 0x00 "OTG2_PORTSC1,Port Status & Control" textline " " textline " " textline " " textline " " textline " " endif textline " " group.long 0x1A4++0x03 line.long 0x00 "OTG2_OTGSC,On-The-Go Status & Control" bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " EN_1MS ,1 millisecond timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " STATUS_1MS ,1 millisecond timer interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected" rbitfld.long 0x00 13. " TOG_1MS ,1 millisecond timer toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B session end" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B session valid" "Invalid,Valid" rbitfld.long 0x00 10. " ASV ,A session valid" "Invalid,Valid" rbitfld.long 0x00 9. " AVV ,A VBUS valid" "Invalid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID pullup" "Off,On" bitfld.long 0x00 4. " DP ,Data pulsing" "Not pulled-up,Pulled-up" bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,Vbus_discharge" "Not discharged,Discharged" group.long 0x1A8++0x03 line.long 0x00 "OTG2_USBMODE,USB Device Mode" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device controller,Host controller" textline " " if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1AC++0x03 line.long 0x00 "OTG2_ENDPTSETUPSTAT,Endpoint Setup Status" hexmask.long.word 0x00 0.--15. 1. " ENDPTSETUPSTAT ,Setup endpoint status" group.long 0x1B0++0x07 line.long 0x00 "OTG2_ENDPTPRIME,Endpoint Prime" bitfld.long 0x00 23. " PETB[7] ,Prime endpoint 7 transmit buffer" "Not requested,Requested" bitfld.long 0x00 22. " PETB[6] ,Prime endpoint 6 transmit buffer" "Not requested,Requested" bitfld.long 0x00 21. " PETB[5] ,Prime endpoint 5 transmit buffer" "Not requested,Requested" bitfld.long 0x00 20. " PETB[4] ,Prime endpoint 4 transmit buffer" "Not requested,Requested" textline " " bitfld.long 0x00 19. " PETB[3] ,Prime endpoint 3 transmit buffer" "Not requested,Requested" bitfld.long 0x00 18. " PETB[2] ,Prime endpoint 2 transmit buffer" "Not requested,Requested" bitfld.long 0x00 17. " PETB[1] ,Prime endpoint 1 transmit buffer" "Not requested,Requested" bitfld.long 0x00 16. " PETB[0] ,Prime endpoint 0 transmit buffer" "Not requested,Requested" textline " " bitfld.long 0x00 7. " PERB[7] ,Prime endpoint 7 receive buffer" "Not requested,Requested" bitfld.long 0x00 6. " PERB[6] ,Prime endpoint 6 receive buffer" "Not requested,Requested" bitfld.long 0x00 5. " PERB[5] ,Prime endpoint 5 receive buffer" "Not requested,Requested" bitfld.long 0x00 4. " PERB[4] ,Prime endpoint 4 receive buffer" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PERB[3] ,Prime endpoint 3 receive buffer" "Not requested,Requested" bitfld.long 0x00 2. " PERB[2] ,Prime endpoint 2 receive buffer" "Not requested,Requested" bitfld.long 0x00 1. " PERB[1] ,Prime endpoint 1 receive buffer" "Not requested,Requested" bitfld.long 0x00 0. " PERB[0] ,Prime endpoint 0 receive buffer" "Not requested,Requested" line.long 0x04 "OTG2_ENDPTFLUSH,Endpoint Flush" bitfld.long 0x04 23. " FETB[7] ,Flush endpoint 7 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 22. " FETB[6] ,Flush endpoint 6 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 21. " FETB[5] ,Flush endpoint 5 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 20. " FETB[4] ,Flush endpoint 4 transmit buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 19. " FETB[3] ,Flush endpoint 3 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 18. " FETB[2] ,Flush endpoint 2 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 17. " FETB[1] ,Flush endpoint 1 transmit buffer" "Not cleared,Cleared" bitfld.long 0x04 16. " FETB[0] ,Flush endpoint 0 transmit buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 7. " FERB[7] ,Flush endpoint 7 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 6. " FERB[6] ,Flush endpoint 6 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 5. " FERB[5] ,Flush endpoint 5 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 4. " FERB[4] ,Flush endpoint 4 receive buffer" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " FERB[3] ,Flush endpoint 3 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 2. " FERB[2] ,Flush endpoint 2 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 1. " FERB[1] ,Flush endpoint 1 receive buffer" "Not cleared,Cleared" bitfld.long 0x04 0. " FERB[0] ,Flush endpoint 0 receive buffer" "Not cleared,Cleared" rgroup.long 0x1B8++0x03 line.long 0x00 "OTG2_ENDPTSTAT,Endpoint Status" bitfld.long 0x00 23. " ETBR[7] ,Endpoint 7 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR[6] ,Endpoint 6 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR[5] ,Endpoint 5 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR[4] ,Endpoint 4 transmit buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR[3] ,Endpoint 3 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR[2] ,Endpoint 2 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR[1] ,Endpoint 1 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR[0] ,Endpoint 0 transmit buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR[7] ,Endpoint 7 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR[6] ,Endpoint 6 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR[5] ,Endpoint 5 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR[4] ,Endpoint 4 receive buffer ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR[3] ,Endpoint 3 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR[2] ,Endpoint 2 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR[1] ,Endpoint 1 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR[0] ,Endpoint 0 receive buffer ready" "Not ready,Ready" group.long 0x1BC++0x03 line.long 0x00 "OTG2_ENDPTCOMPLETE,Endpoint Complete" eventfld.long 0x00 23. " ETCE[7] ,Endpoint 7 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE[6] ,Endpoint 6 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE[5] ,Endpoint 5 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE[4] ,Endpoint 4 transmit complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE[3] ,Endpoint 3 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE[2] ,Endpoint 2 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE[1] ,Endpoint 1 transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE[0] ,Endpoint 0 transmit complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE[7] ,Endpoint 7 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE[6] ,Endpoint 6 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE[5] ,Endpoint 5 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE[4] ,Endpoint 4 receive complete event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE[3] ,Endpoint 3 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE[2] ,Endpoint 2 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE[1] ,Endpoint 1 receive complete event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE[0] ,Endpoint 0 receive complete event" "Not occurred,Occurred" else hgroup.long 0x1AC++0x13 hide.long 0x00 "OTG2_ENDPTSETUPSTAT,Endpoint Setup Status" hide.long 0x04 "OTG2_ENDPTPRIME,Endpoint Prime" textline " " textline " " textline " " hide.long 0x08 "OTG2_ENDPTFLUSH,Endpoint Flush" textline " " textline " " textline " " hide.long 0x0C "OTG2_ENDPTSTAT,Endpoint Status" textline " " textline " " textline " " hide.long 0x10 "OTG2_ENDPTCOMPLETE,Endpoint Complete" textline " " textline " " textline " " endif textline " " group.long 0x1C0++0x03 line.long 0x00 "OTG2_ENDPTCTRL0,Endpoint Control0" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint" "Control,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" textline " " if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1C4++0x03 line.long 0x00 "OTG2_ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C4++0x03 hide.long 0x00 "OTG2_ENDPTCTRL1,Endpoint Control 1" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1C8++0x03 line.long 0x00 "OTG2_ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C8++0x03 hide.long 0x00 "OTG2_ENDPTCTRL2,Endpoint Control 2" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1CC++0x03 line.long 0x00 "OTG2_ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1CC++0x03 hide.long 0x00 "OTG2_ENDPTCTRL3,Endpoint Control 3" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1D0++0x03 line.long 0x00 "OTG2_ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D0++0x03 hide.long 0x00 "OTG2_ENDPTCTRL4,Endpoint Control 4" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1D4++0x03 line.long 0x00 "OTG2_ENDPTCTRL5,Endpoint Control 5" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D4++0x03 hide.long 0x00 "OTG2_ENDPTCTRL5,Endpoint Control 5" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1D8++0x03 line.long 0x00 "OTG2_ENDPTCTRL6,Endpoint Control 6" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1D8++0x03 hide.long 0x00 "OTG2_ENDPTCTRL6,Endpoint Control 6" textline " " textline " " endif if (((per.l(ad:0x30B20000+0x1A8))&0x03)==0x02) group.long 0x1DC++0x03 line.long 0x00 "OTG2_ENDPTCTRL7,Endpoint Control 7" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1DC++0x03 hide.long 0x00 "OTG2_ENDPTCTRL7,Endpoint Control 7" textline " " textline " " endif width 0x0B tree.end endif tree "USB_HSIC (USB_HSIC)" base ad:0x30B30000 width 23. rgroup.long 0x00++0x07 line.long 0x00 "HSIC_HSIC_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the controller core" bitfld.long 0x00 8.--13. " NID ,Complement version of ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HSIC_HWGENERAL,Hardware General" bitfld.long 0x04 10.--11. " SM ,Serial interface mode capability" "No serial engine,?..." bitfld.long 0x04 6.--9. " PHYM ,Transceiver type" "UTMI/UMTI+,,,,,,,,,,,Reset to HSIC,?..." bitfld.long 0x04 4.--5. " PHYW ,Data width of the transciever connected to the controller core" ",,,16 bit" if (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x03) rgroup.long 0x08++0x03 line.long 0x00 "HSIC_HWHOST,Host Hardware Parameters" bitfld.long 0x00 1.--3. " NPORT ,The number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host capable" "Not supported,Supported" else hgroup.long 0x08++0x03 hide.long 0x00 "HSIC_HWHOST,Host Hardware Parameters" endif hgroup.long 0x0C++0x03 hide.long 0x00 "HWDEVICE,Device Hardware Parameters" rgroup.long 0x10++0x07 line.long 0x00 "HSIC_HWTXBUF,TX Buffer Hardware Parameters" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,TX FIFO Buffer size" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "HSIC_HWRXBUF,RX Buffer Hardware Parameters" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Single receive FIFO buffer in the USB controller" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" group.long 0x80++0x13 line.long 0x00 "HSIC_GPTIMER0LD,General Purpose Timer #0 Load" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "HSIC_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "HSIC_GPTIMER1LD,General Purpose Timer #1 Load" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x10 "HSIC_SBUSCFG,System Bus Config" bitfld.long 0x10 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Capability Register Length" if (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x03) rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version" rgroup.long 0x104++0x07 line.long 0x00 "HSIC_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Indicates the number of embedded transaction translators associated with the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Indicates the number of ports assigned to each transaction translator within the USB2.0 host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Indicates whether the ports support port indicator control" "Not supported,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Indicates the number of ports supported per internal companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS ,Specifies the number of physical downstream ports implemented on this host controller" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HSIC_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" textline " " bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" else hgroup.word 0x102++0x01 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long 0x104++0x07 hide.long 0x00 "HSIC_HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HSIC_HCCPARAMS,Host Controller Capability Parameters" endif if (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x02) rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Controller Interface Version" else hgroup.word 0x120++0x01 hide.word 0x00 "DCIVERSION,Device Controller Interface Version" endif hgroup.long 0x124++0x03 hide.long 0x00 "HSIC_DCCPARAMS,Device Controller Capability Parameters" textline " " if (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x02) if (((per.l(ad:0x30B30000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B30000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B30000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 13. " SUTW ,Indicates that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted" "Not corrupted,Corrupted" bitfld.long 0x00 12. " ATDTW ,Indicates that the proper addition of a new dtd to an active (Primed) endpoint's linked list has been asserted" "Not asserted,Asserted" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "HSIC_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "HSIC_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " URE ,USB reset interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" group.long 0x154++0x07 line.long 0x00 "HSIC_DEVICEADDR,Device Address" hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "Instantaneous,Staged and held in hidden register" line.long 0x04 "HSIC_ENDPTLISTADDR,Endpoint List Address" hexmask.long.tbyte 0x04 11.--31. 0x08 " EPBASE ,Endpoint list Pointer(Low)" elif (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x03) if (((per.l(ad:0x30B30000+0x108))&0x06)==0x06) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B30000+0x108))&0x06)==0x02) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS ,Frame list size" "1024,512,256,128,64,31,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" elif (((per.l(ad:0x30B30000+0x108))&0x06)==0x04) group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "HSIC_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" rbitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/stop" "Stopped,Running" endif group.long 0x144++0x07 line.long 0x00 "HSIC_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" eventfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " eventfld.long 0x00 4. " SEI ,System Error" "No error,Error" eventfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" line.long 0x04 "HSIC_USBINTR,Interrupt Enable Register" bitfld.long 0x04 25. " TIE1 ,General purpose timer #1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " TIE0 ,General purpose timer #0 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " SRE ,SOF received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " AAE ,Async advance interrupt enable" "Disabled,Enabled" bitfld.long 0x04 4. " SEE ,System error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 3. " FRE ,Frame list rollover interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PCE ,Port change detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " UE ,USB interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x30B30000+0x144))&0x1000)==0x1000) group.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" else rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame list current index" endif group.long 0x154++0x07 line.long 0x00 "HSIC_PERIODICLISTBASE,Frame List Base Address" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "HSIC_ASYNCLISTADDR,Next Asynch. Address" hexmask.long 0x04 5.--31. 0x20 " ASYBASE ,Link pointer low" else hgroup.long 0x140++0x0F hide.long 0x00 "HSIC_USBCMD,USB Command Register" textline " " textline " " hide.long 0x04 "HSIC_USBSTS,USB Status Register" textline " " textline " " textline " " textline " " hide.long 0x08 "HSIC_USBINTR,Interrupt Enable Register" textline " " textline " " textline " " hide.long 0x0C "FRINDEX,USB Frame Index" hgroup.long 0x154++0x07 hide.long 0x00 "HSIC_DEVICEADDR,Device Address" hide.long 0x04 "HSIC_ENDPTLISTADDR,Endpoint List Address" endif group.long 0x160++0x07 line.long 0x00 "HSIC_BURSTSIZE,Programmable Burst Size" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst size" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst size" line.long 0x04 "HSIC_TXFILLTUNING,TX FIFO Fill Tuning" bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" textline " " group.long 0x178++0x07 line.long 0x00 "HSIC_ENDPTNAK,Endpoint NAK" bitfld.long 0x00 23. " EPTN[7] ,TX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 22. " EPTN[6] ,TX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 21. " EPTN[5] ,TX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 20. " EPTN[4] ,TX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 18. " EPTN[2] ,TX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 17. " EPTN[1] ,TX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 16. " EPTN[0] ,TX endpoint 0 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX endpoint 7 NAK" "Not sent,Sent" bitfld.long 0x00 6. " EPRN[6] ,RX endpoint 6 NAK" "Not sent,Sent" bitfld.long 0x00 5. " EPRN[5] ,RX endpoint 5 NAK" "Not sent,Sent" bitfld.long 0x00 4. " EPRN[4] ,RX endpoint 4 NAK" "Not sent,Sent" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX endpoint 3 NAK" "Not sent,Sent" bitfld.long 0x00 2. " EPRN[2] ,RX endpoint 2 NAK" "Not sent,Sent" bitfld.long 0x00 1. " EPRN[1] ,RX endpoint 1 NAK" "Not sent,Sent" bitfld.long 0x00 0. " EPRN[0] ,RX endpoint 0 NAK" "Not sent,Sent" line.long 0x04 "HSIC_ENDPTNAKEN,Endpoint NAK Enable" bitfld.long 0x04 23. " EPTNE[7] ,TX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 22. " EPTNE[6] ,TX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 21. " EPTNE[5] ,TX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 20. " EPTNE[4] ,TX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTNE[3] ,TX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 18. " EPTNE[2] ,TX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 17. " EPTNE[1] ,TX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 16. " EPTNE[0] ,TX endpoint 0 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRNE[7] ,RX endpoint 7 NAK enable" "Disabled,Enabled" bitfld.long 0x04 6. " EPRNE[6] ,RX endpoint 6 NAK enable" "Disabled,Enabled" bitfld.long 0x04 5. " EPRNE[5] ,RX endpoint 5 NAK enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX endpoint 4 NAK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX endpoint 2 NAK enable" "Disabled,Enabled" bitfld.long 0x04 1. " EPRNE[1] ,RX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX endpoint 0 NAK" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "HSIC_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Controls the default port-routing control logic (To which host controller ports are routed)" "Classic,This" textline " " if (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B30000+0x104))&0x10)==0x10) group.long 0x184++0x03 line.long 0x00 "HSIC_PORTSC1,Port Status & Control" bitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " bitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" elif (((per.l(ad:0x30B30000+0x1A8))&0x03)==0x03)&&(((per.l(ad:0x30B30000+0x104))&0x10)==0x00) group.long 0x184++0x03 line.long 0x00 "HSIC_PORTSC1,Port Status & Control" bitfld.long 0x00 25. 30.--31. " PTS ,PTS" "UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." rbitfld.long 0x00 29. " STS ,Serial transceiver select" "Parallel interface signals,Serial interface engine" bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..." textline " " textline " " bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on Over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Off,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Indicates that an internal companion controller owns and controls the port" "Not owned,Owned" textline " " rbitfld.long 0x00 12. " PP ,Port power" "Off,On" rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High-Speed port" "Low-speed mode,High-speed mode" bitfld.long 0x00 8. " PR ,Port reset" "Not reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active" textline " " eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" else hgroup.long 0x184++0x03 hide.long 0x00 "HSIC_PORTSC1,Port Status & Control" textline " " textline " " textline " " textline " " textline " " endif textline " " hgroup.long 0x1A4++0x03 hide.long 0x00 "HSIC_OTGSC,On-The-Go Status & Control" group.long 0x1A8++0x03 line.long 0x00 "HSIC_USBMODE,USB Device Mode" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,,Host controller" hgroup.long 0x1AC++0x13 hide.long 0x00 "HSIC_ENDPTSETUPSTAT,Endpoint Setup Status" hide.long 0x04 "HSIC_ENDPTPRIME,Endpoint Prime" hide.long 0x08 "HSIC_ENDPTFLUSH,Endpoint Flush" hide.long 0x0C "HSIC_ENDPTSTAT,Endpoint Status" hide.long 0x10 "HSIC_ENDPTCOMPLETE,Endpoint Complete" textline " " group.long 0x1C0++0x03 line.long 0x00 "HSIC_ENDPTCTRL0,Endpoint Control0" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX endpoint" "Control,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" textline " " hgroup.long 0x1C4++0x03 hide.long 0x00 "HSIC_ENDPTCTRL1,Endpoint Control 1" hgroup.long 0x1C8++0x03 hide.long 0x00 "HSIC_ENDPTCTRL2,Endpoint Control 2" hgroup.long 0x1CC++0x03 hide.long 0x00 "HSIC_ENDPTCTRL3,Endpoint Control 3" hgroup.long 0x1D0++0x03 hide.long 0x00 "HSIC_ENDPTCTRL4,Endpoint Control 4" hgroup.long 0x1D4++0x03 hide.long 0x00 "HSIC_ENDPTCTRL5,Endpoint Control 5" hgroup.long 0x1D8++0x03 hide.long 0x00 "HSIC_ENDPTCTRL6,Endpoint Control 6" hgroup.long 0x1DC++0x03 hide.long 0x00 "HSIC_ENDPTCTRL7,Endpoint Control 7" width 0x0B tree.end tree.end tree.end tree.open "GPT (General Purpose Timer)" tree "GPT1" base ad:0x302D0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,GPT Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Compare" bitfld.long 0x00 30. " F02 ,Force output compare channel 2" "No effect,Compare" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Compare" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" textline " " bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral clock,High frequency,External clock,Low frequency,Crystal oscillator,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,GPT enable mode" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,GPT Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler" line.long 0x08 "SR,GPT Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,GPT Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,GPT Output Compare Register 1" line.long 0x14 "OCR2,GPT Output Compare Register 2" line.long 0x18 "OCR3,GPT Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,GPT Input Capture Register 1" line.long 0x04 "ICR2,GPT Input Capture Register 2" line.long 0x08 "CNT,GPT Counter Register" width 0x0B tree.end tree "GPT2" base ad:0x302E0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,GPT Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Compare" bitfld.long 0x00 30. " F02 ,Force output compare channel 2" "No effect,Compare" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Compare" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" textline " " bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral clock,High frequency,External clock,Low frequency,Crystal oscillator,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,GPT enable mode" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,GPT Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler" line.long 0x08 "SR,GPT Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,GPT Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,GPT Output Compare Register 1" line.long 0x14 "OCR2,GPT Output Compare Register 2" line.long 0x18 "OCR3,GPT Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,GPT Input Capture Register 1" line.long 0x04 "ICR2,GPT Input Capture Register 2" line.long 0x08 "CNT,GPT Counter Register" width 0x0B tree.end tree "GPT3" base ad:0x302F0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,GPT Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Compare" bitfld.long 0x00 30. " F02 ,Force output compare channel 2" "No effect,Compare" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Compare" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" textline " " bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral clock,High frequency,External clock,Low frequency,Crystal oscillator,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,GPT enable mode" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,GPT Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler" line.long 0x08 "SR,GPT Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,GPT Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,GPT Output Compare Register 1" line.long 0x14 "OCR2,GPT Output Compare Register 2" line.long 0x18 "OCR3,GPT Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,GPT Input Capture Register 1" line.long 0x04 "ICR2,GPT Input Capture Register 2" line.long 0x08 "CNT,GPT Counter Register" width 0x0B tree.end tree "GPT4" base ad:0x30300000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,GPT Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Compare" bitfld.long 0x00 30. " F02 ,Force output compare channel 2" "No effect,Compare" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Compare" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse" textline " " bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral clock,High frequency,External clock,Low frequency,Crystal oscillator,?..." textline " " bitfld.long 0x00 5. " STOPEN ,GPT stop mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,GPT enable mode" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,GPT Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler" line.long 0x08 "SR,GPT Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,GPT Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,GPT Output Compare Register 1" line.long 0x14 "OCR2,GPT Output Compare Register 2" line.long 0x18 "OCR3,GPT Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,GPT Input Capture Register 1" line.long 0x04 "ICR2,GPT Input Capture Register 2" line.long 0x08 "CNT,GPT Counter Register" width 0x0B tree.end tree.end tree.open "FTM (Flextimer)" tree "FTM1" base ad:0x30640000 width 10. endian.be if (((per.l.be(ad:0x30640000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "Not overflowed,Overflowed" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,?..." bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "Not overflowed,Overflowed" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,?..." rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" textline " " if ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0xC))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x14))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x1C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x24))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x2C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x34))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x3C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==0x10)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x44))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30640000))&0x20)==0x20)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30640000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30640000))&0x20)==0x00)&&(((per.l.be(ad:0x30640000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" textline " " hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l.be(ad:0x30640000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" textline " " bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" textline " " bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" textline " " if (((per.l.be(ad:0x30640000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" textline " " bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" textline " " bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" textline " " bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" textline " " bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" textline " " bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" textline " " bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" rbitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif textline " " group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l.be(ad:0x30640000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" textline " " bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" textline " " bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif sif !cpuis("IMX8DV*") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l.be(ad:0x30640000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" textline " " bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" textline " " bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" textline " " bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" textline " " bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" textline " " bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" textline " " bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" textline " " bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" textline " " bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endian.le width 0x0B tree.end tree "FTM2" base ad:0x30650000 width 10. endian.be if (((per.l.be(ad:0x30650000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "Not overflowed,Overflowed" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,?..." bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "Not overflowed,Overflowed" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,?..." rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" textline " " if ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0xC))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x14))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x01)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x05)==0x04)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x1C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x24))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x100)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x500)==0x400)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x2C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x34))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x10000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x50000)==0x40000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x3C))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==0x10)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x44))&0x30)==(0x20||0x30))&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x00)&&(((per.l.be(ad:0x30650000))&0x20)==0x20)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x1000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l.be(ad:0x30650000+0x64))&0x5000000)==0x4000000)&&(((per.l.be(ad:0x30650000))&0x20)==0x00)&&(((per.l.be(ad:0x30650000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" textline " " rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" textline " " hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l.be(ad:0x30650000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" textline " " bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" textline " " bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" textline " " if (((per.l.be(ad:0x30650000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" textline " " bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" textline " " bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" textline " " bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" textline " " bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" textline " " bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" textline " " bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" rbitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif textline " " group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l.be(ad:0x30650000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" textline " " bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" textline " " bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif sif !cpuis("IMX8DV*") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l.be(ad:0x30650000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" textline " " bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" textline " " bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" textline " " bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" textline " " bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" textline " " bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" textline " " bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" textline " " bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" textline " " bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endian.le width 0x0B tree.end tree.end tree.open "PWM (Pulse Width Modulation)" tree "PWM1" base ad:0x30660000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Output set/rollover cleared,Output cleared/rollover set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM2" base ad:0x30670000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Output set/rollover cleared,Output cleared/rollover set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM3" base ad:0x30680000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Output set/rollover cleared,Output cleared/rollover set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM4" base ad:0x30690000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Output set/rollover cleared,Output cleared/rollover set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree.end tree.open "eLCDIF (Enhanced LCD Interface)" tree "eLCDIF1" base ad:0x30730000 width 11. tree "Control Registers" if (((per.l(ad:0x30730000))&0x40300)==0x40200) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x40300) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x200) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x300) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==(0x40000||0x40100)) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30730000))&0x40300)==0x40200) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x40300) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x200) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x300) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==(0x40000||0x40100)) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30730000))&0x40300)==0x40200) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x40300) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x200) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x300) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==(0x40000||0x40100)) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30730000))&0x40300)==0x40200) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x40300) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x200) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==0x300) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30730000))&0x40300)==(0x40000||0x40100)) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x02)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)!=0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x02)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)!=0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x02)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)!=0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)==0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x02)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30730000))&0x120000)!=0x120000)&&(((per.l(ad:0x30730000+0x10))&0x02)==0x00)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif group.long 0x20++0x03 line.long 0x00 "CTRL2,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x24++0x03 line.long 0x00 "CTRL2_SET,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "CTRL2_CLR,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" tree.end width 16. newline group.long 0x30++0x03 line.long 0x00 "TRANSFER_COUNT,Elcdif Horizontal And Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (Pixels) in each horizontal line" group.long 0x40++0x03 line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x03 line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "TIMING,LCD Interface Next Buffer Address Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of clk_dis_lcdifn cycles that the dcn signal is active after cen is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of clk_dis_lcdifn cycles that the dcn signal is active before cen is asserted" hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in clk_dis_lcdifn cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in clk_dis_lcdifn cycles" width 13. tree "VSYNC Mode And Dotclk Mode Control Registers" if (((per.l(ad:0x30730000))&0x20000)==0x20000) group.long 0x70++0x03 line.long 0x00 "VDCTRL0,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x70++0x03 line.long 0x00 "VDCTRL0,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30730000))&0x20000)==0x20000) group.long 0x74++0x03 line.long 0x00 "VDCTRL0_SET,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x74++0x03 line.long 0x00 "VDCTRL0_SET,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30730000))&0x20000)==0x20000) group.long 0x78++0x03 line.long 0x00 "VDCTRL0_CLR,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x78++0x03 line.long 0x00 "VDCTRL0_CLR,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30730000))&0x20000)==0x20000) group.long 0x7C++0x03 line.long 0x00 "VDCTRL0_TOG,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x7C++0x03 line.long 0x00 "VDCTRL0_TOG,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif group.long 0x80++0x03 line.long 0x00 "VDCTRL1,Elcdif VSYNC Mode And Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "VDCTRL2,Elcdif VSYNC Mode And Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of clk_dis_lcdifn cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of clk_dis_lcdifn cycles between two positive or two negative edges of the HSYNC signal" group.long 0xA0++0x03 line.long 0x00 "VDCTRL3,Elcdif VSYNC Mode And Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Internally multiplexed signals" "Separated,Multiplexed" bitfld.long 0x00 28. " VSYNC_ONLY ,Mode of operation" "DOTCLK,VSYNC" hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Wait for this number of clocks from edge of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Wait for this number of clk_dis_lcdifn cycles from the VSYNC edge before starting LCD transactions" group.long 0xB0++0x03 line.long 0x00 "VDCTRL4,Elcdif VSYNC Mode And Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2ns,4ns,6ns,8ns,?..." bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end" "0,1" hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of clk_dis_lcdifn cycles on each horizontal line that carry valid data in DOTCLK mode" tree.end width 10. tree "Digital Video Interface Control Registers" group.long 0xC0++0x03 line.long 0x00 "DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which field 1 ends" hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which field 2 begins" group.long 0xE0++0x03 line.long 0x00 "DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of field1 where first vertical blanking interval starts" hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of field2 where first vertical blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of field2 where second vertical blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of field1 where second vertical blanking interval ends" hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" tree.end width 12. tree "Coefficient Registers" group.long 0x110++0x03 line.long 0x00 "CSC_COEFF0,RGB To Ycbcr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two's complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components in order to convert from ycbcr 4:4:4 to ycbcr 4:2:2 space" "Sample/hold,,INTERSTITIAL,COSITED" group.long 0x120++0x03 line.long 0x00 "CSC_COEFF1,RGB To Ycbcr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two's complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two's complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "CSC_COEFF2,RGB To Ycbcr 4:2:2 CSC Coefficient 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two's complement green multiplier coefficient for cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two's complement red multiplier coefficient for cb" group.long 0x140++0x03 line.long 0x00 "CSC_COEFF3,RGB To Ycbcr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two's complement red multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two's complement blue multiplier coefficient for cb" group.long 0x150++0x03 line.long 0x00 "CSC_COEFF4,RGB To Ycbcr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two's complement blue multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two's complement green multiplier coefficient for cr" tree.end width 15. newline group.long 0x160++0x03 line.long 0x00 "CSC_OFFSET,RGB To Ycbcr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two's complement offset for the cb and cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "CSC_LIMIT,RGB To Ycbcr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of cb and cr after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of cb and cr after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 ycbcr conversion" group.long 0x180++0x03 line.long 0x00 "DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (Most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to elcdif" hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to elcdif" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (Least significant byte) of data written to elcdif" group.long 0x190++0x03 line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x03 line.long 0x00 "STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,ELCDIF presence" "Not present,Present" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x00 29. " LFIFO_FULL ,Read only view of the signals that indicates LCD LFIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Read only view of the signals that indicates LCD LFIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Read only view of the signals that indicates LCD TXFIFO is full" "Not full,Full" newline bitfld.long 0x00 26. " TXFIFO_EMPTY ,Read only view of the signals that indicates LCD TXFIFO is empty" "Not empty,Empty" else bitfld.long 0x00 29. " LFIFO_FULL ,Indicates that LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Indicates that LCD read datapath FIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Indicates that LCD write datapath FIFO is full" "Not full,Full" newline bitfld.long 0x00 26. " TXFIFO_EMPTY ,Indicates that LCD write datapath FIFO is empty" "Not empty,Empty" endif bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in latency buffer" rgroup.long 0x1C0++0x03 line.long 0x00 "VERSION,LCD Interface Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of RTL version" width 8. tree "Debug Registers" rgroup.long 0x1D0++0x03 line.long 0x00 "DEBUG0,LCD Interface Debug 0 Register" bitfld.long 0x00 31. " STREAMING_END_DETECTED ,DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1" bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1" bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,Read only view of internal sync_signals_on_reg signal" "0,1" bitfld.long 0x00 27. " ENABLE ,Read only view of ENABLE signal" "0,1" newline bitfld.long 0x00 26. " HSYNC ,Read only view of HSYNC signal" "0,1" bitfld.long 0x00 25. " VSYNC ,Read only view of VSYNC signal" "0,1" bitfld.long 0x00 24. " CUR_FRAME_TX ,Indicates that the current frame is being transmitted in the VSYNC mode" "0,1" bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "0,1" newline hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation" bitfld.long 0x00 15. " PXP_LCDIF_B0_READY ,Buffer0 ready signal issued by epxp" "0,1" bitfld.long 0x00 14. " PXP_B0_DONE ,Buffer0 done signal issued by elcdif" "0,1" bitfld.long 0x00 13. " PXP_LCDIF_B1_READY ,Buffer1 ready signal issued by epxp" "0,1" newline bitfld.long 0x00 12. " PXP_B1_DONE ,Buffer1 done signal issued by elcdif" "0,1" bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Read only view of the request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1E0++0x03 line.long 0x00 "DEBUG1,LCD Interface Debug 1 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Vertical data counter" rgroup.long 0x1F0++0x03 line.long 0x00 "DEBUG2,LCD Interface Debug 2 Register" rgroup.long 0x270++0x03 line.long 0x00 "DEBUG3,Elcdif Interface Debug 3 Register" bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x280++0x03 line.long 0x00 "DEBUG4,Elcdif Interface Debug 4 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Current AS state of the horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Current AS state of the vertical data counter" rgroup.long 0x290++0x03 line.long 0x00 "DEBUG5,Elcdif Interface Debug 5 Register" tree.end width 15. tree "AS Registers" group.long 0x200++0x03 line.long 0x00 "THRES,Elcdif Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,This value should be set to a value of pixels from 0 to 511" hexmask.long.word 0x00 0.--8. 1. " PANIC ,Panic level" group.long 0x210++0x03 line.long 0x00 "AS_CTRL,Elcdif AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,LCDIF work as sync mode with CSI input" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,CSI VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 29. " CSI_VSYNC_MODE ,Vsync generate mode" "Internal,External" bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Interrupt when LCDIF lock with CSI vsync input" "Disabled,Enabled" newline bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,Vsync generate mode" "Internal,External" bitfld.long 0x00 23. " PS_DISABLE ,LCDIF will disable PS buffer data" "No,Yes" bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,How to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 20. " ALPHA_INVERT ,Alpha value inversion" "Not inverted,Inverted" newline bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL" bitfld.long 0x00 4.--7. " FORMAT ,Indicates the input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality for alpha surface" "Disabled,Enabled" newline bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Alpha value construction" "Embedded,Override,Multiply,Rops" bitfld.long 0x00 0. " AS_ENABLE ,Fetching AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer" group.long 0x230++0x03 line.long 0x00 "AS_NEXT_BUF,LCDIF1_AS_NEXT_BUF" group.long 0x240++0x03 line.long 0x00 "AS_CLRKEYLOW,Elcdif Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "AS_CLRKEYHIGH,Elcdif Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "SYNC_DELAY,LCD Working Insync Mode With CSI For VSYNC Delay" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" tree.end width 0x0B tree.end tree "eLCDIF2" base ad:0x30734000 width 11. tree "Control Registers" if (((per.l(ad:0x30734000))&0x40300)==0x40200) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x40300) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x200) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x300) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==(0x40000||0x40100)) group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x0++0x03 line.long 0x00 "RL,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30734000))&0x40300)==0x40200) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x40300) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x200) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x300) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==(0x40000||0x40100)) group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x4++0x03 line.long 0x00 "RL_SET,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30734000))&0x40300)==0x40200) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x40300) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x200) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x300) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==(0x40000||0x40100)) group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0x8++0x03 line.long 0x00 "RL_CLR,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if (((per.l(ad:0x30734000))&0x40300)==0x40200) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x40300) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x200) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==0x300) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "Lower,Upper" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" elif (((per.l(ad:0x30734000))&0x40300)==(0x40000||0x40100)) group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" else group.long 0xC++0x03 line.long 0x00 "RL_TOG,Elcdif General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the elcdif" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,Ycbcr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big endian,Half-words,Bytes/half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD data bus transfer width" "16bit,8bit,18bit,24bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16bit,8bit,18bit,24bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to ycbcr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between elcdif and epxp" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,Elcdif mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" newline bitfld.long 0x00 0. " RUN ,Transferring data between the soc and the display" "Not running,Running" endif if ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x02)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)!=0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x10++0x03 line.long 0x00 "CTRL1,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x02)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)!=0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x14++0x03 line.long 0x00 "CTRL1_SET,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x02)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)!=0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x18++0x03 line.long 0x00 "CTRL1_CLR,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif if ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)==0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x02)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" elif ((((per.l(ad:0x30734000))&0x120000)!=0x120000)&&(((per.l(ad:0x30734000+0x10))&0x02)==0x00)) group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWN,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" else group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,Elcdif General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_RD_E,LCD_WR_RWN" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the elcdif master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt request by the elcdif block" "Not requested,Requested" newline bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by elcdif block" "Not required,Required" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (Lfifo), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x00 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the elcdif block" "Not requested,Requested" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the elcdif block when" "Not requested,Requested" newline bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the elcdif block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the elcdif block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "No reset,Reset" endif group.long 0x20++0x03 line.long 0x00 "CTRL2,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x24++0x03 line.long 0x00 "CTRL2_SET,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "CTRL2_CLR,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" group.long 0x2C++0x03 line.long 0x00 "CTRL2_TOG,Elcdif General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that elcdif should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" tree.end width 16. newline group.long 0x30++0x03 line.long 0x00 "TRANSFER_COUNT,Elcdif Horizontal And Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (Pixels) in each horizontal line" group.long 0x40++0x03 line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x03 line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "TIMING,LCD Interface Next Buffer Address Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of clk_dis_lcdifn cycles that the dcn signal is active after cen is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of clk_dis_lcdifn cycles that the dcn signal is active before cen is asserted" hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in clk_dis_lcdifn cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in clk_dis_lcdifn cycles" width 13. tree "VSYNC Mode And Dotclk Mode Control Registers" if (((per.l(ad:0x30734000))&0x20000)==0x20000) group.long 0x70++0x03 line.long 0x00 "VDCTRL0,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x70++0x03 line.long 0x00 "VDCTRL0,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30734000))&0x20000)==0x20000) group.long 0x74++0x03 line.long 0x00 "VDCTRL0_SET,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x74++0x03 line.long 0x00 "VDCTRL0_SET,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30734000))&0x20000)==0x20000) group.long 0x78++0x03 line.long 0x00 "VDCTRL0_CLR,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x78++0x03 line.long 0x00 "VDCTRL0_CLR,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif if (((per.l(ad:0x30734000))&0x20000)==0x20000) group.long 0x7C++0x03 line.long 0x00 "VDCTRL0_TOG,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" else group.long 0x7C++0x03 line.long 0x00 "VDCTRL0_TOG,Elcdif VSYNC Mode And Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Disabled,Enabled" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Not inverted,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" endif group.long 0x80++0x03 line.long 0x00 "VDCTRL1,Elcdif VSYNC Mode And Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "VDCTRL2,Elcdif VSYNC Mode And Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of clk_dis_lcdifn cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of clk_dis_lcdifn cycles between two positive or two negative edges of the HSYNC signal" group.long 0xA0++0x03 line.long 0x00 "VDCTRL3,Elcdif VSYNC Mode And Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Internally multiplexed signals" "Separated,Multiplexed" bitfld.long 0x00 28. " VSYNC_ONLY ,Mode of operation" "DOTCLK,VSYNC" hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Wait for this number of clocks from edge of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Wait for this number of clk_dis_lcdifn cycles from the VSYNC edge before starting LCD transactions" group.long 0xB0++0x03 line.long 0x00 "VDCTRL4,Elcdif VSYNC Mode And Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2ns,4ns,6ns,8ns,?..." bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end" "0,1" hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of clk_dis_lcdifn cycles on each horizontal line that carry valid data in DOTCLK mode" tree.end width 10. tree "Digital Video Interface Control Registers" group.long 0xC0++0x03 line.long 0x00 "DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which field 1 ends" hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which field 2 begins" group.long 0xE0++0x03 line.long 0x00 "DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of field1 where first vertical blanking interval starts" hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of field2 where first vertical blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of field2 where second vertical blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of field1 where second vertical blanking interval ends" hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" tree.end width 12. tree "Coefficient Registers" group.long 0x110++0x03 line.long 0x00 "CSC_COEFF0,RGB To Ycbcr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two's complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components in order to convert from ycbcr 4:4:4 to ycbcr 4:2:2 space" "Sample/hold,,INTERSTITIAL,COSITED" group.long 0x120++0x03 line.long 0x00 "CSC_COEFF1,RGB To Ycbcr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two's complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two's complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "CSC_COEFF2,RGB To Ycbcr 4:2:2 CSC Coefficient 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two's complement green multiplier coefficient for cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two's complement red multiplier coefficient for cb" group.long 0x140++0x03 line.long 0x00 "CSC_COEFF3,RGB To Ycbcr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two's complement red multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two's complement blue multiplier coefficient for cb" group.long 0x150++0x03 line.long 0x00 "CSC_COEFF4,RGB To Ycbcr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two's complement blue multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two's complement green multiplier coefficient for cr" tree.end width 15. newline group.long 0x160++0x03 line.long 0x00 "CSC_OFFSET,RGB To Ycbcr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two's complement offset for the cb and cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "CSC_LIMIT,RGB To Ycbcr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of cb and cr after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of cb and cr after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 ycbcr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 ycbcr conversion" group.long 0x180++0x03 line.long 0x00 "DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (Most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to elcdif" hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to elcdif" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (Least significant byte) of data written to elcdif" group.long 0x190++0x03 line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x03 line.long 0x00 "STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,ELCDIF presence" "Not present,Present" sif cpuis("IMX7DUAL-CM4")||cpuis("IMX7DUAL-CA7") bitfld.long 0x00 29. " LFIFO_FULL ,Read only view of the signals that indicates LCD LFIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Read only view of the signals that indicates LCD LFIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Read only view of the signals that indicates LCD TXFIFO is full" "Not full,Full" newline bitfld.long 0x00 26. " TXFIFO_EMPTY ,Read only view of the signals that indicates LCD TXFIFO is empty" "Not empty,Empty" else bitfld.long 0x00 29. " LFIFO_FULL ,Indicates that LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Indicates that LCD read datapath FIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Indicates that LCD write datapath FIFO is full" "Not full,Full" newline bitfld.long 0x00 26. " TXFIFO_EMPTY ,Indicates that LCD write datapath FIFO is empty" "Not empty,Empty" endif bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in latency buffer" rgroup.long 0x1C0++0x03 line.long 0x00 "VERSION,LCD Interface Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of RTL version" width 8. tree "Debug Registers" rgroup.long 0x1D0++0x03 line.long 0x00 "DEBUG0,LCD Interface Debug 0 Register" bitfld.long 0x00 31. " STREAMING_END_DETECTED ,DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1" bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1" bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,Read only view of internal sync_signals_on_reg signal" "0,1" bitfld.long 0x00 27. " ENABLE ,Read only view of ENABLE signal" "0,1" newline bitfld.long 0x00 26. " HSYNC ,Read only view of HSYNC signal" "0,1" bitfld.long 0x00 25. " VSYNC ,Read only view of VSYNC signal" "0,1" bitfld.long 0x00 24. " CUR_FRAME_TX ,Indicates that the current frame is being transmitted in the VSYNC mode" "0,1" bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "0,1" newline hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation" bitfld.long 0x00 15. " PXP_LCDIF_B0_READY ,Buffer0 ready signal issued by epxp" "0,1" bitfld.long 0x00 14. " PXP_B0_DONE ,Buffer0 done signal issued by elcdif" "0,1" bitfld.long 0x00 13. " PXP_LCDIF_B1_READY ,Buffer1 ready signal issued by epxp" "0,1" newline bitfld.long 0x00 12. " PXP_B1_DONE ,Buffer1 done signal issued by elcdif" "0,1" bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Read only view of the request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1E0++0x03 line.long 0x00 "DEBUG1,LCD Interface Debug 1 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Vertical data counter" rgroup.long 0x1F0++0x03 line.long 0x00 "DEBUG2,LCD Interface Debug 2 Register" rgroup.long 0x270++0x03 line.long 0x00 "DEBUG3,Elcdif Interface Debug 3 Register" bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x280++0x03 line.long 0x00 "DEBUG4,Elcdif Interface Debug 4 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Current AS state of the horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Current AS state of the vertical data counter" rgroup.long 0x290++0x03 line.long 0x00 "DEBUG5,Elcdif Interface Debug 5 Register" tree.end width 15. tree "AS Registers" group.long 0x200++0x03 line.long 0x00 "THRES,Elcdif Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,This value should be set to a value of pixels from 0 to 511" hexmask.long.word 0x00 0.--8. 1. " PANIC ,Panic level" group.long 0x210++0x03 line.long 0x00 "AS_CTRL,Elcdif AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,LCDIF work as sync mode with CSI input" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,CSI VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 29. " CSI_VSYNC_MODE ,Vsync generate mode" "Internal,External" bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Interrupt when LCDIF lock with CSI vsync input" "Disabled,Enabled" newline bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,Vsync generate mode" "Internal,External" bitfld.long 0x00 23. " PS_DISABLE ,LCDIF will disable PS buffer data" "No,Yes" bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,How to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "No swap,Big endinan,Hafl-words,Bytes/half-word" bitfld.long 0x00 20. " ALPHA_INVERT ,Alpha value inversion" "Not inverted,Inverted" newline bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL" bitfld.long 0x00 4.--7. " FORMAT ,Indicates the input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality for alpha surface" "Disabled,Enabled" newline bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Alpha value construction" "Embedded,Override,Multiply,Rops" bitfld.long 0x00 0. " AS_ENABLE ,Fetching AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer" group.long 0x230++0x03 line.long 0x00 "AS_NEXT_BUF,LCDIF1_AS_NEXT_BUF" group.long 0x240++0x03 line.long 0x00 "AS_CLRKEYLOW,Elcdif Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "AS_CLRKEYHIGH,Elcdif Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "SYNC_DELAY,LCD Working Insync Mode With CSI For VSYNC Delay" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" tree.end width 0x0B tree.end tree.end tree.open "CSI (CMOS Sensor Interface)" tree "CSI1" base ad:0x30710000 width 19. if (((per.l(ad:0x30710000))&0x510)==0x00) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30710000))&0x510)==0x10) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC polarity select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30710000))&0x510)==0x100) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30710000))&0x510)==0x110) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC polarity select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30710000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst type of DMA transfer from RXFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst type of DMA transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit frame counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame count reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RXFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA request enable for RXFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA request enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RXFF_LEVEL ,Number of data words after a RXFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit sensor mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy zero packing enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic error correction enable" "Disabled,Enabled" textline " " hgroup.long 0x0C++0x07 hide.long 0x00 "CSISTATFIFO,CSI Statistic FIFO Register" in hide.long 0x04 "CSIRFIFO,CSI RX FIFO Register" in textline " " group.long 0x14++0x07 line.long 0x00 "CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "No error,Error" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO overrun interrupt status" "Not overflowed,Overflowed" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO overrun interrupt status" "Not overflowed,Overflowed" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA transfer done from STATFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA transfer done in frame buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA transfer done in frame buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of frame (Eof) interrupt status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of frame interrupt status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR field 2 interrupt status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR field 1 interrupt status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change of field interrupt status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse error interrupt status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR error interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RXFIFO" "Not ready,Ready" textline " " group.long 0x20++0x2F line.long 0x00 "CSIDMASA_STATFIFO,CSI DMA Start Address Register - For STATFIFO" hexmask.long 0x00 2.--31. 0x04 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - For STATFIFO" line.long 0x08 "CSIDMASA_FB1,CSI DMA Start Address Register - For Frame Buffer1" hexmask.long 0x08 2.--31. 0x04 " DMA_START_ADDR_FB1 ,DMA start address in frame buffer1" line.long 0x0C "CSIDMASA_FB2,CSI DMA Transfer Size Register - For Frame Buffer2" hexmask.long 0x0C 2.--31. 0x04 " DMA_START_ADDR_FB2 ,DMA start address in frame buffer2" line.long 0x10 "CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 16.--31. 1. " DEINTERLACE_STRIDE ,DEINTERLACE STRIDE" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" rbitfld.long 0x00 25.--30. " MIPI_DATA_FORMAT ,Image data format" ",,,,,,,,,,,,,,,,,,,,,,,,YUV420 (8-bit),YUV420 (10-bit),YUV420 (8-bit legacy),,YUV420 (8-bit CSPS),YUV420 (10-bit CSPS),YUV422 (8-bit),YUV422 (10-bit),,,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,User defined 1,User defined 2,User defined 3,User defined 4,User defined 5,User defined 6,User defined 7,User defined 8,?..." bitfld.long 0x00 24. " LINE_STRIDE_EN ,LINE_STRIDE_EN" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DATA_FROM_MIPI ,DATA_FROM_MIPI" "Parallel sensor,MIPI" bitfld.long 0x00 21. " MIPI_YU_SWAP ,MIPI_YU_SWAP" "Not swapped,Swapped" bitfld.long 0x00 20. " MIPI_DOUBLE_CMPNT ,Double component per clock cycle in YUV422 formats" "Single,Double" textline " " bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],Data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "Disabled,Enabled" bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "Fifo_full_level,Hburst_length" textline " " bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt Enable(In interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (Interlace mode)" "Disabled,Enabled" bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "VSYNC,First data" textline " " bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Disabled,Enabled" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method when input is TVDECODER or standard CCIR656 video" "Disabled,Enabled" width 0x0B tree.end sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) tree "CSI2" base ad:0x30718000 width 19. if (((per.l(ad:0x30718000))&0x510)==0x00) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30718000))&0x510)==0x10) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC polarity select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30718000))&0x510)==0x100) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30718000))&0x510)==0x110) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC polarity select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x30718000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst type of DMA transfer from RXFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst type of DMA transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit frame counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame count reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RXFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA request enable for RXFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA request enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RXFF_LEVEL ,Number of data words after a RXFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit sensor mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy zero packing enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic error correction enable" "Disabled,Enabled" textline " " hgroup.long 0x0C++0x07 hide.long 0x00 "CSISTATFIFO,CSI Statistic FIFO Register" in hide.long 0x04 "CSIRFIFO,CSI RX FIFO Register" in textline " " group.long 0x14++0x07 line.long 0x00 "CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "No error,Error" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO overrun interrupt status" "Not overflowed,Overflowed" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO overrun interrupt status" "Not overflowed,Overflowed" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA transfer done from STATFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA transfer done in frame buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA transfer done in frame buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of frame (Eof) interrupt status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of frame interrupt status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR field 2 interrupt status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR field 1 interrupt status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change of field interrupt status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse error interrupt status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR error interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RXFIFO" "Not ready,Ready" textline " " group.long 0x20++0x2F line.long 0x00 "CSIDMASA_STATFIFO,CSI DMA Start Address Register - For STATFIFO" hexmask.long 0x00 2.--31. 0x04 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - For STATFIFO" line.long 0x08 "CSIDMASA_FB1,CSI DMA Start Address Register - For Frame Buffer1" hexmask.long 0x08 2.--31. 0x04 " DMA_START_ADDR_FB1 ,DMA start address in frame buffer1" line.long 0x0C "CSIDMASA_FB2,CSI DMA Transfer Size Register - For Frame Buffer2" hexmask.long 0x0C 2.--31. 0x04 " DMA_START_ADDR_FB2 ,DMA start address in frame buffer2" line.long 0x10 "CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 16.--31. 1. " DEINTERLACE_STRIDE ,DEINTERLACE STRIDE" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" rbitfld.long 0x00 25.--30. " MIPI_DATA_FORMAT ,Image data format" ",,,,,,,,,,,,,,,,,,,,,,,,YUV420 (8-bit),YUV420 (10-bit),YUV420 (8-bit legacy),,YUV420 (8-bit CSPS),YUV420 (10-bit CSPS),YUV422 (8-bit),YUV422 (10-bit),,,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,User defined 1,User defined 2,User defined 3,User defined 4,User defined 5,User defined 6,User defined 7,User defined 8,?..." bitfld.long 0x00 24. " LINE_STRIDE_EN ,LINE_STRIDE_EN" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DATA_FROM_MIPI ,DATA_FROM_MIPI" "Parallel sensor,MIPI" bitfld.long 0x00 21. " MIPI_YU_SWAP ,MIPI_YU_SWAP" "Not swapped,Swapped" bitfld.long 0x00 20. " MIPI_DOUBLE_CMPNT ,Double component per clock cycle in YUV422 formats" "Single,Double" textline " " bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],Data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "Disabled,Enabled" bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "Fifo_full_level,Hburst_length" textline " " bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt Enable(In interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (Interlace mode)" "Disabled,Enabled" bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "VSYNC,First data" textline " " bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Disabled,Enabled" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method when input is TVDECODER or standard CCIR656 video" "Disabled,Enabled" width 0x0B tree.end endif tree.end tree "MIPI_DSI (MIPI DSI Host Controller)" base ad:0x30760000 width 12. rgroup.long 0x00++0x0B line.long 0x00 "VERSION,Version Register" line.long 0x04 "STATUS,STATUS" bitfld.long 0x04 31. " PLLSTABLE ,D-PHY PLL generates stable byteclk" "Not stable,Stable" bitfld.long 0x04 20. " SWRSTRLS ,Specifies the software reset status" "Reset,Release" bitfld.long 0x04 16. " DIRECTION ,Specifies the data direction indicator" "Forward,Backward" bitfld.long 0x04 10. " TXREADYHSCLK ,Specifies the HS clock ready at clock lane" "Not ready,Ready" textline " " bitfld.long 0x04 9. " ULPSCLK ,Specifies the ULPS indicator at clock lane" "No ULPS,ULPS" bitfld.long 0x04 8. " STOPSTATECLK ,Specifies the stop state indicator at clock lane" "No stop,Stop" bitfld.long 0x04 5. " ULPSDAT[1] ,Specifies the ULPS indicator at data lane 1" "No ULPS,ULPS" bitfld.long 0x04 4. " ULPSDAT[0] ,Specifies the ULPS indicator at data lane 0" "No ULPS,ULPS" textline " " bitfld.long 0x04 1. " STOPSTATEDAT[1] ,Specifies the stop state indicator at data lane 1" "No stop,Stop" bitfld.long 0x04 0. " STOPSTATEDAT[0] ,Specifies the stop state indicator at data lane 0" "No stop,Stop" line.long 0x08 "RGB_STATUS,RGB Status Register" bitfld.long 0x08 31. " CMDMODE_INSEL ,Specifies the command mode input selection" "RGB video interface,S-i80 interface" bitfld.long 0x08 12. " RGBSTATE[12] ,RGB packetize FSM status bit [12]" "No effect,NHOLD" bitfld.long 0x08 11. " RGBSTATE[11] ,RGB packetize FSM status bit [11]" "No effect,EOT" bitfld.long 0x08 10. " RGBSTATE[10] ,RGB packetize FSM status bit [10]" "No effect,HFP" textline " " bitfld.long 0x08 9. " RGBSTATE[9] ,RGB packetize FSM status bit [9]" "No effect,NULL" bitfld.long 0x08 8. " RGBSTATE[8] ,RGB packetize FSM status bit [8]" "No effect,RGB" bitfld.long 0x08 7. " RGBSTATE[7] ,RGB packetize FSM status bit [7]" "No effect,HBP" bitfld.long 0x08 6. " RGBSTATE[6] ,RGB packetize FSM status bit [6]" "No effect,HSE" textline " " bitfld.long 0x08 5. " RGBSTATE[5] ,RGB packetize FSM status bit [5]" "No effect,HSA" bitfld.long 0x08 4. " RGBSTATE[4] ,RGB packetize FSM status bit [4]" "No effect,HSS" bitfld.long 0x08 3. " RGBSTATE[3] ,RGB packetize FSM status bit [3]" "No effect,VSE" bitfld.long 0x08 2. " RGBSTATE[2] ,RGB packetize FSM status bit [2]" "No effect,VSYS" textline " " bitfld.long 0x08 1. " RGBSTATE[1] ,RGB packetize FSM status bit [1]" "No effect,STOP" bitfld.long 0x08 0. " RGBSTATE[0] ,RGB packetize FSM status bit [0]" "No effect,IDLE" group.long 0x0C++0x2F line.long 0x00 "SWRST,SWRST" bitfld.long 0x00 16. " FUNCRST ,Specifies the software reset" "Standby,Reset" bitfld.long 0x00 0. " SWRST ,Specifies the software reset" "Standby,Reset" line.long 0x04 "CLKCTRL,Clock Control Register" bitfld.long 0x04 31. " TXREQUESTHSCLK ,Specifies the HS clock request for HS transfer at clock lane" "No,Yes" bitfld.long 0x04 29. " DPHY_SEL ,D-PHY select" "1.5 Gbps,1 Gbps" bitfld.long 0x04 28. " ESCCLKEN ,Enables the escape clock generating prescaler" "Disabled,Enabled" bitfld.long 0x04 27. " PLLBYPASS ,Sets the pllbypass signal connected to D-PHY module input for selecting clock source bit" "PLL output,External serial clock" textline " " bitfld.long 0x04 25.--26. " BYTECLKSRC ,Selects byte clock source" "D-PHY PLL,?..." bitfld.long 0x04 24. " BYTECLKEN ,Enables byte clock" "Disabled,Enabled" bitfld.long 0x04 21. " LANEESCCLKEN[2] ,Enables escape clock for data lane 1" "Disabled,Enabled" bitfld.long 0x04 20. " LANEESCCLKEN[1] ,Enables escape clock for data lane 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " LANEESCCLKEN[0] ,Enables escape clock for clock lane" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " ESCPRESCALER ,Specifies the escape clock prescaler value" line.long 0x08 "TIMEOUT,TIMEOUT" hexmask.long.byte 0x08 16.--23. 1. " BTAOUT ,Specifies the timer for BTA" hexmask.long.word 0x08 0.--15. 1. " LPDRTOUT ,Specifies the timer for LP rx mode timeout" textline " " line.long 0x0C "CONFIG,CONFIG" bitfld.long 0x0C 31. " NON_CONTINUOUS_CLOCK_LANE ,Non-continuous clock mode" "Disabled,Enabled" bitfld.long 0x0C 30. " CLKLANE_STOP_START ,PHY clock lane on / off for ESD" "Disabled,Enabled" textline " " bitfld.long 0x0C 29. " MFLUSH_VS ,Auto flush of MD FIFO using vsync pulse" "Disabled,Enabled" bitfld.long 0x0C 28. " EOT_R03 ,Disables eot packet in HS mode" "No,Yes" textline " " bitfld.long 0x0C 27. " SYNCINFORM ,Selects sync pulse or event mode in video mode" "Event,Pulse" bitfld.long 0x0C 26. " BURSTMODE ,Selects burst mode in video mode" "Non-burst,Burst" textline " " bitfld.long 0x0C 25. " VIDEOMODE ,Specifies display configuration" "0,1" bitfld.long 0x0C 24. " AUTOMODE ,Specifies auto vertical count mode" "Configuration,Auto" textline " " bitfld.long 0x0C 23. " HSEDISABLEMODE ,Transfers hsync end packet in vsync pulse and vporch area" "Disabled,Enabled" bitfld.long 0x0C 22. " HFPDISABLEMODE ,Specifies HFP disable mode" "No,Yes" textline " " bitfld.long 0x0C 21. " HBPDISABLEMODE ,Specifies HBP disable mode" "No,Yes" bitfld.long 0x0C 20. " HSADISABLEMODE ,Specifies HSA disable mode" "No,Yes" textline " " bitfld.long 0x0C 18.--19. " MAINVC ,Specifies virtual channel number for main display" "0,1,2,3" bitfld.long 0x0C 16.--17. " SUBVC ,Specifies virtual channel number for sub display" "0,1,2,3" textline " " bitfld.long 0x0C 12.--14. " MAINPIXFORMAT ,Specifies pixel stream format for main display" "3 Bpp,8 Bpp,12 Bpp,16 Bpp,16-bit Rgb(565),18-bit Rgb(666:packed pixel Stream),18-bit Rgb(666:loosely packed pixel stream),24-bit Rgb(888)" bitfld.long 0x0C 8.--10. " SUBPIXFORMAT ,Specifies pixel stream format for main display" "3 Bpp,8 Bpp,12 Bpp,16 Bpp,16-bit Rgb(565),18-bit Rgb(666:packed pixel Stream),18-bit Rgb(666:loosely packed pixel stream),24-bit Rgb(888)" textline " " bitfld.long 0x0C 5.--6. " NUMOFDATLANE ,Sets the data lane number" "Data lane 0,Data lane 0 ~ 1,?..." bitfld.long 0x0C 2. " LANEEN[2] ,Data lane 1 enabler" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " LANEEN[1] ,Data lane 0 enabler" "Disabled,Enabled" bitfld.long 0x0C 0. " LANEEN[0] ,Clock lane enabler" "Disabled,Enabled" textline " " line.long 0x10 "ESCMODE,Escape Mode Register" hexmask.long.word 0x10 21.--31. 1. " STOPSTATE_CNT ,Specifies the interval value between transmitting read packet (Or write set_tear_on command) and BTA request" bitfld.long 0x10 20. " FORCESTOPSTATE ,Forces stopstate for D-PHY" "Not forced,Forced" bitfld.long 0x10 16. " FORCEBTA ,Forces bus turn around" "Not forced,Forced" bitfld.long 0x10 7. " CMDLPDT ,Specifies LPDT transfers command in SFR FIFO" "HS mode,LP mode" textline " " bitfld.long 0x10 6. " TXLPDT ,Specifies data transmission in LP mode (All data transfer in LPDT)" "HS mode,LP mode" bitfld.long 0x10 4. " TXTRIGGERRST ,Specifies remote reset trigger function" "0,1" bitfld.long 0x10 3. " TXULPSDAT ,Specifies ULPS request for data lane" "0,1" bitfld.long 0x10 2. " TXULPSEXIT ,Specifies ULPS exit request for data lane" "0,1" textline " " bitfld.long 0x10 1. " TXULPSCLK ,Specifies ULPS request for clock lane" "0,1" bitfld.long 0x10 0. " TXULPSCLKEXIT ,Specifies ULPS exit request for clock lane" "0,1" line.long 0x14 "MDRESOL,Main Display Image Resolution Register" bitfld.long 0x14 31. " MAINSTANDBY ,Specifies standby for receiving DISPCON output in command mode after setting all configuration" "Not ready,Standby" hexmask.long.word 0x14 16.--27. 1. " MAINVRESOL ,Specifies vertical resolution (1 ~ 2047)" hexmask.long.word 0x14 0.--11. 1. " MAINHRESOL ,Specifies horizontal resolution (1 ~ 2047)" line.long 0x18 "MVPORCH,Main Display VPORCH Register" bitfld.long 0x18 28.--31. " CMDALLOW ,Specifies the number of horizontal lines where command packet transmission is allowed after stable VFP period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x18 16.--26. 1. " STABLEVFP ,Specifies the number of horizontal lines, where command packet transmission is not allowed after end of active region" hexmask.long.word 0x18 0.--11. 1. " MAINVBP ,Specifies vertical back porch width for video mode (Line count)" line.long 0x1C "MHPORCH,MIPI_DSI_MHPORCH" hexmask.long.word 0x1C 16.--31. 1. " MAINHFP ,Specifies the horizontal front porch width for video mode" hexmask.long.word 0x1C 0.--15. 1. " MAINHBP ,Specifies the horizontal back porch width for video mode" line.long 0x20 "MSYNC,MIPI_DSI_MSYNC" hexmask.long.word 0x20 22.--31. 1. " MAINVSA ,Specifies the vertical sync pulse width for video mode (Line count)" hexmask.long.word 0x20 0.--15. 1. " MAINHSA ,Specifies the horizontal sync pulse width for video mode" line.long 0x24 "SDRESOL,Sub Display Image Resolution Register" bitfld.long 0x24 31. " SUBSTANDBY ,Specifies standby for receiving DISPCON output in command mode after setting all configuration" "Not ready,Standby" hexmask.long.word 0x24 16.--26. 1. " SUBVRESOL ,Specifies the vertical resolution (1 ~ 1024)" hexmask.long.word 0x24 0.--10. 1. " SUBHRESOL ,Specifies the horizontal resolution (1 ~ 1024)" line.long 0x28 "INTSRC,Interrupt Source Register" eventfld.long 0x28 31. " PLLSTABLE ,Indicates that D-PHY PLL is stable" "Not stable,Stable" eventfld.long 0x28 30. " SWRSTRELEASE ,Releases the software reset" "No reset,Reset" eventfld.long 0x28 29. " SFRPLFIFOEMPTY ,Specifies the SFR payload FIFO empty" "Not empty,Empty" eventfld.long 0x28 28. " SFRPHFIFOEMPTY ,Specifies the SFR packet header FIFO emtpy" "Not empty,Empty" textline " " eventfld.long 0x28 27. " SYNCOVERRIDE ,Indicates that other DSI command transfer have overridden sync timing" "Not overriden,Overriden" eventfld.long 0x28 25. " BUSTURNOVER ,Indicates when bus grant turns over from DSI slave to DSI master" "Not turned over,Turned over" eventfld.long 0x28 24. " FRAMEDONE ,Indicates when MIPI DSIM transfers the whole image frame" "Not completed,Completed" eventfld.long 0x28 21. " LPDRTOUT ,Specifies the LP rx timeout" "No timeout,Timeout" textline " " eventfld.long 0x28 20. " TATOUT ,Turns around acknowledge timeout" "No timeout,Timeout" eventfld.long 0x28 18. " RXDATDONE ,Completes receiving data" "In progress,Done" eventfld.long 0x28 17. " RXTE ,Receives TE rx trigger" "Not received,Received" eventfld.long 0x28 16. " RXACK ,Receives ACK rx trigger" "Not received,Received" textline " " eventfld.long 0x28 15. " ERRRXECC ,Specifies the ECC multi bit error in LPDR" "No error,Error" eventfld.long 0x28 14. " ERRRXCRC ,Specifies the CRC error in LPDR" "No error,Error" eventfld.long 0x28 11. " ERRESC1 ,Specifies the escape mode entry error lane 1" "No error,Error" eventfld.long 0x28 10. " ERRESC0 ,Specifies the escape mode entry error lane 0" "No error,Error" textline " " eventfld.long 0x28 7. " ERRSYNC1 ,Specifies the LPDT sync error lane1" "No error,Error" eventfld.long 0x28 6. " ERRSYNC0 ,Specifies the LPDT sync error lane0" "No error,Error" eventfld.long 0x28 3. " ERRCONTROL1 ,Controls error lane1" "No error,Error" eventfld.long 0x28 2. " ERRCONTROL0 ,Controls error lane0" "No error,Error" textline " " eventfld.long 0x28 1. " ERRCONTENTLP0 ,Specifies the LP0 contention error" "No error,Error" eventfld.long 0x28 0. " ERRCONTENTLP1 ,Specifies the LP1 contention error" "No error,Error" line.long 0x2C "INTMSK,Interrupt Mask Register" bitfld.long 0x2C 31. " MSKPLLSTABLE ,Indicates that D-PHY PLL is stable" "Masked,Not masked" bitfld.long 0x2C 30. " MSKSWRSTRELEASE ,Releases the software reset" "Masked,Not masked" bitfld.long 0x2C 29. " MSKSFRPLFIFOEMPTY ,Empties SFR payload FIFO" "Masked,Not masked" bitfld.long 0x2C 28. " MSKSFRPHFIFOEMPTY ,Interrupt mask for SFR packet header FIFO empty" "Masked,Not masked" textline " " bitfld.long 0x2C 27. " MSKSYNCOVERRIDE ,Indicates that other DSI command transfer have overridden sync timingg" "Masked,Not masked" bitfld.long 0x2C 25. " MSKBUSTURNOVER ,Indicates when bus grant turns over from DSI slave to DSI master" "Masked,Not masked" bitfld.long 0x2C 24. " MSKFRAMEDONE ,Indicates when MIPI DSIM transfers whole image frame" "Masked,Not masked" bitfld.long 0x2C 21. " MSKLPDRTOUT ,Specifies the LP rx timeout" "Masked,Not masked" textline " " bitfld.long 0x2C 20. " MSKTATOUT ,Specifies turnaround acknowledge timeout" "Masked,Not masked" bitfld.long 0x2C 18. " MSKRXDATDONE ,Specifies completion of data receiving" "Masked,Not masked" bitfld.long 0x2C 17. " MSKRXTE ,Specifies receipt of TE rx trigger" "Masked,Not masked" bitfld.long 0x2C 16. " MSKRXACK ,Specifies receipt of ACK rx trigger" "Masked,Not masked" textline " " bitfld.long 0x2C 15. " MSKRXECC ,Specifies ECC multibit error in LPDR" "Masked,Not masked" bitfld.long 0x2C 14. " MSKRXCRC ,Specifies CRC error in LPDR" "Masked,Not masked" bitfld.long 0x2C 11. " MSKESC1 ,Specifies escape mode entry error in lane1" "Masked,Not masked" bitfld.long 0x2C 10. " MSKESC0 ,Specifies escape mode entry error in lane0" "Masked,Not masked" textline " " bitfld.long 0x2C 7. " MSKSYNC1 ,Specifies LPDT sync error in lane1" "Masked,Not masked" bitfld.long 0x2C 6. " MSKSYNC0 ,Specifies LPDT sync error in lane0" "Masked,Not masked" bitfld.long 0x2C 3. " MSKCONTROL1 ,Controls error in lane1" "Masked,Not masked" bitfld.long 0x2C 2. " MSKCONTROL0 ,Controls error in lane0" "Masked,Not masked" textline " " bitfld.long 0x2C 1. " MSKCONTENTLP0 ,Specifies LP0 contention error" "Masked,Not masked" bitfld.long 0x2C 0. " MSKCONTENTLP1 ,Specifies LP1 contention error" "Masked,Not masked" textline " " hgroup.long 0x3C++0x0B hide.long 0x00 "PKTHDR,Packet Header FIFO Register" in hide.long 0x04 "PAYLOAD,Payload FIFO Register" in hide.long 0x08 "RXFIFO,Payload FIFO Register" in textline " " group.long 0x48++0x0B line.long 0x00 "FIFOTHLD,FIFO Threshold Level Register" hexmask.long.word 0x00 0.--8. 1. " WFULLLEVELSFR ,Almost full level of SFR payload FIFO" line.long 0x04 "FIFOCTRL,FIFO Status And Control Register" rbitfld.long 0x04 25. " FULLRX ,Rx FIFO full" "Not full,Full" rbitfld.long 0x04 24. " EMPTYRX ,Rx FIFO empty" "Not empty,Empty" rbitfld.long 0x04 23. " FULLHSFR ,SFR packet header FIFO full" "Not full,Full" rbitfld.long 0x04 22. " EMPTYHSFR ,SFR packet header FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x04 21. " FULLLSFR ,SFR payload FIFO full" "Not full,Full" rbitfld.long 0x04 20. " EMPTYLSFR ,SFR payload FIFO empty" "Not empty,Empty" rbitfld.long 0x04 19. " FULLHI80 ,S-i80 packet header FIFO full" "Not full,Full" rbitfld.long 0x04 18. " EMPTYHI80 ,S-i80 packet header FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x04 17. " FULLLI80 ,S-i80 payload FIFO full" "Not full,Full" rbitfld.long 0x04 16. " EMPTYLI80 ,S-i80 payload FIFO empty" "Not empty,Empty" rbitfld.long 0x04 15. " FULLHSUB ,Sub display packet header FIFO full" "Not full,Full" rbitfld.long 0x04 14. " EMPTYHSUB ,Sub display packet header FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x04 13. " FULLLSUB ,Sub display payload FIFO full" "Not full,Full" rbitfld.long 0x04 12. " EMPTYLSUB ,Sub display payload FIFO empty" "Not empty,Empty" rbitfld.long 0x04 11. " FULLHMAIN ,Main display packet header FIFO full" "Not full,Full" rbitfld.long 0x04 10. " EMPTYHMAIN ,Main display packet header FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x04 9. " FULLLMAIN ,Main display payload FIFO full" "Not full,Full" rbitfld.long 0x04 8. " EMPTYLMAIN ,Main display payload FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " NINITRX ,MD FIFO read point initialize" "Not initialized,Initialized" bitfld.long 0x04 3. " NINITSFR ,SFR FIFO write point initialize" "Not initialized,Initialized" textline " " bitfld.long 0x04 2. " NLNITL80 ,S-i80 FIFO write point initialize" "Not initialized,Initialized" bitfld.long 0x04 1. " NINITSUB ,SD FIFO write point initialize" "Not initialized,Initialized" bitfld.long 0x04 0. " NINITMAIN ,MD FIFO write point initialize" "Not initialized,Initialized" line.long 0x08 "MEMACCHR,FIFO Memory AC Characteristic Register" bitfld.long 0x08 15. " PGEN_SD ,Sub display FIFO memory power gating" "Not gated,Gated" bitfld.long 0x08 14. " RETN_SD ,Sub display FIFO memory retention" "No retention,Retention" bitfld.long 0x08 11.--13. " EMAB_SD ,Sub display FIFO memory B port margin adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. " EMAA_SD ,Sub display FIFO memory A port margin adjustment" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 7. " PGEN_MD ,Main display FIFO memory power gating" "Not gated,Gated" bitfld.long 0x08 6. " RETN_MD ,Main display FIFO memory retention" "No retention,Retention" bitfld.long 0x08 3.--5. " EMAB_MD ,Main display FIFO memory B port margin adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " EMAA_MD ,Main display FIFO memory A port margin adjustment" "0,1,2,3,4,5,6,7" textline " " if (((per.l(ad:0x30760000+0x1C)&0x80)==0x80)||((per.l(ad:0x30760000+0x1C)&0x40)==0x40)) group.long 0x78++0x03 line.long 0x00 "MULTI_PKT,MULTI_PKT" bitfld.long 0x00 28. " PKT_GO_RDY ,Specifies the send command Packet(S) on this frame VFP" "Not ready,Ready" hexmask.long.word 0x00 16.--27. 1. " PKT_SEND_CNT_REF ,Specifies the command Packet(S) send point indicator" hexmask.long.word 0x00 0.--15. 1. " MULTI_PKT_CNT_REF ,Specifies the number of packets on single transmission" else group.long 0x78++0x03 line.long 0x00 "MULTI_PKT,MULTI_PKT" bitfld.long 0x00 30. " MULTI_PKT_EN ,Specifies the send multi command packets on single transmission" "Single,Multi" bitfld.long 0x00 29. " PKT_GO_EN ,Specifies the send command Packet(S) per frame enable" "During every VFP,During 1frame VFP" bitfld.long 0x00 28. " PKT_GO_RDY ,Specifies the send command Packet(S) on this frame VFP" "Not ready,Ready" hexmask.long.word 0x00 16.--27. 1. " PKT_SEND_CNT_REF ,Specifies the command Packet(S) send point indicator" hexmask.long.word 0x00 0.--15. 1. " MULTI_PKT_CNT_REF ,Specifies the number of packets on single transmission" endif textline " " group.long 0x90++0x2F line.long 0x00 "PLLCTRL_1G,1 Gbps D-PHY PLL Control Register" bitfld.long 0x00 12.--15. " HSZEROCTL ,1 gbps D-PHY HS-Zero driving timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FREQ_BAND ,1 gbps D-PHY timing control for D-PHY global operation timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--6. " PREPRCTL ,1 gbps D-PHY PLL Tclk-prepare and Ths-prepare driving control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRPRCTLCLK ,1 gbps D-PHY PLL Ths-prepare driving time control" "0,1,2,3,4,5,6,7" line.long 0x04 "PLLCTRL,PLL Control Register" bitfld.long 0x04 25. " DPDNSWAP_CLK ,Swaps dp / dn channel of clock lane" "Not swapped,Swapped" bitfld.long 0x04 24. " DPDNSWAP_DAT ,Swaps dp / dn channel of data lanes" "Not swapped,Swapped" bitfld.long 0x04 23. " PLLEN ,Enables PLL" "Disabled,Enabled" hexmask.long.tbyte 0x04 1.--19. 1. " PMS ,Specifies the PLL PMS value" textline " " line.long 0x08 "PLLCTRL1,PLL Control Register 1" bitfld.long 0x08 31. " M_PLLCTL[31] ,M_PLLCTL31 to D-PHY" "0,1" bitfld.long 0x08 30. " [30] ,M_PLLCTL30 to D-PHY" "0,1" bitfld.long 0x08 29. " [29] ,M_PLLCTL29 to D-PHY" "0,1" bitfld.long 0x08 28. " [28] ,M_PLLCTL28 to D-PHY" "0,1" bitfld.long 0x08 27. " [27] ,M_PLLCTL27 to D-PHY" "0,1" bitfld.long 0x08 26. " [26] ,M_PLLCTL26 to D-PHY" "0,1" bitfld.long 0x08 25. " [25] ,M_PLLCTL25 to D-PHY" "0,1" bitfld.long 0x08 24. " [24] ,M_PLLCTL24 to D-PHY" "0,1" textline " " bitfld.long 0x08 23. " [23] ,M_PLLCTL23 to D-PHY" "0,1" bitfld.long 0x08 22. " [22] ,M_PLLCTL22 to D-PHY" "0,1" bitfld.long 0x08 21. " [21] ,M_PLLCTL21 to D-PHY" "0,1" bitfld.long 0x08 20. " [20] ,M_PLLCTL20 to D-PHY" "0,1" bitfld.long 0x08 19. " [19] ,M_PLLCTL19 to D-PHY" "0,1" bitfld.long 0x08 18. " [18] ,M_PLLCTL18 to D-PHY" "0,1" bitfld.long 0x08 17. " [17] ,M_PLLCTL17 to D-PHY" "0,1" bitfld.long 0x08 16. " [16] ,M_PLLCTL16 to D-PHY" "0,1" textline " " bitfld.long 0x08 15. " [15] ,M_PLLCTL15 to D-PHY" "0,1" bitfld.long 0x08 14. " [14] ,M_PLLCTL14 to D-PHY" "0,1" bitfld.long 0x08 13. " [13] ,M_PLLCTL13 to D-PHY" "0,1" bitfld.long 0x08 12. " [12] ,M_PLLCTL12 to D-PHY" "0,1" bitfld.long 0x08 11. " [11] ,M_PLLCTL11 to D-PHY" "0,1" bitfld.long 0x08 10. " [10] ,M_PLLCTL10 to D-PHY" "0,1" bitfld.long 0x08 9. " [9] ,M_PLLCTL9 to D-PHY" "0,1" bitfld.long 0x08 8. " [8] ,M_PLLCTL8 to D-PHY" "0,1" textline " " bitfld.long 0x08 7. " [7] ,M_PLLCTL7 to D-PHY" "0,1" bitfld.long 0x08 6. " [6] ,M_PLLCTL6 to D-PHY" "0,1" bitfld.long 0x08 5. " [5] ,M_PLLCTL5 to D-PHY" "0,1" bitfld.long 0x08 4. " [4] ,M_PLLCTL4 to D-PHY" "0,1" bitfld.long 0x08 3. " [3] ,M_PLLCTL3 to D-PHY" "0,1" bitfld.long 0x08 2. " [2] ,M_PLLCTL2 to D-PHY" "0,1" bitfld.long 0x08 1. " [1] ,M_PLLCTL1 to D-PHY" "0,1" bitfld.long 0x08 0. " [0] ,M_PLLCTL0 to D-PHY" "0,1" line.long 0x0C "PLLCTRL2,PLL Control Register 2" bitfld.long 0x0C 7. " M_PLLCTL[7] ,M_PLLCTL39 to D-PHY" "0,1" bitfld.long 0x0C 6. " [6] ,M_PLLCTL38 to D-PHY" "0,1" bitfld.long 0x0C 5. " [5] ,M_PLLCTL37 to D-PHY" "0,1" bitfld.long 0x0C 4. " [4] ,M_PLLCTL36 to D-PHY" "0,1" bitfld.long 0x0C 3. " [3] ,M_PLLCTL35 to D-PHY" "0,1" bitfld.long 0x0C 2. " [2] ,M_PLLCTL34 to D-PHY" "0,1" bitfld.long 0x0C 1. " [1] ,M_PLLCTL33 to D-PHY" "0,1" bitfld.long 0x0C 0. " [0] ,M_PLLCTL32 to D-PHY" "0,1" line.long 0x10 "PLLTMR,PLL Timer Register" line.long 0x14 "PHYCTRL_B1,D-PHY Master And Slave Analog Block Control Register 1" bitfld.long 0x14 31. " B_DPHYCTL[31] ,B_DPHYCTL31 to D-PHY" "0,1" bitfld.long 0x14 30. " [30] ,B_DPHYCTL30 to D-PHY" "0,1" bitfld.long 0x14 29. " [29] ,B_DPHYCTL29 to D-PHY" "0,1" bitfld.long 0x14 28. " [28] ,B_DPHYCTL28 to D-PHY" "0,1" bitfld.long 0x14 27. " [27] ,B_DPHYCTL27 to D-PHY" "0,1" bitfld.long 0x14 26. " [26] ,B_DPHYCTL26 to D-PHY" "0,1" bitfld.long 0x14 25. " [25] ,B_DPHYCTL25 to D-PHY" "0,1" bitfld.long 0x14 24. " [24] ,B_DPHYCTL24 to D-PHY" "0,1" textline " " bitfld.long 0x14 23. " [23] ,B_DPHYCTL23 to D-PHY" "0,1" bitfld.long 0x14 22. " [22] ,B_DPHYCTL22 to D-PHY" "0,1" bitfld.long 0x14 21. " [21] ,B_DPHYCTL21 to D-PHY" "0,1" bitfld.long 0x14 20. " [20] ,B_DPHYCTL20 to D-PHY" "0,1" bitfld.long 0x14 19. " [19] ,B_DPHYCTL19 to D-PHY" "0,1" bitfld.long 0x14 18. " [18] ,B_DPHYCTL18 to D-PHY" "0,1" bitfld.long 0x14 17. " [17] ,B_DPHYCTL17 to D-PHY" "0,1" bitfld.long 0x14 16. " [16] ,B_DPHYCTL16 to D-PHY" "0,1" textline " " bitfld.long 0x14 15. " [15] ,B_DPHYCTL15 to D-PHY" "0,1" bitfld.long 0x14 14. " [14] ,B_DPHYCTL14 to D-PHY" "0,1" bitfld.long 0x14 13. " [13] ,B_DPHYCTL13 to D-PHY" "0,1" bitfld.long 0x14 12. " [12] ,B_DPHYCTL12 to D-PHY" "0,1" bitfld.long 0x14 11. " [11] ,B_DPHYCTL11 to D-PHY" "0,1" bitfld.long 0x14 10. " [10] ,B_DPHYCTL10 to D-PHY" "0,1" bitfld.long 0x14 9. " [9] ,B_DPHYCTL9 to D-PHY" "0,1" bitfld.long 0x14 8. " [8] ,B_DPHYCTL8 to D-PHY" "0,1" textline " " bitfld.long 0x14 7. " [7] ,B_DPHYCTL7 to D-PHY" "0,1" bitfld.long 0x14 6. " [6] ,B_DPHYCTL6 to D-PHY" "0,1" bitfld.long 0x14 5. " [5] ,B_DPHYCTL5 to D-PHY" "0,1" bitfld.long 0x14 4. " [4] ,B_DPHYCTL4 to D-PHY" "0,1" bitfld.long 0x14 3. " [3] ,B_DPHYCTL3 to D-PHY" "0,1" bitfld.long 0x14 2. " [2] ,B_DPHYCTL2 to D-PHY" "0,1" bitfld.long 0x14 1. " [1] ,B_DPHYCTL1 to D-PHY" "0,1" bitfld.long 0x14 0. " [0] ,B_DPHYCTL0 to D-PHY" "0,1" line.long 0x18 "PHYCTRL_B2,D-PHY Master And Slave Analog Block Control Register 2" bitfld.long 0x18 31. " B_DPHYCTL[63] ,B_DPHYCTL63 to D-PHY" "0,1" bitfld.long 0x18 30. " [62] ,B_DPHYCTL62 to D-PHY" "0,1" bitfld.long 0x18 29. " [61] ,B_DPHYCTL61 to D-PHY" "0,1" bitfld.long 0x18 28. " [60] ,B_DPHYCTL60 to D-PHY" "0,1" bitfld.long 0x18 27. " [59] ,B_DPHYCTL59 to D-PHY" "0,1" bitfld.long 0x18 26. " [58] ,B_DPHYCTL58 to D-PHY" "0,1" bitfld.long 0x18 25. " [57] ,B_DPHYCTL57 to D-PHY" "0,1" bitfld.long 0x18 24. " [56] ,B_DPHYCTL56 to D-PHY" "0,1" textline " " bitfld.long 0x18 23. " [55] ,B_DPHYCTL55 to D-PHY" "0,1" bitfld.long 0x18 22. " [54] ,B_DPHYCTL54 to D-PHY" "0,1" bitfld.long 0x18 21. " [53] ,B_DPHYCTL53 to D-PHY" "0,1" bitfld.long 0x18 20. " [52] ,B_DPHYCTL52 to D-PHY" "0,1" bitfld.long 0x18 19. " [51] ,B_DPHYCTL51 to D-PHY" "0,1" bitfld.long 0x18 18. " [50] ,B_DPHYCTL50 to D-PHY" "0,1" bitfld.long 0x18 17. " [49] ,B_DPHYCTL49 to D-PHY" "0,1" bitfld.long 0x18 16. " [48] ,B_DPHYCTL48 to D-PHY" "0,1" textline " " bitfld.long 0x18 15. " [47] ,B_DPHYCTL47 to D-PHY" "0,1" bitfld.long 0x18 14. " [46] ,B_DPHYCTL46 to D-PHY" "0,1" bitfld.long 0x18 13. " [45] ,B_DPHYCTL45 to D-PHY" "0,1" bitfld.long 0x18 12. " [44] ,B_DPHYCTL44 to D-PHY" "0,1" bitfld.long 0x18 11. " [43] ,B_DPHYCTL43 to D-PHY" "0,1" bitfld.long 0x18 10. " [42] ,B_DPHYCTL42 to D-PHY" "0,1" bitfld.long 0x18 9. " [41] ,B_DPHYCTL41 to D-PHY" "0,1" bitfld.long 0x18 8. " [40] ,B_DPHYCTL40 to D-PHY" "0,1" textline " " bitfld.long 0x18 7. " [39] ,B_DPHYCTL39 to D-PHY" "0,1" bitfld.long 0x18 6. " [38] ,B_DPHYCTL38 to D-PHY" "0,1" bitfld.long 0x18 5. " [37] ,B_DPHYCTL37 to D-PHY" "0,1" bitfld.long 0x18 4. " [36] ,B_DPHYCTL36 to D-PHY" "0,1" bitfld.long 0x18 3. " [35] ,B_DPHYCTL35 to D-PHY" "0,1" bitfld.long 0x18 2. " [34] ,B_DPHYCT34 to D-PHY" "0,1" bitfld.long 0x18 1. " [33] ,B_DPHYCTL33 to D-PHY" "0,1" bitfld.long 0x18 0. " [32] ,B_DPHYCTL32 to D-PHY" "0,1" line.long 0x1C "PHYCTRL_M1,D-PHY Master Analog Block Control Register 1" bitfld.long 0x1C 31. " M_DPHYCTL[31] ,M_DPHYCTL31 to D-PHY" "0,1" bitfld.long 0x1C 30. " [30] ,M_DPHYCTL30 to D-PHY" "0,1" bitfld.long 0x1C 29. " [29] ,M_DPHYCTL29 to D-PHY" "0,1" bitfld.long 0x1C 28. " [28] ,M_DPHYCTL28 to D-PHY" "0,1" bitfld.long 0x1C 27. " [27] ,M_DPHYCTL27 to D-PHY" "0,1" bitfld.long 0x1C 26. " [26] ,M_DPHYCTL26 to D-PHY" "0,1" bitfld.long 0x1C 25. " [25] ,M_DPHYCTL25 to D-PHY" "0,1" bitfld.long 0x1C 24. " [24] ,M_DPHYCTL24 to D-PHY" "0,1" textline " " bitfld.long 0x1C 23. " [23] ,M_DPHYCTL23 to D-PHY" "0,1" bitfld.long 0x1C 22. " [22] ,M_DPHYCTL22 to D-PHY" "0,1" bitfld.long 0x1C 21. " [21] ,M_DPHYCTL21 to D-PHY" "0,1" bitfld.long 0x1C 20. " [20] ,M_DPHYCTL20 to D-PHY" "0,1" bitfld.long 0x1C 19. " [19] ,M_DPHYCTL19 to D-PHY" "0,1" bitfld.long 0x1C 18. " [18] ,M_DPHYCTL18 to D-PHY" "0,1" bitfld.long 0x1C 17. " [17] ,M_DPHYCTL17 to D-PHY" "0,1" bitfld.long 0x1C 16. " [16] ,M_DPHYCTL16 to D-PHY" "0,1" textline " " bitfld.long 0x1C 15. " [15] ,M_DPHYCTL15 to D-PHY" "0,1" bitfld.long 0x1C 14. " [14] ,M_DPHYCTL14 to D-PHY" "0,1" bitfld.long 0x1C 13. " [13] ,M_DPHYCTL13 to D-PHY" "0,1" bitfld.long 0x1C 12. " [12] ,M_DPHYCTL12 to D-PHY" "0,1" bitfld.long 0x1C 11. " [11] ,M_DPHYCTL11 to D-PHY" "0,1" bitfld.long 0x1C 10. " [10] ,M_DPHYCTL10 to D-PHY" "0,1" bitfld.long 0x1C 9. " [9] ,M_DPHYCTL9 to D-PHY" "0,1" bitfld.long 0x1C 8. " [8] ,M_DPHYCTL8 to D-PHY" "0,1" textline " " bitfld.long 0x1C 7. " [7] ,M_DPHYCTL7 to D-PHY" "0,1" bitfld.long 0x1C 6. " [6] ,M_DPHYCTL6 to D-PHY" "0,1" bitfld.long 0x1C 5. " [5] ,M_DPHYCTL5 to D-PHY" "0,1" bitfld.long 0x1C 4. " [4] ,M_DPHYCTL4 to D-PHY" "0,1" bitfld.long 0x1C 3. " [3] ,M_DPHYCTL3 to D-PHY" "0,1" bitfld.long 0x1C 2. " [2] ,M_DPHYCTL2 to D-PHY" "0,1" bitfld.long 0x1C 1. " [1] ,M_DPHYCTL1 to D-PHY" "0,1" bitfld.long 0x1C 0. " [0] ,M_DPHYCTL0 to D-PHY" "0,1" line.long 0x20 "PHYCTRL_M2,D-PHY Master Analog Block Control Register 1" bitfld.long 0x20 31. " B_DPHYCTL[63] ,M_DPHYCTL63 to D-PHY" "0,1" bitfld.long 0x20 30. " [62] ,M_DPHYCTL62 to D-PHY" "0,1" bitfld.long 0x20 29. " [61] ,M_DPHYCTL61 to D-PHY" "0,1" bitfld.long 0x20 28. " [60] ,M_DPHYCTL60 to D-PHY" "0,1" bitfld.long 0x20 27. " [59] ,M_DPHYCTL59 to D-PHY" "0,1" bitfld.long 0x20 26. " [58] ,M_DPHYCTL58 to D-PHY" "0,1" bitfld.long 0x20 25. " [57] ,M_DPHYCTL57 to D-PHY" "0,1" bitfld.long 0x20 24. " [56] ,M_DPHYCTL56 to D-PHY" "0,1" textline " " bitfld.long 0x20 23. " [55] ,M_DPHYCTL55 to D-PHY" "0,1" bitfld.long 0x20 22. " [54] ,M_DPHYCTL54 to D-PHY" "0,1" bitfld.long 0x20 21. " [53] ,M_DPHYCTL53 to D-PHY" "0,1" bitfld.long 0x20 20. " [52] ,M_DPHYCTL52 to D-PHY" "0,1" bitfld.long 0x20 19. " [51] ,M_DPHYCTL51 to D-PHY" "0,1" bitfld.long 0x20 18. " [50] ,M_DPHYCTL50 to D-PHY" "0,1" bitfld.long 0x20 17. " [49] ,M_DPHYCTL49 to D-PHY" "0,1" bitfld.long 0x20 16. " [48] ,M_DPHYCTL48 to D-PHY" "0,1" textline " " bitfld.long 0x20 15. " [47] ,M_DPHYCTL47 to D-PHY" "0,1" bitfld.long 0x20 14. " [46] ,M_DPHYCTL46 to D-PHY" "0,1" bitfld.long 0x20 13. " [45] ,M_DPHYCTL45 to D-PHY" "0,1" bitfld.long 0x20 12. " [44] ,M_DPHYCTL44 to D-PHY" "0,1" bitfld.long 0x20 11. " [43] ,M_DPHYCTL43 to D-PHY" "0,1" bitfld.long 0x20 10. " [42] ,M_DPHYCTL42 to D-PHY" "0,1" bitfld.long 0x20 9. " [41] ,M_DPHYCTL41 to D-PHY" "0,1" bitfld.long 0x20 8. " [40] ,M_DPHYCTL40 to D-PHY" "0,1" textline " " bitfld.long 0x20 7. " [39] ,M_DPHYCTL39 to D-PHY" "0,1" bitfld.long 0x20 6. " [38] ,M_DPHYCTL38 to D-PHY" "0,1" bitfld.long 0x20 5. " [37] ,M_DPHYCTL37 to D-PHY" "0,1" bitfld.long 0x20 4. " [36] ,M_DPHYCTL36 to D-PHY" "0,1" bitfld.long 0x20 3. " [35] ,M_DPHYCTL35 to D-PHY" "0,1" bitfld.long 0x20 2. " [34] ,B_DPHYCT34 to D-PHY" "0,1" bitfld.long 0x20 1. " [33] ,M_DPHYCTL33 to D-PHY" "0,1" bitfld.long 0x20 0. " [32] ,M_DPHYCTL32 to D-PHY" "0,1" line.long 0x24 "PHYTIMING,D-PHY Timing Register" bitfld.long 0x24 15. " M_TLPXCTL[7] ,M_TLPXCTL7 to D-PHY" "0,1" bitfld.long 0x24 14. " [6] ,M_TLPXCTL6 to D-PHY" "0,1" bitfld.long 0x24 13. " [5] ,M_TLPXCTL5 to D-PHY" "0,1" bitfld.long 0x24 12. " [4] ,M_TLPXCTL4 to D-PHY" "0,1" bitfld.long 0x24 11. " [3] ,M_TLPXCTL3 to D-PHY" "0,1" bitfld.long 0x24 10. " [2] ,M_TLPXCTL2 to D-PHY" "0,1" bitfld.long 0x24 9. " [1] ,M_TLPXCTL1 to D-PHY" "0,1" bitfld.long 0x24 8. " [0] ,M_TLPXCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x24 7. " M_THSEXITCTL[7] ,M_THSEXITCTL7 to D-PHY" "0,1" bitfld.long 0x24 6. " [6] ,M_THSEXITCTL6 to D-PHY" "0,1" bitfld.long 0x24 5. " [5] ,M_THSEXITCTL5 to D-PHY" "0,1" bitfld.long 0x24 4. " [4] ,M_THSEXITCTL4 to D-PHY" "0,1" bitfld.long 0x24 3. " [3] ,M_THSEXITCTL3 to D-PHY" "0,1" bitfld.long 0x24 2. " [2] ,M_THSEXITCTL2 to D-PHY" "0,1" bitfld.long 0x24 1. " [1] ,M_THSEXITCTL1 to D-PHY" "0,1" bitfld.long 0x24 0. " [0] ,M_THSEXITCTL0 to D-PHY" "0,1" line.long 0x28 "PHYTIMING1,PHYTIMING1" bitfld.long 0x28 31. " M_TCLKPRPRCTL[7] ,M_TCLKPRPRCTL7 to D-PHY" "0,1" bitfld.long 0x28 30. " [6] ,M_TCLKPRPRCTL6 to D-PHY" "0,1" bitfld.long 0x28 29. " [5] ,M_TCLKPRPRCTL5 to D-PHY" "0,1" bitfld.long 0x28 28. " [4] ,M_TCLKPRPRCTL4 to D-PHY" "0,1" bitfld.long 0x28 27. " [3] ,M_TCLKPRPRCTL3 to D-PHY" "0,1" bitfld.long 0x28 26. " [2] ,M_TCLKPRPRCTL2 to D-PHY" "0,1" bitfld.long 0x28 25. " [1] ,M_TCLKPRPRCTL1 to D-PHY" "0,1" bitfld.long 0x28 24. " [0] ,M_TCLKPRPRCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x28 23. " M_TCLKZEROCTL[7] ,M_TCLKZEROCTL7 to D-PHY" "0,1" bitfld.long 0x28 22. " [6] ,M_TCLKZEROCTL6 to D-PHY" "0,1" bitfld.long 0x28 21. " [5] ,M_TCLKZEROCTL5 to D-PHY" "0,1" bitfld.long 0x28 20. " [4] ,M_TCLKZEROCTL4 to D-PHY" "0,1" bitfld.long 0x28 19. " [3] ,M_TCLKZEROCTL3 to D-PHY" "0,1" bitfld.long 0x28 18. " [2] ,M_TCLKZEROCTL2 to D-PHY" "0,1" bitfld.long 0x28 17. " [1] ,M_TCLKZEROCTL1 to D-PHY" "0,1" bitfld.long 0x28 16. " [0] ,M_TCLKZEROCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x28 15. " M_TCLKPOSTCTL[7] ,M_TCLKPOSTCTL7 to D-PHY" "0,1" bitfld.long 0x28 14. " [6] ,M_TCLKPOSTCTL6 to D-PHY" "0,1" bitfld.long 0x28 13. " [5] ,M_TCLKPOSTCTL5 to D-PHY" "0,1" bitfld.long 0x28 12. " [4] ,M_TCLKPOSTCTL4 to D-PHY" "0,1" bitfld.long 0x28 11. " [3] ,M_TCLKPOSTCTL3 to D-PHY" "0,1" bitfld.long 0x28 10. " [2] ,M_TCLKPOSTCTL2 to D-PHY" "0,1" bitfld.long 0x28 9. " [1] ,M_TCLKPOSTCTL1 to D-PHY" "0,1" bitfld.long 0x28 8. " [0] ,M_TCLKPOSTCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x28 7. " M_TCLKTRAILCTL[7] ,M_TCLKTRAILCTL7 to D-PHY" "0,1" bitfld.long 0x28 6. " [6] ,M_TCLKTRAILCTL6 to D-PHY" "0,1" bitfld.long 0x28 5. " [5] ,M_TCLKTRAILCTL5 to D-PHY" "0,1" bitfld.long 0x28 4. " [4] ,M_TCLKTRAILCTL4 to D-PHY" "0,1" bitfld.long 0x28 3. " [3] ,M_TCLKTRAILCTL3 to D-PHY" "0,1" bitfld.long 0x28 2. " [2] ,M_TCLKTRAILCTL2 to D-PHY" "0,1" bitfld.long 0x28 1. " [1] ,M_TCLKTRAILCTL1 to D-PHY" "0,1" bitfld.long 0x28 0. " [0] ,M_TCLKTRAILCTL0 to D-PHY" "0,1" line.long 0x2C "PHYTIMING2,D-PHY Timing Register 2" bitfld.long 0x2C 23. " M_THSPRPRCTL[7] ,M_THSPRPRCTL7 to D-PHY" "0,1" bitfld.long 0x2C 22. " [6] ,M_THSPRPRCTL6 to D-PHY" "0,1" bitfld.long 0x2C 21. " [5] ,M_THSPRPRCTL5 to D-PHY" "0,1" bitfld.long 0x2C 20. " [4] ,M_THSPRPRCTL4 to D-PHY" "0,1" bitfld.long 0x2C 19. " [3] ,M_THSPRPRCTL3 to D-PHY" "0,1" bitfld.long 0x2C 18. " [2] ,M_THSPRPRCTL2 to D-PHY" "0,1" bitfld.long 0x2C 17. " [1] ,M_THSPRPRCTL1 to D-PHY" "0,1" bitfld.long 0x2C 16. " [0] ,M_THSPRPRCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x2C 15. " M_THSZEROCTL[7] ,M_THSZEROCTL7 to D-PHY" "0,1" bitfld.long 0x2C 14. " [6] ,M_THSZEROCTL6 to D-PHY" "0,1" bitfld.long 0x2C 13. " [5] ,M_THSZEROCTL5 to D-PHY" "0,1" bitfld.long 0x2C 12. " [4] ,M_THSZEROCTL4 to D-PHY" "0,1" bitfld.long 0x2C 11. " [3] ,M_THSZEROCTL3 to D-PHY" "0,1" bitfld.long 0x2C 10. " [2] ,M_THSZEROCTL2 to D-PHY" "0,1" bitfld.long 0x2C 9. " [1] ,M_THSZEROCTL1 to D-PHY" "0,1" bitfld.long 0x2C 8. " [0] ,M_THSZEROCTL0 to D-PHY" "0,1" textline " " bitfld.long 0x2C 7. " M_THSTRAILCTL[7] ,M_THSTRAILCTL7 to D-PHY" "0,1" bitfld.long 0x2C 6. " [6] ,M_THSTRAILCTL6 to D-PHY" "0,1" bitfld.long 0x2C 5. " [5] ,M_THSTRAILCTL5 to D-PHY" "0,1" bitfld.long 0x2C 4. " [4] ,M_THSTRAILCTL4 to D-PHY" "0,1" bitfld.long 0x2C 3. " [3] ,M_THSTRAILCTL3 to D-PHY" "0,1" bitfld.long 0x2C 2. " [2] ,M_THSTRAILCTL2 to D-PHY" "0,1" bitfld.long 0x2C 1. " [1] ,M_THSTRAILCTL1 to D-PHY" "0,1" bitfld.long 0x2C 0. " [0] ,M_THSTRAILCTL0 to D-PHY" "0,1" width 0x0B tree.end tree "MIPI_CSI2 (MIPI CSI2 Host Controller)" base ad:0x30750000 width 16. group.long 0x04++0x07 line.long 0x00 "CSIS_CMN_CTRL,CSIS Common Control" bitfld.long 0x00 16. " UPDATE_SHADOW ,Strobe of updating shadow register CH0" "Not updated,Updated" bitfld.long 0x00 10.--11. " INTERLEAVE_MODE ,Selects interleave mode" "CH0 only,DT only,VC only,VC and DT" bitfld.long 0x00 8.--9. " LANE_NUMBER ,Number of data lane" "1,2,?..." bitfld.long 0x00 2. " UPDATE_SHADOW_CTRL ,Updates shadow control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_REST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " CSI_EN ,MIPI CSI2 system enable" "Disabled,Enabled" line.long 0x04 "CSIS_CLK_CTRL,CSIS Clock Gate Control" bitfld.long 0x04 16.--19. " CLKGATE_TRAIL ,Trailing clocks are used for poping the F/F of ISP or CAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. " CLKGATE_EN ,Pixel clock's alive" "Always,During the interval of frame" bitfld.long 0x04 0. " WCLK_SRC ,Pixel clock source" "PCLK,EXTCLK" group.long 0x10++0x07 line.long 0x00 "CSIS_INT_MSK,CSIS Interrupt Mask" bitfld.long 0x00 31. " MSK_EVENBEFORE ,Non image data are received at even frame and before image" "Masked,Unmasked" bitfld.long 0x00 30. " MSK_EVENAFTER ,Non image data are received at even frame and after image" "Masked,Unmasked" bitfld.long 0x00 29. " MSK_ODDBEFORE ,Non image data are received at odd frame and before image" "Masked,Unmasked" bitfld.long 0x00 28. " MSK_ODDAFTER ,Non image data are received at odd frame and after image" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " MSK_FRAMESTART[3] ,FS packet is received for CH3" "Masked,Unmasked" bitfld.long 0x00 26. " MSK_FRAMESTART[2] ,FS packet is received for CH2" "Masked,Unmasked" bitfld.long 0x00 25. " MSK_FRAMESTART[1] ,FS packet is received for CH1" "Masked,Unmasked" bitfld.long 0x00 24. " MSK_FRAMESTART[0] ,FS packet is received for CH0" "Masked,Unmasked" textline " " bitfld.long 0x00 23. " MSK_FRAMEEND[3] ,FS packet is received for CH3" "Masked,Unmasked" bitfld.long 0x00 22. " MSK_FRAMEEND[2] ,FS packet is received for CH2" "Masked,Unmasked" bitfld.long 0x00 21. " MSK_FRAMEEND[1] ,FS packet is received for CH1" "Masked,Unmasked" bitfld.long 0x00 20. " MSK_FRAMEEND[0] ,FS packet is received for CH0" "Masked,Unmasked" textline " " bitfld.long 0x00 17. " MSK_ERR_SOT_HS[1] ,Start of transmission error for lane1" "Masked,Unmasked" bitfld.long 0x00 16. " MSK_ERR_SOT_HS[0] ,Start of transmission error for lane0" "Masked,Unmasked" textline " " bitfld.long 0x00 15. " MSK_ERR_LOST_FS[3] ,Lost of frame start packet for CH3" "Masked,Unmasked" bitfld.long 0x00 14. " MSK_ERR_LOST_FS[2] ,Lost of frame start packet for CH2" "Masked,Unmasked" bitfld.long 0x00 13. " MSK_ERR_LOST_FS[1] ,Lost of frame start packet for CH1" "Masked,Unmasked" bitfld.long 0x00 12. " MSK_ERR_LOST_FS[0] ,Lost of frame start packet for CH0" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " MSK_ERR_LOST_FE[3] ,Lost of frame end packet for CH3" "Masked,Unmasked" bitfld.long 0x00 10. " MSK_ERR_LOST_FE[2] ,Lost of frame end packet for CH2" "Masked,Unmasked" bitfld.long 0x00 9. " MSK_ERR_LOST_FE[1] ,Lost of frame end packet for CH1" "Masked,Unmasked" bitfld.long 0x00 8. " MSK_ERR_LOST_FE[0] ,Lost of frame end packet for CH0" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " MSK_ERR_OVER[3] ,Image FIFO overflow interrupt for CH3" "Masked,Unmasked" bitfld.long 0x00 6. " MSK_ERR_OVER[2] ,Image FIFO overflow interrupt for CH2" "Masked,Unmasked" bitfld.long 0x00 5. " MSK_ERR_OVER[1] ,Image FIFO overflow interrupt for CH1" "Masked,Unmasked" bitfld.long 0x00 4. " MSK_ERR_OVER[0] ,Image FIFO overflow interrupt for CH0" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " MSK_ERR_WRONG_CFG ,Wrong configuration" "Masked,Unmasked" bitfld.long 0x00 2. " MSK_ERR_ECC ,ECC error" "Masked,Unmasked" bitfld.long 0x00 1. " MSK_ERR_CRC ,CRC error" "Masked,Unmasked" bitfld.long 0x00 0. " MSK_ERR_ID ,Unknown ID error" "Masked,Unmasked" line.long 0x04 "CSIS_INT_SRC,CSIS Interrupt Source" bitfld.long 0x04 31. " EVENBEFORE ,Non image data are received at even frame and before image" "No innterrupt,Interrupt" bitfld.long 0x04 30. " EVENAFTER ,Non image data are received at even frame and after image" "No innterrupt,Interrupt" bitfld.long 0x04 29. " ODDBEFORE ,Non image data are received at odd frame and before image" "No innterrupt,Interrupt" bitfld.long 0x04 28. " ODDAFTER ,Non image data are received at odd frame and after image" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 27. " FRAMESTART[3] ,FS packet is received for CH3" "No innterrupt,Interrupt" bitfld.long 0x04 26. " FRAMESTART[2] ,FS packet is received for CH2" "No innterrupt,Interrupt" bitfld.long 0x04 25. " FRAMESTART[1] ,FS packet is received for CH1" "No innterrupt,Interrupt" bitfld.long 0x04 24. " FRAMESTART[0] ,FS packet is received for CH0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 23. " FRAMEEND[3] ,FE packet is received for CH3" "No innterrupt,Interrupt" bitfld.long 0x04 22. " FRAMEEND[2] ,FS packet is received for CH2" "No innterrupt,Interrupt" bitfld.long 0x04 21. " FRAMEEND[1] ,FS packet is received for CH1" "No innterrupt,Interrupt" bitfld.long 0x04 20. " FRAMEEND[0] ,FS packet is received for CH0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 17. " ERR_SOT_HS[1] ,Start of transmission error for lane1" "No innterrupt,Interrupt" bitfld.long 0x04 16. " ERR_SOT_HS[0] ,Start of transmission error for lane0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 15. " ERR_LOST_FS[3] ,Lost of frame start packet for CH3" "No innterrupt,Interrupt" bitfld.long 0x04 14. " ERR_LOST_FS[2] ,Lost of frame start packet for CH2" "No innterrupt,Interrupt" bitfld.long 0x04 13. " ERR_LOST_FS[1] ,Lost of frame start packet for CH1" "No innterrupt,Interrupt" bitfld.long 0x04 12. " ERR_LOST_FS[0] ,Lost of frame start packet for CH0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 11. " ERR_LOST_FE[3] ,Lost of frame end packet for CH3" "No innterrupt,Interrupt" bitfld.long 0x04 10. " ERR_LOST_FE[2] ,Lost of frame end packet for CH2" "No innterrupt,Interrupt" bitfld.long 0x04 9. " ERR_LOST_FE[1] ,Lost of frame end packet for CH1" "No innterrupt,Interrupt" bitfld.long 0x04 8. " ERR_LOST_FE[0] ,Lost of frame end packet for CH0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 7. " ERR_OVER[3] ,Image FIFO overflow interrupt for CH3" "No innterrupt,Interrupt" bitfld.long 0x04 6. " ERR_OVER[2] ,Image FIFO overflow interrupt for CH2" "No innterrupt,Interrupt" bitfld.long 0x04 5. " ERR_OVER[1] ,Image FIFO overflow interrupt for CH1" "No innterrupt,Interrupt" bitfld.long 0x04 4. " ERR_OVER[0] ,Image FIFO overflow interrupt for CH0" "No innterrupt,Interrupt" textline " " bitfld.long 0x04 3. " ERR_WRONG_CFG ,Wrong configuration" "No innterrupt,Interrupt" bitfld.long 0x04 2. " ERR_ECC ,ECC error" "No innterrupt,Interrupt" bitfld.long 0x04 1. " ERR_CRC ,CRC error" "No innterrupt,Interrupt" bitfld.long 0x04 0. " ERR_ID ,Unknown ID error" "No innterrupt,Interrupt" rgroup.long 0x20++0x03 line.long 0x00 "DPHY_STATUS,D-PHY Status" bitfld.long 0x00 9. " ULPSDAT[1] ,Data lane 1 is in ULPS" "Not ULPS,ULPS" bitfld.long 0x00 8. " ULPSDAT[0] ,Data lane 0 is in ULPS" "Not ULPS,ULPS" bitfld.long 0x00 5. " STOPSTATEDAT[1] ,Data lane 1 is in stop state" "Normal state,Stop state" bitfld.long 0x00 4. " STOPSTATEDAT[0] ,Data lane 0 is in stop state" "Normal state,Stop state" textline " " bitfld.long 0x00 1. " ULPSCLK ,Clock lane is in ULPS" "Not ULPS,ULPS" bitfld.long 0x00 0. " STOPSTATECLK ,Clock lane is in stop state" "Normal state,Stop state" group.long 0x24++0x03 line.long 0x00 "DPHY_CMN_CTRL,D-PHY Common Control" hexmask.long.byte 0x00 24.--31. 1. " HSSETTLE ,HS-RX settle time control register" bitfld.long 0x00 22.--23. " S_CLKSETTLECTL ,D-PHY control register is for standard spec v0.9 of MIPI CSI2" "0,1,2,3" bitfld.long 0x00 6. " S_DPDN_SWAP_CLK ,Swapping dp and dn channel of clock lane" "Not swapped,Swapped" bitfld.long 0x00 5. " S_DPDN_SWAP_DAT ,Swapping dp and dn channel of data lanes" "Not swapped,Swapped" textline " " bitfld.long 0x00 2. " ENABLE_DAT[1] ,D-PHY data lane 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_DAT[0] ,D-PHY data lane 0 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_CLK ,D-PHY clock lane enable" "Disabled,Enabled" group.long 0x30++0x0F line.long 0x00 "DPHY_BCTRL_L,D-PHY Master And Slave Control Register Low" line.long 0x04 "DPHY_BCTRL_H,D-PHY Master And Slave Control Register High" line.long 0x08 "DPHY_SCTRL_L,D-PHY Slave Control Register Low" line.long 0x0C "DPHY_SCTRL_H,D-PHY Slave Control Register High" if (((per.l(ad:0x30750000+0x40))&0xFC)==0xA8) group.long 0x40++0x03 line.long 0x00 "ISP_CONFIG_CH0,ISP Configuration Register Of CH0" hexmask.long.byte 0x00 24.--31. 1. " MEM_FULL_GAP ,MEM_FULL_GAP" bitfld.long 0x00 12. " DOUBLE_CMPNT ,Double component per clock cycle in YUV422 formats" "Single,Double" bitfld.long 0x00 11. " PARALLEL ,The outer bus width of CSIS V3.3" "Normal,32-bit data alignment" bitfld.long 0x00 10. " RGB_SWAP ,Swapping RGB sequence" "Not swapped,Swapped" textline " " bitfld.long 0x00 9. " DECOMP_PREDICT ,Decompress prediction mode of CH0" "Simple,?..." bitfld.long 0x00 8. " DECOMP_EN ,Decompress enable" "Disabled,Enabled" bitfld.long 0x00 2.--7. " DATAFORMAT ,Image data format" ",,,,,,,,,,,,,,,,,,,,,,,,YUV420 (8-bit),YUV420 (10-bit),YUV420 (8-bit legacy),,YUV420 (8-bit CSPS),YUV420 (10-bit CSPS),YUV422 (8-bit),YUV422 (10-bit),,,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,User def. 1,User def. 2,User def. 3,User def. 4,User def. 5,User def. 6,User def. 7,User def. 8,?..." bitfld.long 0x00 0.--1. " VIRTUAL_CHANNEL ,Set virtual channel for data interleave" "0,1,2,3" else group.long 0x40++0x03 line.long 0x00 "ISP_CONFIG_CH0,ISP Configuration Register Of CH0" hexmask.long.byte 0x00 24.--31. 1. " MEM_FULL_GAP ,MEM_FULL_GAP" bitfld.long 0x00 12. " DOUBLE_CMPNT ,Double component per clock cycle in YUV422 formats" "Single,Double" bitfld.long 0x00 11. " PARALLEL ,The outer bus width of CSIS V3.3" "Normal,32-bit data alignment" bitfld.long 0x00 10. " RGB_SWAP ,Swapping RGB sequence" "Not swapped,Swapped" textline " " bitfld.long 0x00 9. " DECOMP_PREDICT ,Decompress prediction mode of CH0" "Simple,Advanced" bitfld.long 0x00 8. " DECOMP_EN ,Decompress enable" "Disabled,Enabled" bitfld.long 0x00 2.--7. " DATAFORMAT ,Image data format" ",,,,,,,,,,,,,,,,,,,,,,,,YUV420 (8-bit),YUV420 (10-bit),YUV420 (8-bit legacy),,YUV420 (8-bit CSPS),YUV420 (10-bit CSPS),YUV422 (8-bit),YUV422 (10-bit),,,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,User def. 1,User def. 2,User def. 3,User def. 4,User def. 5,User def. 6,User def. 7,User def. 8,?..." bitfld.long 0x00 0.--1. " VIRTUAL_CHANNEL ,Set virtual channel for data interleave" "0,1,2,3" endif group.long 0x44++0x07 line.long 0x00 "ISP_RESOL_CH0,ISP Image Resolution Register Of CH0" hexmask.long.word 0x00 16.--31. 1. " VRESOL ,Vertical image resolution" hexmask.long.word 0x00 0.--15. 1. " HRESOL ,Horizontal Image resolution" line.long 0x04 "ISP_SYNC_CH0,ISP SYNC Register Of CH0" bitfld.long 0x04 18.--23. " HSYNC_LINTV ,Interval between hsync falling and hsync rising" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 12.--17. " VSYNC_SINTV ,Interval between vsync rising and first hsync rising" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 0.--11. 1. " VSYNC_EINTV ,Interval between last hsync falling and vsync falling" rgroup.long 0x80++0x0B line.long 0x00 "SDW_CONFIG_CH0,Shadow Configuration Register Of CH0" hexmask.long.byte 0x00 24.--31. 1. " NAMEMEM_FULL_GAP_SDW ,Current MEM_FULL_GAP" bitfld.long 0x00 12. " DOUBLE_CMPNT_SDW ,Current double component" "Single,Double" bitfld.long 0x00 11. " PARALLEL_SDW ,Current parallel" "Normal,32-bit data alignment" bitfld.long 0x00 10. " RGB_SWAP_SDW ,Current RGB_SWAP" "Not swapped,Swapped" textline " " bitfld.long 0x00 9. " DECOMP_PREDICT_SDW ,Current decompress prediction mode" "Simple,Advanced" bitfld.long 0x00 8. " DECOMP_EN_SDW ,Current decompress enable" "Disabled,Enabled" bitfld.long 0x00 2.--7. " DATAFORMAT ,Current image data format" ",,,,,,,,,,,,,,,,,,,,,,,,YUV420 (8-bit),YUV420 (10-bit),YUV420 (8-bit legacy),,YUV420 (8-bit CSPS),YUV420 (10-bit CSPS),YUV422 (8-bit),YUV422 (10-bit),,,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,User def. 1,User def. 2,User def. 3,User def. 4,User def. 5,User def. 6,User def. 7,User def. 8,?..." bitfld.long 0x00 0.--1. " VIRTUAL_CHANNEL ,Current virtual channel" "0,1,2,3" line.long 0x04 "SDW_RESOL_CH0,Shadow Resolution Register Of CH0" hexmask.long.word 0x04 16.--31. 1. " VRESOL_SDW ,Current vertical image resolution" hexmask.long.word 0x04 0.--15. 1. " HRESOL_SDW ,Current horizontal image resolution" line.long 0x08 "SDW_SYNC_CH0,Shadow SYNC Register Of CH0" bitfld.long 0x08 18.--23. " HSYNC_LINTV_SDW ,Current interval between hsync falling and hsync rising (Line interval)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 12.--17. " VSYNC_SINTV_SDW ,Current interval between vsync rising and first hsync rising" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 0.--11. 1. " VSYNC_EINTV_SDW ,Current interval between last hsync falling and vsync falling" textline " " group.long 0xC0++0x0B line.long 0x00 "DBG_CTRL,Debug Control Register" bitfld.long 0x00 15. " DBG_FORCE_UPDATE[3] ,Update shadow reg for CH3" "Normally update,Forced update" bitfld.long 0x00 14. " DBG_FORCE_UPDATE[2] ,Update shadow reg for CH2" "Normally update,Forced update" textline " " bitfld.long 0x00 13. " DBG_FORCE_UPDATE[1] ,Update shadow reg for CH1" "Normally update,Forced update" bitfld.long 0x00 12. " DBG_FORCE_UPDATE[0] ,Update shadow reg for CH0" "Normally update,Forced update" textline " " bitfld.long 0x00 11. " DBG_DONT_STOP_LAST_LINE[3] ,Ignore STOP_REQ from ISP at the LAST_LINE for CH3" "Not ignored,Ignored" bitfld.long 0x00 10. " DBG_DONT_STOP_LAST_LINE[2] ,Ignore STOP_REQ from ISP at the LAST_LINE for CH2" "Not ignored,Ignored" textline " " bitfld.long 0x00 9. " DBG_DONT_STOP_LAST_LINE[1] ,Ignore STOP_REQ from ISP at the LAST_LINE for CH1" "Not ignored,Ignored" bitfld.long 0x00 8. " DBG_DONT_STOP_LAST_LINE[0] ,Ignore STOP_REQ from ISP at the LAST_LINE for CH0" "Not ignored,Ignored" textline " " bitfld.long 0x00 7. " DBG_BLK_EXC_FRAME[3] ,Blockes the exceeded frame for CH3" "Not blocked,Blocked" bitfld.long 0x00 6. " DBG_BLK_EXC_FRAME[2] ,Blockes the exceeded frame for CH2" "Not blocked,Blocked" textline " " bitfld.long 0x00 5. " DBG_BLK_EXC_FRAME[1] ,Blockes the exceeded frame for CH1" "Not blocked,Blocked" bitfld.long 0x00 4. " DBG_BLK_EXC_FRAME[0] ,Blockes the exceeded frame for CH0" "Not blocked,Blocked" textline " " bitfld.long 0x00 3. " DBG_CH_OUTPUT[3] ,Forces CH3 output to 1" "Not forced,Forced" bitfld.long 0x00 2. " DBG_CH_OUTPUT[2] ,Forces CH2 output to 1" "Not forced,Forced" textline " " bitfld.long 0x00 1. " DBG_CH_OUTPUT[1] ,Forces CH1 output to 1" "Not forced,Forced" bitfld.long 0x00 0. " DBG_CH_OUTPUT[0] ,Forces CH0 output to 1" "Not forced,Forced" textline " " line.long 0x04 "DBG_INTR_MSK,Debug Interrupt Mask" bitfld.long 0x04 25. " DT_NOT_SUPPORT ,DT_NOT_SUPPORT" "Masked,Unmasked" bitfld.long 0x04 24. " DT_IGNORE ,DT_IGNORE" "Masked,Unmasked" textline " " bitfld.long 0x04 23. " ERR_FRAME_SIZE[3] ,Error frame size for CH3" "Masked,Unmasked" bitfld.long 0x04 22. " ERR_FRAME_SIZE[2] ,Error frame size for CH2" "Masked,Unmasked" bitfld.long 0x04 21. " ERR_FRAME_SIZE[1] ,Error frame size for CH1" "Masked,Unmasked" bitfld.long 0x04 20. " ERR_FRAME_SIZE[0] ,Error frame size for CH0" "Masked,Unmasked" textline " " bitfld.long 0x04 19. " TRUNCATED_FRAME[3] ,Truncated frame for CH3" "Masked,Unmasked" bitfld.long 0x04 18. " TRUNCATED_FRAME[2] ,Truncated frame for CH2" "Masked,Unmasked" bitfld.long 0x04 17. " TRUNCATED_FRAME[1] ,Truncated frame for CH1" "Masked,Unmasked" bitfld.long 0x04 16. " TRUNCATED_FRAME[0] ,Truncated frame for CH0" "Masked,Unmasked" textline " " bitfld.long 0x04 15. " EARLY_FE[3] ,Early FE for CH3" "Masked,Unmasked" bitfld.long 0x04 14. " EARLY_FE[2] ,Early FE for CH2" "Masked,Unmasked" bitfld.long 0x04 13. " EARLY_FE[1] ,Early FE for CH1" "Masked,Unmasked" bitfld.long 0x04 12. " EARLY_FE[0] ,Early FE for CH0" "Masked,Unmasked" textline " " bitfld.long 0x04 11. " EARLY_FS[3] ,Early FS for CH3" "Masked,Unmasked" bitfld.long 0x04 10. " EARLY_FS[2] ,Early FS for CH2" "Masked,Unmasked" bitfld.long 0x04 9. " EARLY_FS[1] ,Early FS for CH1" "Masked,Unmasked" bitfld.long 0x04 8. " EARLY_FS[0] ,Early FS for CH0" "Masked,Unmasked" textline " " bitfld.long 0x04 7. " CAM_VSYNC_FALL[3] ,CAM_VSYNC_FALL for CH3" "Masked,Unmasked" bitfld.long 0x04 6. " CAM_VSYNC_FALL[2] ,CAM_VSYNC_FALL for CH2" "Masked,Unmasked" bitfld.long 0x04 5. " CAM_VSYNC_FALL[1] ,CAM_VSYNC_FALL for CH1" "Masked,Unmasked" bitfld.long 0x04 4. " CAM_VSYNC_FALL[0] ,CAM_VSYNC_FALL for CH0" "Masked,Unmasked" textline " " bitfld.long 0x04 3. " CAM_VSYNC_RISE[3] ,CAM_VSYNC_RISE for CH3" "Masked,Unmasked" bitfld.long 0x04 2. " CAM_VSYNC_RISE[2] ,CAM_VSYNC_RISE for CH2" "Masked,Unmasked" bitfld.long 0x04 1. " CAM_VSYNC_RISE[1] ,CAM_VSYNC_RISE for CH1" "Masked,Unmasked" bitfld.long 0x04 0. " CAM_VSYNC_RISE[0] ,CAM_VSYNC_RISE for CH0" "Masked,Unmasked" line.long 0x08 "DBG_INTR_SRC,Debug Interrupt Mask" bitfld.long 0x08 25. " DT_NOT_SUPPORT ,The data type of the received packet is not supported (Rgb444 or RGB555)" "No interrupt,Interrupt" bitfld.long 0x08 24. " DT_IGNORE ,The data type of the received packet is ignored (Null or BLANKING)" "No interrupt,Interrupt" textline " " bitfld.long 0x08 23. " ERR_FRAME_SIZE[3] ,The received frame is not matched with the configured for CH3" "No interrupt,Interrupt" bitfld.long 0x08 22. " ERR_FRAME_SIZE[2] ,The received frame is not matched with the configured for CH2" "No interrupt,Interrupt" bitfld.long 0x08 21. " ERR_FRAME_SIZE[1] ,The received frame is not matched with the configured for CH1" "No interrupt,Interrupt" bitfld.long 0x08 20. " ERR_FRAME_SIZE[0] ,The received frame is not matched with the configured for CH0" "No interrupt,Interrupt" textline " " bitfld.long 0x08 19. " TRUNCATED_FRAME[3] ,Truncated frame is received for CH3" "No interrupt,Interrupt" bitfld.long 0x08 18. " TRUNCATED_FRAME[2] ,Truncated frame is received for CH2" "No interrupt,Interrupt" bitfld.long 0x08 17. " TRUNCATED_FRAME[1] ,Truncated frame is received for CH1" "No interrupt,Interrupt" bitfld.long 0x08 16. " TRUNCATED_FRAME[0] ,Truncated frame is received for CH0" "No interrupt,Interrupt" textline " " bitfld.long 0x08 15. " EARLY_FE[3] ,Frame end packet is received during transfer of image for CH3" "No interrupt,Interrupt" bitfld.long 0x08 14. " EARLY_FE[2] ,Frame end packet is received during transfer of image for CH2" "No interrupt,Interrupt" bitfld.long 0x08 13. " EARLY_FE[1] ,Frame end packet is received during transfer of image for CH1" "No interrupt,Interrupt" bitfld.long 0x08 12. " EARLY_FE[0] ,Frame end packet is received during transfer of image for CH0" "No interrupt,Interrupt" textline " " bitfld.long 0x08 11. " EARLY_FS[3] ,Frame start packet is received during transfer of image for CH3" "No interrupt,Interrupt" bitfld.long 0x08 10. " EARLY_FS[2] ,Frame start packet is received during transfer of image for CH2" "No interrupt,Interrupt" bitfld.long 0x08 9. " EARLY_FS[1] ,Frame start packet is received during transfer of image for CH1" "No interrupt,Interrupt" bitfld.long 0x08 8. " EARLY_FS[0] ,Frame start packet is received during transfer of image for CH0" "No interrupt,Interrupt" textline " " bitfld.long 0x08 7. " CAM_VSYNC_FALL[3] ,The falling of vsync in the CAM I/F for CH3" "No interrupt,Interrupt" bitfld.long 0x08 6. " CAM_VSYNC_FALL[2] ,The falling of vsync in the CAM I/F for CH2" "No interrupt,Interrupt" bitfld.long 0x08 5. " CAM_VSYNC_FALL[1] ,The falling of vsync in the CAM I/F for CH1" "No interrupt,Interrupt" bitfld.long 0x08 4. " CAM_VSYNC_FALL[0] ,The falling of vsync in the CAM I/F for CH0" "No interrupt,Interrupt" textline " " bitfld.long 0x08 3. " CAM_VSYNC_RISE[3] ,The rising of vsync in the CAM I/F for CH3" "No interrupt,Interrupt" bitfld.long 0x08 2. " CAM_VSYNC_RISE[2] ,The rising of vsync in the CAM I/F for CH2" "No interrupt,Interrupt" bitfld.long 0x08 1. " CAM_VSYNC_RISE[1] ,The rising of vsync in the CAM I/F for CH1" "No interrupt,Interrupt" bitfld.long 0x08 0. " CAM_VSYNC_RISE[0] ,The rising of vsync in the CAM I/F for CH0" "No interrupt,Interrupt" rgroup.long 0x2000++0x03 line.long 0x00 "NON_IMG_DATA,Non Image Data" width 0x0B tree.end sif (!(CPUIS("IMX7SOLO-CM4")||CPUIS("IMX7SOLO-CA7"))) tree "EPDC (Electrophoretic Display Controller)" base ad:0x306F0000 width 18. group.long 0x00++0x13 line.long 0x00 "CTRL,EPDC Control Register" bitfld.long 0x00 31. " SFTRST ,Normal EPDC operation" "Enabled,Disabled" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated" bitfld.long 0x00 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x00 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x04 "CTRL_SET,EPDC Control Set Register" bitfld.long 0x04 31. " SFTRST ,Normal EPDC operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap of the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x04 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap of the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x08 "CTRL_CLR,EPDC Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Normal EPDC operation" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x08 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x0C "CTRL_TOG,EPDC Control Toggle Register" bitfld.long 0x0C 31. " SFTRST ,Normal EPDC operation" "Not toggled,Toggled" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled" bitfld.long 0x0C 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x0C 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x10 "WB_ADDR_TCE,EPDC Working Buffer Address For TCE" group.long 0x20++0x03 line.long 0x00 "WVADDR,EPDC Waveform Address Pointer" group.long 0x30++0x03 line.long 0x00 "WB_ADDR,EPDC Working Buffer Address" group.long 0x40++0x03 line.long 0x00 "RES,EPDC Screen Resolution" hexmask.long.word 0x00 16.--28. 1. " VERTICAL ,Vertical resoltion (In pixels)" hexmask.long.word 0x00 0.--12. 1. " HORIZONTAL ,Horizontal resolution (In pixels)" if (((per.l(ad:0x306F0000+0x50))&0x3000)==(0x2000||0x3000)) group.long 0x50++0x0F line.long 0x00 "FORMAT,EPDC Format Control Register" bitfld.long 0x00 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Truncate,Rounding" hexmask.long.byte 0x00 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x00 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "Yes,No" bitfld.long 0x00 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x00 11. " WB_COMPRESS ,Indicates whether the working buffer is compressed" "Not compressed,Compressed" bitfld.long 0x00 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x00 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x04 "FORMAT_SET,EPDC Format Control Set Register" bitfld.long 0x04 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Set" hexmask.long.byte 0x04 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x04 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "No effect,Set" bitfld.long 0x04 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x04 11. " WB_COMPRESS ,Indicates whether the working buffer is compressed" "No effect,Set" bitfld.long 0x04 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x04 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x08 "FORMAT_CLR,EPDC Format Control Clear Register" bitfld.long 0x08 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Clear" hexmask.long.byte 0x08 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x08 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "No effect,Clear" bitfld.long 0x08 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x08 11. " WB_COMPRESS ,Indicates whether the working buffer is compressed" "No effect,Clear" bitfld.long 0x08 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x08 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x0C "FORMAT_TOG,EPDC Format Control Toggle Register" bitfld.long 0x0C 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Not toggled,Toggled" hexmask.long.byte 0x0C 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x0C 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "Not toggled,Toggled" bitfld.long 0x0C 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x0C 11. " WB_COMPRESS ,Indicates whether the working buffer is compressed" "Not toggled,Toggled" bitfld.long 0x0C 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x0C 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" else group.long 0x50++0x0F line.long 0x00 "FORMAT,EPDC Format Control Register" bitfld.long 0x00 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Truncate,Rounding" hexmask.long.byte 0x00 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x00 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "Yes,No" bitfld.long 0x00 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x00 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x00 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x04 "FORMAT_SET,EPDC Format Control Set Register" bitfld.long 0x04 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Set" hexmask.long.byte 0x04 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x04 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "No effect,Set" bitfld.long 0x04 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x04 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x04 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x08 "FORMAT_CLR,EPDC Format Control Clear Register" bitfld.long 0x08 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Clear" hexmask.long.byte 0x08 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x08 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "No effect,Clear" bitfld.long 0x08 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x08 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x08 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x0C "FORMAT_TOG,EPDC Format Control Toggle Register" bitfld.long 0x0C 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Not toggled,Toggled" hexmask.long.byte 0x0C 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" bitfld.long 0x0C 14. " WB_ADDR_NO_COPY ,Copies automatically WB_ADDR to WB_ADDR_TCE before starting every frame" "Not toggled,Toggled" bitfld.long 0x0C 12.--13. " WB_TYPE ,Working buffer type" "Internal,Waveform,16 bit external,32 bit external" textline " " bitfld.long 0x0C 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x0C 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" endif group.long 0x60++0x03 line.long 0x00 "WB_FIELD0,Working Buffer Field Setting" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,Used to either force field into a fixed value or compare to wb field to mask off the pixel" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO_FIXED,FIXED,NE_FIXED,EQ_FIXED" bitfld.long 0x00 13.--15. " USAGE ,Usage" "NOT_USED,,,PARTIAL,LUT,CP,NP,PTS" bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x03 line.long 0x00 "WB_FIELD1,Working Buffer Field Setting" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,Used to either force field into a fixed value or compare to wb field to mask off the pixel" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO_FIXED,FIXED,NE_FIXED,EQ_FIXED" bitfld.long 0x00 13.--15. " USAGE ,Usage" "NOT_USED,,,PARTIAL,LUT,CP,NP,PTS" bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "WB_FIELD2,Working Buffer Field Setting" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,Used to either force field into a fixed value or compare to wb field to mask off the pixel" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO_FIXED,FIXED,NE_FIXED,EQ_FIXED" bitfld.long 0x00 13.--15. " USAGE ,Usage" "NOT_USED,,,PARTIAL,LUT,CP,NP,PTS" bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "WB_FIELD3,Working Buffer Field Setting" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,Used to either force field into a fixed value or compare to wb field to mask off the pixel" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO_FIXED,FIXED,NE_FIXED,EQ_FIXED" bitfld.long 0x00 13.--15. " USAGE ,Usage" "NOT_USED,,,PARTIAL,LUT,CP,NP,PTS" bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x0F line.long 0x00 "FIFOCTRL,EPDC FIFO Control Register" bitfld.long 0x00 31. " EN_PRIOR ,Enable watermark-based priority elevation mechanism" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" hexmask.long.byte 0x00 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x04 "FIFOCTRL_SET,EPDC FIFO Control Set Register" bitfld.long 0x04 31. " EN_PRIOR ,Enable watermark-based priority elevation mechanism" "No effect,Set" hexmask.long.byte 0x04 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" hexmask.long.byte 0x04 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x04 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x08 "FIFOCTRL_CLR,EPDC FIFO Control Clear Register" bitfld.long 0x08 31. " EN_PRIOR ,Enable watermark-based priority elevation mechanism" "No effect,Clear" hexmask.long.byte 0x08 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" hexmask.long.byte 0x08 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x08 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x0C "FIFOCTRL_TOG,EPDC FIFO Control Toggle Register" bitfld.long 0x0C 31. " EN_PRIOR ,Enable watermark-based priority elevation mechanism" "Not toggled,Toggled" hexmask.long.byte 0x0C 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" hexmask.long.byte 0x0C 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x0C 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" group.long 0x100++0x03 line.long 0x00 "UPD_ADDR,EPDC Update Region Address" group.long 0x110++0x03 line.long 0x00 "UPD_STRIDE,EPDC Update Region Stride" group.long 0x120++0x03 line.long 0x00 "UPD_CORD,EPDC Update Command Co-ordinate" hexmask.long.word 0x00 16.--28. 1. " YCORD ,Y co-ordinate for incoming region update" hexmask.long.word 0x00 0.--12. 1. " XCORD ,X co-ordinate for incoming region update" group.long 0x140++0x03 line.long 0x00 "UPD_SIZE,EPDC Update Command Size" hexmask.long.word 0x00 16.--28. 1. " HEIGHT ,Height (In pixels)" hexmask.long.word 0x00 0.--12. 1. " WIDTH ,Width (In pixels)" group.long 0x160++0x0F line.long 0x00 "UPD_CTRL,EPDC Update Command Control" bitfld.long 0x00 31. " USE_FIXED ,Use fixed pixel values" "Not used,Used" bitfld.long 0x00 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x00 5. " STANDBY ,STANDBY" "No,Yes" bitfld.long 0x00 4. " NO_LUT_CANCEL ,EPDC will cancel LUT loading for void update" "No,Yes" textline " " bitfld.long 0x00 3. " PAUSE ,Automatical waveform mode selection" "AUTO,MANUAL" bitfld.long 0x00 2. " AUTOWV ,Enable automatical waveform mode selection" "Disabled,Enabled" bitfld.long 0x00 1. " DRY_RUN ,Enable dry run mode" "Disabled,Enabled" bitfld.long 0x00 0. " UPDATE_MODE ,Update mode" "Partial,Full" line.long 0x04 "UPD_CTRL_SET,EPDC Update Command Control Set" bitfld.long 0x04 31. " USE_FIXED ,Use fixed pixel values" "No effect,Set" bitfld.long 0x04 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x04 5. " STANDBY ,STANDBY" "No effect,Set" bitfld.long 0x04 4. " NO_LUT_CANCEL ,EPDC will cancel LUT loading for void update" "No effect,Set" textline " " bitfld.long 0x04 3. " PAUSE ,Automatical waveform mode selection" "No effect,Set" bitfld.long 0x04 2. " AUTOWV ,Enable automatical waveform mode selection" "No effect,Set" bitfld.long 0x04 1. " DRY_RUN ,Enable dry run mode" "No effect,Set" bitfld.long 0x04 0. " UPDATE_MODE ,Update mode" "No effect,Set" line.long 0x08 "UPD_CTRL_CLR,EPDC Update Command Control Clear" bitfld.long 0x08 31. " USE_FIXED ,Use fixed pixel values" "No effect,Clear" bitfld.long 0x08 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x08 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x08 5. " STANDBY ,STANDBY" "No effect,Clear" bitfld.long 0x08 4. " NO_LUT_CANCEL ,EPDC will cancel LUT loading for void update" "No effect,Clear" textline " " bitfld.long 0x08 3. " PAUSE ,Automatical waveform mode selection" "No effect,Clear" bitfld.long 0x08 2. " AUTOWV ,Enable automatical waveform mode selection" "No effect,Clear" bitfld.long 0x08 1. " DRY_RUN ,Enable dry run mode" "No effect,Clear" bitfld.long 0x08 0. " UPDATE_MODE ,Update mode" "No effect,Clear" line.long 0x0C "UPD_CTRL,EPDC Update Command Control Toggle" bitfld.long 0x0C 31. " USE_FIXED ,Use fixed pixel values" "Not toggled,Toggled" bitfld.long 0x0C 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0C 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x0C 5. " STANDBY ,STANDBY" "Not toggled,Toggled" bitfld.long 0x0C 4. " NO_LUT_CANCEL ,EPDC will cancel LUT loading for void update" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " PAUSE ,Automatical waveform mode selection" "Not toggled,Toggled" bitfld.long 0x0C 2. " AUTOWV ,Enable automatical waveform mode selection" "Not toggled,Toggled" bitfld.long 0x0C 1. " DRY_RUN ,Enable dry run mode" "Not toggled,Toggled" bitfld.long 0x0C 0. " UPDATE_MODE ,Update mode" "Not toggled,Toggled" group.long 0x180++0x0F line.long 0x00 "UPD_FIXED,EPDC Update Fixed Pixel Control" bitfld.long 0x00 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not updated,Updated" bitfld.long 0x00 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not updated,Updated" hexmask.long.byte 0x00 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x00 0.--7. 1. " FIXCP ,CP value" line.long 0x04 "UPD_FIXED_SET,EPDC Update Fixed Pixel Control Set" bitfld.long 0x04 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Set" bitfld.long 0x04 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Set" hexmask.long.byte 0x04 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x04 0.--7. 1. " FIXCP ,CP value" line.long 0x08 "UPD_FIXED_CLR,EPDC Update Fixed Pixel Control Clear" bitfld.long 0x08 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Clear" bitfld.long 0x08 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Clear" hexmask.long.byte 0x08 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x08 0.--7. 1. " FIXCP ,CP value" line.long 0x0C "UPD_FIXED_TOG,EPDC Update Fixed Pixel Control Toggle" bitfld.long 0x0C 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not toggled,Toggled" bitfld.long 0x0C 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not toggled,Toggled" hexmask.long.byte 0x0C 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x0C 0.--7. 1. " FIXCP ,CP value" group.long 0x1A0++0x03 line.long 0x00 "TEMP,EPDC Temperature Register" group.long 0x1C0++0x03 line.long 0x00 "AUTOWV_LUT,Waveform Mode Lookup Table Control Register" hexmask.long.byte 0x00 16.--23. 1. " DATA ,DATA" bitfld.long 0x00 0.--2. " ADDR ,ADDR" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x0F line.long 0x00 "LUT_STANDBY1,EPDC LUT Standby Register For LUT 31~0" bitfld.long 0x00 31. " LUT31 ,LUT 31 standby control" "0,1" bitfld.long 0x00 30. " LUT30 ,LUT 30 standby control" "0,1" bitfld.long 0x00 29. " LUT29 ,LUT 29 standby control" "0,1" bitfld.long 0x00 28. " LUT28 ,LUT 28 standby control" "0,1" textline " " bitfld.long 0x00 27. " LUT27 ,LUT 27 standby control" "0,1" bitfld.long 0x00 26. " LUT26 ,LUT 26 standby control" "0,1" bitfld.long 0x00 25. " LUT25 ,LUT 25 standby control" "0,1" bitfld.long 0x00 24. " LUT24 ,LUT 24 standby control" "0,1" textline " " bitfld.long 0x00 23. " LUT23 ,LUT 23 standby control" "0,1" bitfld.long 0x00 22. " LUT22 ,LUT 22 standby control" "0,1" bitfld.long 0x00 21. " LUT21 ,LUT 21 standby control" "0,1" bitfld.long 0x00 20. " LUT20 ,LUT 20 standby control" "0,1" textline " " bitfld.long 0x00 19. " LUT19 ,LUT 19 standby control" "0,1" bitfld.long 0x00 18. " LUT18 ,LUT 18 standby control" "0,1" bitfld.long 0x00 17. " LUT17 ,LUT 17 standby control" "0,1" bitfld.long 0x00 16. " LUT16 ,LUT 16 standby control" "0,1" textline " " bitfld.long 0x00 15. " LUT15 ,LUT 15 standby control" "0,1" bitfld.long 0x00 14. " LUT14 ,LUT 14 standby control" "0,1" bitfld.long 0x00 13. " LUT13 ,LUT 13 standby control" "0,1" bitfld.long 0x00 12. " LUT12 ,LUT 12 standby control" "0,1" textline " " bitfld.long 0x00 11. " LUT11 ,LUT 11 standby control" "0,1" bitfld.long 0x00 10. " LUT10 ,LUT 10 standby control" "0,1" bitfld.long 0x00 9. " LUT9 ,LUT 9 standby control" "0,1" bitfld.long 0x00 8. " LUT8 ,LUT 8 standby control" "0,1" textline " " bitfld.long 0x00 7. " LUT7 ,LUT 7 standby control" "0,1" bitfld.long 0x00 6. " LUT6 ,LUT 6 standby control" "0,1" bitfld.long 0x00 5. " LUT5 ,LUT 5 standby control" "0,1" bitfld.long 0x00 4. " LUT4 ,LUT 4 standby control" "0,1" textline " " bitfld.long 0x00 3. " LUT3 ,LUT 3 standby control" "0,1" bitfld.long 0x00 2. " LUT2 ,LUT 2 standby control" "0,1" bitfld.long 0x00 1. " LUT1 ,LUT 1 standby control" "0,1" bitfld.long 0x00 0. " LUT0 ,LUT 0 standby control" "0,1" line.long 0x04 "LUT_STANDBY1_SET,EPDC LUT Standby Register For LUT 31~0" bitfld.long 0x04 31. " LUT31 ,LUT 31 standby control" "No effect,Set" bitfld.long 0x04 30. " LUT30 ,LUT 30 standby control" "No effect,Set" bitfld.long 0x04 29. " LUT29 ,LUT 29 standby control" "No effect,Set" bitfld.long 0x04 28. " LUT28 ,LUT 28 standby control" "No effect,Set" textline " " bitfld.long 0x04 27. " LUT27 ,LUT 27 standby control" "No effect,Set" bitfld.long 0x04 26. " LUT26 ,LUT 26 standby control" "No effect,Set" bitfld.long 0x04 25. " LUT25 ,LUT 25 standby control" "No effect,Set" bitfld.long 0x04 24. " LUT24 ,LUT 24 standby control" "No effect,Set" textline " " bitfld.long 0x04 23. " LUT23 ,LUT 23 standby control" "No effect,Set" bitfld.long 0x04 22. " LUT22 ,LUT 22 standby control" "No effect,Set" bitfld.long 0x04 21. " LUT21 ,LUT 21 standby control" "No effect,Set" bitfld.long 0x04 20. " LUT20 ,LUT 20 standby control" "No effect,Set" textline " " bitfld.long 0x04 19. " LUT19 ,LUT 19 standby control" "No effect,Set" bitfld.long 0x04 18. " LUT18 ,LUT 18 standby control" "No effect,Set" bitfld.long 0x04 17. " LUT17 ,LUT 17 standby control" "No effect,Set" bitfld.long 0x04 16. " LUT16 ,LUT 16 standby control" "No effect,Set" textline " " bitfld.long 0x04 15. " LUT15 ,LUT 15 standby control" "No effect,Set" bitfld.long 0x04 14. " LUT14 ,LUT 14 standby control" "No effect,Set" bitfld.long 0x04 13. " LUT13 ,LUT 13 standby control" "No effect,Set" bitfld.long 0x04 12. " LUT12 ,LUT 12 standby control" "No effect,Set" textline " " bitfld.long 0x04 11. " LUT11 ,LUT 11 standby control" "No effect,Set" bitfld.long 0x04 10. " LUT10 ,LUT 10 standby control" "No effect,Set" bitfld.long 0x04 9. " LUT9 ,LUT 9 standby control" "No effect,Set" bitfld.long 0x04 8. " LUT8 ,LUT 8 standby control" "No effect,Set" textline " " bitfld.long 0x04 7. " LUT7 ,LUT 7 standby control" "No effect,Set" bitfld.long 0x04 6. " LUT6 ,LUT 6 standby control" "No effect,Set" bitfld.long 0x04 5. " LUT5 ,LUT 5 standby control" "No effect,Set" bitfld.long 0x04 4. " LUT4 ,LUT 4 standby control" "No effect,Set" textline " " bitfld.long 0x04 3. " LUT3 ,LUT 3 standby control" "No effect,Set" bitfld.long 0x04 2. " LUT2 ,LUT 2 standby control" "No effect,Set" bitfld.long 0x04 1. " LUT1 ,LUT 1 standby control" "No effect,Set" bitfld.long 0x04 0. " LUT0 ,LUT 0 standby control" "No effect,Set" line.long 0x08 "LUT_STANDBY1_CLR,EPDC LUT Standby Register For LUT 31~0" bitfld.long 0x08 31. " LUT31 ,LUT 31 standby control" "No effect,Clear" bitfld.long 0x08 30. " LUT30 ,LUT 30 standby control" "No effect,Clear" bitfld.long 0x08 29. " LUT29 ,LUT 29 standby control" "No effect,Clear" bitfld.long 0x08 28. " LUT28 ,LUT 28 standby control" "No effect,Clear" textline " " bitfld.long 0x08 27. " LUT27 ,LUT 27 standby control" "No effect,Clear" bitfld.long 0x08 26. " LUT26 ,LUT 26 standby control" "No effect,Clear" bitfld.long 0x08 25. " LUT25 ,LUT 25 standby control" "No effect,Clear" bitfld.long 0x08 24. " LUT24 ,LUT 24 standby control" "No effect,Clear" textline " " bitfld.long 0x08 23. " LUT23 ,LUT 23 standby control" "No effect,Clear" bitfld.long 0x08 22. " LUT22 ,LUT 22 standby control" "No effect,Clear" bitfld.long 0x08 21. " LUT21 ,LUT 21 standby control" "No effect,Clear" bitfld.long 0x08 20. " LUT20 ,LUT 20 standby control" "No effect,Clear" textline " " bitfld.long 0x08 19. " LUT19 ,LUT 19 standby control" "No effect,Clear" bitfld.long 0x08 18. " LUT18 ,LUT 18 standby control" "No effect,Clear" bitfld.long 0x08 17. " LUT17 ,LUT 17 standby control" "No effect,Clear" bitfld.long 0x08 16. " LUT16 ,LUT 16 standby control" "No effect,Clear" textline " " bitfld.long 0x08 15. " LUT15 ,LUT 15 standby control" "No effect,Clear" bitfld.long 0x08 14. " LUT14 ,LUT 14 standby control" "No effect,Clear" bitfld.long 0x08 13. " LUT13 ,LUT 13 standby control" "No effect,Clear" bitfld.long 0x08 12. " LUT12 ,LUT 12 standby control" "No effect,Clear" textline " " bitfld.long 0x08 11. " LUT11 ,LUT 11 standby control" "No effect,Clear" bitfld.long 0x08 10. " LUT10 ,LUT 10 standby control" "No effect,Clear" bitfld.long 0x08 9. " LUT9 ,LUT 9 standby control" "No effect,Clear" bitfld.long 0x08 8. " LUT8 ,LUT 8 standby control" "No effect,Clear" textline " " bitfld.long 0x08 7. " LUT7 ,LUT 7 standby control" "No effect,Clear" bitfld.long 0x08 6. " LUT6 ,LUT 6 standby control" "No effect,Clear" bitfld.long 0x08 5. " LUT5 ,LUT 5 standby control" "No effect,Clear" bitfld.long 0x08 4. " LUT4 ,LUT 4 standby control" "No effect,Clear" textline " " bitfld.long 0x08 3. " LUT3 ,LUT 3 standby control" "No effect,Clear" bitfld.long 0x08 2. " LUT2 ,LUT 2 standby control" "No effect,Clear" bitfld.long 0x08 1. " LUT1 ,LUT 1 standby control" "No effect,Clear" bitfld.long 0x08 0. " LUT0 ,LUT 0 standby control" "No effect,Clear" line.long 0x0C "LUT_STANDBY1_TOG,EPDC LUT Standby Register For LUT 31~0" bitfld.long 0x0C 31. " LUT31 ,LUT 31 standby control" "Not toggled,Toggled" bitfld.long 0x0C 30. " LUT30 ,LUT 30 standby control" "Not toggled,Toggled" bitfld.long 0x0C 29. " LUT29 ,LUT 29 standby control" "Not toggled,Toggled" bitfld.long 0x0C 28. " LUT28 ,LUT 28 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 27. " LUT27 ,LUT 27 standby control" "Not toggled,Toggled" bitfld.long 0x0C 26. " LUT26 ,LUT 26 standby control" "Not toggled,Toggled" bitfld.long 0x0C 25. " LUT25 ,LUT 25 standby control" "Not toggled,Toggled" bitfld.long 0x0C 24. " LUT24 ,LUT 24 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " LUT23 ,LUT 23 standby control" "Not toggled,Toggled" bitfld.long 0x0C 22. " LUT22 ,LUT 22 standby control" "Not toggled,Toggled" bitfld.long 0x0C 21. " LUT21 ,LUT 21 standby control" "Not toggled,Toggled" bitfld.long 0x0C 20. " LUT20 ,LUT 20 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " LUT19 ,LUT 19 standby control" "Not toggled,Toggled" bitfld.long 0x0C 18. " LUT18 ,LUT 18 standby control" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT17 ,LUT 17 standby control" "Not toggled,Toggled" bitfld.long 0x0C 16. " LUT16 ,LUT 16 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 15. " LUT15 ,LUT 15 standby control" "Not toggled,Toggled" bitfld.long 0x0C 14. " LUT14 ,LUT 14 standby control" "Not toggled,Toggled" bitfld.long 0x0C 13. " LUT13 ,LUT 13 standby control" "Not toggled,Toggled" bitfld.long 0x0C 12. " LUT12 ,LUT 12 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " LUT11 ,LUT 11 standby control" "Not toggled,Toggled" bitfld.long 0x0C 10. " LUT10 ,LUT 10 standby control" "Not toggled,Toggled" bitfld.long 0x0C 9. " LUT9 ,LUT 9 standby control" "Not toggled,Toggled" bitfld.long 0x0C 8. " LUT8 ,LUT 8 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LUT7 ,LUT 7 standby control" "Not toggled,Toggled" bitfld.long 0x0C 6. " LUT6 ,LUT 6 standby control" "Not toggled,Toggled" bitfld.long 0x0C 5. " LUT5 ,LUT 5 standby control" "Not toggled,Toggled" bitfld.long 0x0C 4. " LUT4 ,LUT 4 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " LUT3 ,LUT 3 standby control" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUT2 ,LUT 2 standby control" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUT1 ,LUT 1 standby control" "Not toggled,Toggled" bitfld.long 0x0C 0. " LUT0 ,LUT 0 standby control" "Not toggled,Toggled" group.long 0x1F0++0x0F line.long 0x00 "LUT_STANDBY2,EPDC LUT Standby Register For LUT 63~32" bitfld.long 0x00 31. " LUT63 ,LUT 63 standby control" "0,1" bitfld.long 0x00 30. " LUT62 ,LUT 62 standby control" "0,1" bitfld.long 0x00 29. " LUT61 ,LUT 61 standby control" "0,1" bitfld.long 0x00 28. " LUT60 ,LUT 60 standby control" "0,1" textline " " bitfld.long 0x00 27. " LUT59 ,LUT 59 standby control" "0,1" bitfld.long 0x00 26. " LUT58 ,LUT 58 standby control" "0,1" bitfld.long 0x00 25. " LUT57 ,LUT 57 standby control" "0,1" bitfld.long 0x00 24. " LUT56 ,LUT 56 standby control" "0,1" textline " " bitfld.long 0x00 23. " LUT55 ,LUT 55 standby control" "0,1" bitfld.long 0x00 22. " LUT54 ,LUT 54 standby control" "0,1" bitfld.long 0x00 21. " LUT53 ,LUT 53 standby control" "0,1" bitfld.long 0x00 20. " LUT52 ,LUT 52 standby control" "0,1" textline " " bitfld.long 0x00 19. " LUT51 ,LUT 51 standby control" "0,1" bitfld.long 0x00 18. " LUT50 ,LUT 50 standby control" "0,1" bitfld.long 0x00 17. " LUT49 ,LUT 49 standby control" "0,1" bitfld.long 0x00 16. " LUT48 ,LUT 48 standby control" "0,1" textline " " bitfld.long 0x00 15. " LUT47 ,LUT 47 standby control" "0,1" bitfld.long 0x00 14. " LUT46 ,LUT 46 standby control" "0,1" bitfld.long 0x00 13. " LUT45 ,LUT 45 standby control" "0,1" bitfld.long 0x00 12. " LUT44 ,LUT 44 standby control" "0,1" textline " " bitfld.long 0x00 11. " LUT43 ,LUT 43 standby control" "0,1" bitfld.long 0x00 10. " LUT42 ,LUT 42 standby control" "0,1" bitfld.long 0x00 9. " LUT41 ,LUT 41 standby control" "0,1" bitfld.long 0x00 8. " LUT40 ,LUT 40 standby control" "0,1" textline " " bitfld.long 0x00 7. " LUT39 ,LUT 39 standby control" "0,1" bitfld.long 0x00 6. " LUT38 ,LUT 38 standby control" "0,1" bitfld.long 0x00 5. " LUT37 ,LUT 37 standby control" "0,1" bitfld.long 0x00 4. " LUT36 ,LUT 36 standby control" "0,1" textline " " bitfld.long 0x00 3. " LUT35 ,LUT 35 standby control" "0,1" bitfld.long 0x00 2. " LUT34 ,LUT 34 standby control" "0,1" bitfld.long 0x00 1. " LUT33 ,LUT 33 standby control" "0,1" bitfld.long 0x00 0. " LUT32 ,LUT 32 standby control" "0,1" line.long 0x04 "LUT_STANDBY2_SET,EPDC LUT Standby Register For LUT 63~32" bitfld.long 0x04 31. " LUT63 ,LUT 63 standby control" "No effect,Set" bitfld.long 0x04 30. " LUT62 ,LUT 62 standby control" "No effect,Set" bitfld.long 0x04 29. " LUT61 ,LUT 61 standby control" "No effect,Set" bitfld.long 0x04 28. " LUT60 ,LUT 60 standby control" "No effect,Set" textline " " bitfld.long 0x04 27. " LUT59 ,LUT 59 standby control" "No effect,Set" bitfld.long 0x04 26. " LUT58 ,LUT 58 standby control" "No effect,Set" bitfld.long 0x04 25. " LUT57 ,LUT 57 standby control" "No effect,Set" bitfld.long 0x04 24. " LUT56 ,LUT 56 standby control" "No effect,Set" textline " " bitfld.long 0x04 23. " LUT55 ,LUT 55 standby control" "No effect,Set" bitfld.long 0x04 22. " LUT54 ,LUT 54 standby control" "No effect,Set" bitfld.long 0x04 21. " LUT53 ,LUT 53 standby control" "No effect,Set" bitfld.long 0x04 20. " LUT52 ,LUT 52 standby control" "No effect,Set" textline " " bitfld.long 0x04 19. " LUT51 ,LUT 51 standby control" "No effect,Set" bitfld.long 0x04 18. " LUT50 ,LUT 50 standby control" "No effect,Set" bitfld.long 0x04 17. " LUT49 ,LUT 49 standby control" "No effect,Set" bitfld.long 0x04 16. " LUT48 ,LUT 48 standby control" "No effect,Set" textline " " bitfld.long 0x04 15. " LUT47 ,LUT 47 standby control" "No effect,Set" bitfld.long 0x04 14. " LUT46 ,LUT 46 standby control" "No effect,Set" bitfld.long 0x04 13. " LUT45 ,LUT 45 standby control" "No effect,Set" bitfld.long 0x04 12. " LUT44 ,LUT 44 standby control" "No effect,Set" textline " " bitfld.long 0x04 11. " LUT43 ,LUT 43 standby control" "No effect,Set" bitfld.long 0x04 10. " LUT42 ,LUT 42 standby control" "No effect,Set" bitfld.long 0x04 9. " LUT41 ,LUT 41 standby control" "No effect,Set" bitfld.long 0x04 8. " LUT40 ,LUT 40 standby control" "No effect,Set" textline " " bitfld.long 0x04 7. " LUT39 ,LUT 39 standby control" "No effect,Set" bitfld.long 0x04 6. " LUT38 ,LUT 38 standby control" "No effect,Set" bitfld.long 0x04 5. " LUT37 ,LUT 37 standby control" "No effect,Set" bitfld.long 0x04 4. " LUT36 ,LUT 36 standby control" "No effect,Set" textline " " bitfld.long 0x04 3. " LUT35 ,LUT 35 standby control" "No effect,Set" bitfld.long 0x04 2. " LUT34 ,LUT 34 standby control" "No effect,Set" bitfld.long 0x04 1. " LUT33 ,LUT 33 standby control" "No effect,Set" bitfld.long 0x04 0. " LUT32 ,LUT 32 standby control" "No effect,Set" line.long 0x08 "LUT_STANDBY2_CLR,EPDC LUT Standby Register For LUT 63~32" bitfld.long 0x08 31. " LUT63 ,LUT 63 standby control" "No effect,Clear" bitfld.long 0x08 30. " LUT62 ,LUT 62 standby control" "No effect,Clear" bitfld.long 0x08 29. " LUT61 ,LUT 61 standby control" "No effect,Clear" bitfld.long 0x08 28. " LUT60 ,LUT 60 standby control" "No effect,Clear" textline " " bitfld.long 0x08 27. " LUT59 ,LUT 59 standby control" "No effect,Clear" bitfld.long 0x08 26. " LUT58 ,LUT 58 standby control" "No effect,Clear" bitfld.long 0x08 25. " LUT57 ,LUT 57 standby control" "No effect,Clear" bitfld.long 0x08 24. " LUT56 ,LUT 56 standby control" "No effect,Clear" textline " " bitfld.long 0x08 23. " LUT55 ,LUT 55 standby control" "No effect,Clear" bitfld.long 0x08 22. " LUT54 ,LUT 54 standby control" "No effect,Clear" bitfld.long 0x08 21. " LUT53 ,LUT 53 standby control" "No effect,Clear" bitfld.long 0x08 20. " LUT52 ,LUT 52 standby control" "No effect,Clear" textline " " bitfld.long 0x08 19. " LUT51 ,LUT 51 standby control" "No effect,Clear" bitfld.long 0x08 18. " LUT50 ,LUT 50 standby control" "No effect,Clear" bitfld.long 0x08 17. " LUT49 ,LUT 49 standby control" "No effect,Clear" bitfld.long 0x08 16. " LUT48 ,LUT 48 standby control" "No effect,Clear" textline " " bitfld.long 0x08 15. " LUT47 ,LUT 47 standby control" "No effect,Clear" bitfld.long 0x08 14. " LUT46 ,LUT 46 standby control" "No effect,Clear" bitfld.long 0x08 13. " LUT45 ,LUT 45 standby control" "No effect,Clear" bitfld.long 0x08 12. " LUT44 ,LUT 44 standby control" "No effect,Clear" textline " " bitfld.long 0x08 11. " LUT43 ,LUT 43 standby control" "No effect,Clear" bitfld.long 0x08 10. " LUT42 ,LUT 42 standby control" "No effect,Clear" bitfld.long 0x08 9. " LUT41 ,LUT 41 standby control" "No effect,Clear" bitfld.long 0x08 8. " LUT40 ,LUT 40 standby control" "No effect,Clear" textline " " bitfld.long 0x08 7. " LUT39 ,LUT 39 standby control" "No effect,Clear" bitfld.long 0x08 6. " LUT38 ,LUT 38 standby control" "No effect,Clear" bitfld.long 0x08 5. " LUT37 ,LUT 37 standby control" "No effect,Clear" bitfld.long 0x08 4. " LUT36 ,LUT 36 standby control" "No effect,Clear" textline " " bitfld.long 0x08 3. " LUT35 ,LUT 35 standby control" "No effect,Clear" bitfld.long 0x08 2. " LUT34 ,LUT 34 standby control" "No effect,Clear" bitfld.long 0x08 1. " LUT33 ,LUT 33 standby control" "No effect,Clear" bitfld.long 0x08 0. " LUT32 ,LUT 32 standby control" "No effect,Clear" line.long 0x0C "LUT_STANDBY2_TOG,EPDC LUT Standby Register For LUT 63~32" bitfld.long 0x0C 31. " LUT63 ,LUT 63 standby control" "Not toggled,Toggled" bitfld.long 0x0C 30. " LUT62 ,LUT 62 standby control" "Not toggled,Toggled" bitfld.long 0x0C 29. " LUT61 ,LUT 61 standby control" "Not toggled,Toggled" bitfld.long 0x0C 28. " LUT60 ,LUT 60 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 27. " LUT59 ,LUT 59 standby control" "Not toggled,Toggled" bitfld.long 0x0C 26. " LUT58 ,LUT 58 standby control" "Not toggled,Toggled" bitfld.long 0x0C 25. " LUT57 ,LUT 57 standby control" "Not toggled,Toggled" bitfld.long 0x0C 24. " LUT56 ,LUT 56 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " LUT55 ,LUT 55 standby control" "Not toggled,Toggled" bitfld.long 0x0C 22. " LUT54 ,LUT 54 standby control" "Not toggled,Toggled" bitfld.long 0x0C 21. " LUT53 ,LUT 53 standby control" "Not toggled,Toggled" bitfld.long 0x0C 20. " LUT52 ,LUT 52 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " LUT51 ,LUT 51 standby control" "Not toggled,Toggled" bitfld.long 0x0C 18. " LUT50 ,LUT 50 standby control" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT49 ,LUT 49 standby control" "Not toggled,Toggled" bitfld.long 0x0C 16. " LUT48 ,LUT 48 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 15. " LUT47 ,LUT 47 standby control" "Not toggled,Toggled" bitfld.long 0x0C 14. " LUT46 ,LUT 46 standby control" "Not toggled,Toggled" bitfld.long 0x0C 13. " LUT45 ,LUT 45 standby control" "Not toggled,Toggled" bitfld.long 0x0C 12. " LUT44 ,LUT 44 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " LUT43 ,LUT 43 standby control" "Not toggled,Toggled" bitfld.long 0x0C 10. " LUT42 ,LUT 42 standby control" "Not toggled,Toggled" bitfld.long 0x0C 9. " LUT41 ,LUT 41 standby control" "Not toggled,Toggled" bitfld.long 0x0C 8. " LUT40 ,LUT 40 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LUT39 ,LUT 39 standby control" "Not toggled,Toggled" bitfld.long 0x0C 6. " LUT38 ,LUT 38 standby control" "Not toggled,Toggled" bitfld.long 0x0C 5. " LUT37 ,LUT 37 standby control" "Not toggled,Toggled" bitfld.long 0x0C 4. " LUT36 ,LUT 36 standby control" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " LUT35 ,LUT 35 standby control" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUT34 ,LUT 34 standby control" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUT33 ,LUT 33 standby control" "Not toggled,Toggled" bitfld.long 0x0C 0. " LUT32 ,LUT 32 standby control" "Not toggled,Toggled" textline " " if (((per.l(ad:0x306F0000+0x200))&0x44)==0x44) group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove" textline " " bitfld.long 0x00 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not drove,Drove" bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not used,Used" bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" textline " " bitfld.long 0x00 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not applied,Applied" bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" bitfld.long 0x04 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Set" textline " " bitfld.long 0x04 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Set" bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Set" bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" textline " " bitfld.long 0x04 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Set" bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Set" bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" bitfld.long 0x08 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Clear" textline " " bitfld.long 0x08 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Clear" bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Clear" bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" textline " " bitfld.long 0x08 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Clear" bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" bitfld.long 0x0C 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not toggled,Toggled" bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not toggled,Toggled" bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not toggled,Toggled" bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" elif (((per.l(ad:0x306F0000+0x200))&0x44)==0x04) group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" textline " " bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not used,Used" bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" textline " " bitfld.long 0x00 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not applied,Applied" bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" textline " " bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Set" bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" textline " " bitfld.long 0x04 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Set" bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Set" bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" textline " " bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Clear" bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" textline " " bitfld.long 0x08 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Clear" bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" textline " " bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not toggled,Toggled" bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not toggled,Toggled" bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" else group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove" textline " " bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" textline " " bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" textline " " bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" textline " " bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Set" bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" textline " " bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" textline " " bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new luts to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" textline " " bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" textline " " bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (In bits)" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" endif group.long 0x220++0x0F line.long 0x00 "TCE_SDCFG,EPDC Timing Control Engine Source-Driver Config Register" bitfld.long 0x00 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "Not held,Held" bitfld.long 0x00 20. " SDSHR ,Value for source-driver shift direction output port" "Low,High" bitfld.long 0x00 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." textline " " bitfld.long 0x00 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not reversed,Reversed" hexmask.long.word 0x00 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (Outputs) per source-driver IC" line.long 0x04 "TCE_SDCFG_SET,EPDC Timing Control Engine Source-Driver Config Set Register" bitfld.long 0x04 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "No effect,Set" bitfld.long 0x04 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Set" bitfld.long 0x04 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x04 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." textline " " bitfld.long 0x04 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Set" hexmask.long.word 0x04 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (Outputs) per source-driver IC" line.long 0x08 "TCE_SDCFG_CLR,EPDC Timing Control Engine Source-Driver Config Clear Register" bitfld.long 0x08 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "No effect,Clear" bitfld.long 0x08 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Clear" bitfld.long 0x08 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x08 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." textline " " bitfld.long 0x08 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Clear" hexmask.long.word 0x08 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (Outputs) per source-driver IC" line.long 0x0C "TCE_SDCFG_TOG,EPDC Timing Control Engine Source-Driver Config Toggle Register" bitfld.long 0x0C 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "Not toggled,Toggled" bitfld.long 0x0C 20. " SDSHR ,Value for source-driver shift direction output port" "Not toggled,Toggled" bitfld.long 0x0C 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x0C 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." textline " " bitfld.long 0x0C 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not toggled,Toggled" hexmask.long.word 0x0C 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (Outputs) per source-driver IC" group.long 0x240++0x0F line.long 0x00 "TCE_GDCFG,EPDC Timing Control Engine Gate-Driver Config Register" hexmask.long.word 0x00 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x00 4. " GDRL ,Value for gate-driver right/left shift output port" "Low,High" bitfld.long 0x00 1. " GDOE_MODE ,Method for driving GDOE signal" "All times,Delayed" bitfld.long 0x00 0. " GDSP_MODE ,Method for driving GDSP pulse" "Fixed,FRAME_SYNC" line.long 0x04 "TCE_GDCFG_SET,EPDC Timing Control Engine Gate-Driver Config Set Register" hexmask.long.word 0x04 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x04 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Set" bitfld.long 0x04 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Set" bitfld.long 0x04 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Set" line.long 0x08 "TCE_GDCFG_CLR,EPDC Timing Control Engine Gate-Driver Config Clear Register" hexmask.long.word 0x08 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x08 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Clear" bitfld.long 0x08 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Clear" bitfld.long 0x08 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Clear" line.long 0x0C "TCE_GDCFG_TOG,EPDC Timing Control Engine Gate-Driver Config Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x0C 4. " GDRL ,Value for gate-driver right/left shift output port" "Not toggled,Toggled" bitfld.long 0x0C 1. " GDOE_MODE ,Method for driving GDOE signal" "Not toggled,Toggled" bitfld.long 0x0C 0. " GDSP_MODE ,Method for driving GDSP pulse" "Not toggled,Toggled" group.long 0x260++0x0F line.long 0x00 "TCE_HSCAN1,EPDC Timing Control Engine Horizontal Timing Register 1" hexmask.long.word 0x00 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x00 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x04 "TCE_HSCAN1_SET,EPDC Timing Control Engine Horizontal Timing Set Register 1" hexmask.long.word 0x04 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x04 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x08 "TCE_HSCAN1_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 1" hexmask.long.word 0x08 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x08 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x0C "TCE_HSCAN1_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 1" hexmask.long.word 0x0C 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x0C 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" group.long 0x280++0x0F line.long 0x00 "TCE_HSCAN2,EPDC Timing Control Engine Horizontal Timing Register 2" hexmask.long.word 0x00 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x00 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x04 "TCE_HSCAN2_SET,EPDC Timing Control Engine Horizontal Timing Set Register 2" hexmask.long.word 0x04 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x04 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x08 "TCE_HSCAN2_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 2" hexmask.long.word 0x08 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x08 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x0C "TCE_HSCAN2_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 2" hexmask.long.word 0x0C 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x0C 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" group.long 0x2A0++0x0F line.long 0x00 "TCE_VSCAN,EPDC Timing Control Engine Vertical Timing Register" hexmask.long.byte 0x00 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x00 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" hexmask.long.byte 0x00 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x04 "TCE_VSCAN_SET,EPDC Timing Control Engine Vertical Timing Set Register" hexmask.long.byte 0x04 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x04 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" hexmask.long.byte 0x04 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x08 "TCE_VSCAN_CLR,EPDC Timing Control Engine Vertical Timing Clear Register" hexmask.long.byte 0x08 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x08 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" hexmask.long.byte 0x08 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x0C "TCE_VSCAN_TOG,EPDC Timing Control Engine Vertical Timing Toggle Register" hexmask.long.byte 0x0C 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x0C 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" hexmask.long.byte 0x0C 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" group.long 0x2C0++0x0F line.long 0x00 "TCE_OE,EPDC Timing Control Engine OE Timing Control Register" hexmask.long.byte 0x00 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x00 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" hexmask.long.byte 0x00 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x00 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x04 "TCE_OE_SET,EPDC Timing Control Engine OE Timing Control Set Register" hexmask.long.byte 0x04 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x04 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" hexmask.long.byte 0x04 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x04 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x08 "TCE_OE_CLR,EPDC Timing Control Engine OE Timing Control Clear Register" hexmask.long.byte 0x08 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x08 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" hexmask.long.byte 0x08 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x08 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x0C "TCE_OE_TOG,EPDC Timing Control Engine OE Timing Control Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x0C 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" hexmask.long.byte 0x0C 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x0C 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" group.long 0x2E0++0x0F line.long 0x00 "TCE_POLARITY,EPDC Timing Control Engine Driver Polarity Register" bitfld.long 0x00 4. " GDSP_POL ,GDSP output" "Active low,Active high" bitfld.long 0x00 3. " GDOE_POL ,GDOE output" "Active low,Active high" bitfld.long 0x00 2. " SDOE_POL ,SDOE" "Active low,Active high" textline " " bitfld.long 0x00 1. " SDLE_POL ,SDLE output" "Active low,Active high" bitfld.long 0x00 0. " SDCE_POL ,All 10 SDCE outputs" "Active low,Active high" line.long 0x04 "TCE_POLARITY_SET,EPDC Timing Control Engine Driver Polarity Register" bitfld.long 0x04 4. " GDSP_POL ,GDSP output" "No effect,Set" bitfld.long 0x04 3. " GDOE_POL ,GDOE output" "No effect,Set" bitfld.long 0x04 2. " SDOE_POL ,SDOE" "No effect,Set" textline " " bitfld.long 0x04 1. " SDLE_POL ,SDLE output" "No effect,Set" bitfld.long 0x04 0. " SDCE_POL ,All 10 SDCE outputs" "No effect,Set" line.long 0x08 "TCE_POLARITY_CLR,EPDC Timing Control Engine Driver Polarity Register" bitfld.long 0x08 4. " GDSP_POL ,GDSP output" "No effect,Clear" bitfld.long 0x08 3. " GDOE_POL ,GDOE output" "No effect,Clear" bitfld.long 0x08 2. " SDOE_POL ,SDOE" "No effect,Clear" textline " " bitfld.long 0x08 1. " SDLE_POL ,SDLE output" "No effect,Clear" bitfld.long 0x08 0. " SDCE_POL ,All 10 SDCE outputs" "No effect,Clear" line.long 0x0C "TCE_POLARITY_TOG,EPDC Timing Control Engine Driver Polarity Register" bitfld.long 0x0C 4. " GDSP_POL ,GDSP output" "Not toggled,Toggled" bitfld.long 0x0C 3. " GDOE_POL ,GDOE output" "Not toggled,Toggled" bitfld.long 0x0C 2. " SDOE_POL ,SDOE" "Not toggled,Toggled" textline " " bitfld.long 0x0C 1. " SDLE_POL ,SDLE output" "Not toggled,Toggled" bitfld.long 0x0C 0. " SDCE_POL ,All 10 SDCE outputs" "Not toggled,Toggled" group.long 0x300++0x2F line.long 0x00 "TCE_TIMING1,EPDC Timing Control Engine Timing Register 1" bitfld.long 0x00 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x00 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not inverted,Inverted" bitfld.long 0x00 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x04 "TCE_TIMING1_SET,EPDC Timing Control Engine Timing Set Register 1" bitfld.long 0x04 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x04 3. " SDCLK_INVERT ,Invert phase of SDCLK" "No effect,Set" bitfld.long 0x04 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x08 "TCE_TIMING1_CLR,EPDC Timing Control Engine Timing Clear Register 1" bitfld.long 0x08 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x08 3. " SDCLK_INVERT ,Invert phase of SDCLK" "No effect,Clear" bitfld.long 0x08 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x0C "TCE_TIMING1_TOG,EPDC Timing Control Engine Timing Toggle Register 1" bitfld.long 0x0C 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x0C 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x10 "TCE_TIMING2,EPDC Timing Control Engine Timing Register 2" hexmask.long.word 0x10 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x10 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N pixclks" line.long 0x14 "TCE_TIMING2_SET,EPDC Timing Control Engine Timing Set Register 2" hexmask.long.word 0x14 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x14 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N pixclks" line.long 0x18 "TCE_TIMING2_CLR,EPDC Timing Control Engine Timing Clear Register 2" hexmask.long.word 0x18 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x18 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N pixclks" line.long 0x1C "TCE_TIMING2_TOG,EPDC Timing Control Engine Timing Register 2" hexmask.long.word 0x1C 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x1C 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N pixclks" line.long 0x20 "TCE_TIMING3,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x20 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles" hexmask.long.word 0x20 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles" line.long 0x24 "TCE_TIMING3_SET,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x24 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles" hexmask.long.word 0x24 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles" line.long 0x28 "TCE_TIMING3_CLR,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x28 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles" hexmask.long.word 0x28 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles" line.long 0x2C "TCE_TIMING3_TOG,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x2C 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles" hexmask.long.word 0x2C 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles" group.long 0x380++0x1F line.long 0x00 "PIGEON_CTRL0,EPDC Pigeon Mode Control Register 0" hexmask.long.word 0x00 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x00 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x04 "PIGEON_CTRL0_SET,EPDC Pigeon Mode Control Set Register 0" hexmask.long.word 0x04 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x04 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x08 "PIGEON_CTRL0_CLR,EPDC Pigeon Mode Control Clear Register 0" hexmask.long.word 0x08 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x08 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x0C "PIGEON_CTRL0_TOG,EPDC Pigeon Mode Control Toggle Register 0" hexmask.long.word 0x0C 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x0C 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x10 "PIGEON_CTRL1,EPDC Pigeon Mode Control Register 1" hexmask.long.word 0x10 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x10 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x14 "PIGEON_CTRL1_SET,EPDC Pigeon Mode Control Set Register 1" hexmask.long.word 0x14 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x14 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x18 "PIGEON_CTRL1_CLR,EPDC Pigeon Mode Control Clear Register 1" hexmask.long.word 0x18 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x18 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x1C "PIGEON_CTRL1_TOG,EPDC Pigeon Mode Control Register 1" hexmask.long.word 0x1C 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x1C 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" textline " " group.long 0x3C0++0x4F line.long 0x00 "IRQ_MASK1,EPDC IRQ Mask Register For LUT 0-31" bitfld.long 0x00 31. " LUT31_CMPLT_IRQ_EN ,LUT31 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " LUT30_CMPLT_IRQ_EN ,LUT30 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " LUT29_CMPLT_IRQ_EN ,LUT29 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " LUT28_CMPLT_IRQ_EN ,LUT28 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LUT27_CMPLT_IRQ_EN ,LUT27 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " LUT26_CMPLT_IRQ_EN ,LUT26 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " LUT25_CMPLT_IRQ_EN ,LUT25 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " LUT24_CMPLT_IRQ_EN ,LUT24 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LUT23_CMPLT_IRQ_EN ,LUT23 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " LUT22_CMPLT_IRQ_EN ,LUT22 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " LUT21_CMPLT_IRQ_EN ,LUT21 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " LUT20_CMPLT_IRQ_EN ,LUT20 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LUT19_CMPLT_IRQ_EN ,LUT19 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " LUT18_CMPLT_IRQ_EN ,LUT18 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " LUT17_CMPLT_IRQ_EN ,LUT17 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " LUT16_CMPLT_IRQ_EN ,LUT16 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LUT15_CMPLT_IRQ_EN ,LUT15 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " LUT14_CMPLT_IRQ_EN ,LUT14 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " LUT13_CMPLT_IRQ_EN ,LUT13 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " LUT12_CMPLT_IRQ_EN ,LUT12 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LUT11_CMPLT_IRQ_EN ,LUT11 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " LUT10_CMPLT_IRQ_EN ,LUT10 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " LUT9_CMPLT_IRQ_EN ,LUT9 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " LUT8_CMPLT_IRQ_EN ,LUT8 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LUT7_CMPLT_IRQ_EN ,LUT7 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " LUT6_CMPLT_IRQ_EN ,LUT6 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LUT5_CMPLT_IRQ_EN ,LUT5 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " LUT4_CMPLT_IRQ_EN ,LUT4 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LUT3_CMPLT_IRQ_EN ,LUT3 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LUT2_CMPLT_IRQ_EN ,LUT2 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " LUT1_CMPLT_IRQ_EN ,LUT1 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " LUT0_CMPLT_IRQ_EN ,LUT0 complete interrupt enable" "Disabled,Enabled" line.long 0x04 "IRQ_MASK1_SET,EPDC IRQ Mask Set Register For LUT 0-31" bitfld.long 0x04 31. " LUT31_CMPLT_IRQ_SET ,LUT31 complete interrupt set" "No effect,Set" bitfld.long 0x04 30. " LUT30_CMPLT_IRQ_SET ,LUT30 complete interrupt set" "No effect,Set" bitfld.long 0x04 29. " LUT29_CMPLT_IRQ_SET ,LUT29 complete interrupt set" "No effect,Set" bitfld.long 0x04 28. " LUT28_CMPLT_IRQ_SET ,LUT28 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 27. " LUT27_CMPLT_IRQ_SET ,LUT27 complete interrupt set" "No effect,Set" bitfld.long 0x04 26. " LUT26_CMPLT_IRQ_SET ,LUT26 complete interrupt set" "No effect,Set" bitfld.long 0x04 25. " LUT25_CMPLT_IRQ_SET ,LUT25 complete interrupt set" "No effect,Set" bitfld.long 0x04 24. " LUT24_CMPLT_IRQ_SET ,LUT24 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 23. " LUT23_CMPLT_IRQ_SET ,LUT23 complete interrupt set" "No effect,Set" bitfld.long 0x04 22. " LUT22_CMPLT_IRQ_SET ,LUT22 complete interrupt set" "No effect,Set" bitfld.long 0x04 21. " LUT21_CMPLT_IRQ_SET ,LUT21 complete interrupt set" "No effect,Set" bitfld.long 0x04 20. " LUT20_CMPLT_IRQ_SET ,LUT20 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 19. " LUT19_CMPLT_IRQ_SET ,LUT19 complete interrupt set" "No effect,Set" bitfld.long 0x04 18. " LUT18_CMPLT_IRQ_SET ,LUT18 complete interrupt set" "No effect,Set" bitfld.long 0x04 17. " LUT17_CMPLT_IRQ_SET ,LUT17 complete interrupt set" "No effect,Set" bitfld.long 0x04 16. " LUT16_CMPLT_IRQ_SET ,LUT16 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 15. " LUT15_CMPLT_IRQ_SET ,LUT15 complete interrupt set" "No effect,Set" bitfld.long 0x04 14. " LUT14_CMPLT_IRQ_SET ,LUT14 complete interrupt set" "No effect,Set" bitfld.long 0x04 13. " LUT13_CMPLT_IRQ_SET ,LUT13 complete interrupt set" "No effect,Set" bitfld.long 0x04 12. " LUT12_CMPLT_IRQ_SET ,LUT12 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 11. " LUT11_CMPLT_IRQ_SET ,LUT11 complete interrupt set" "No effect,Set" bitfld.long 0x04 10. " LUT10_CMPLT_IRQ_SET ,LUT10 complete interrupt set" "No effect,Set" bitfld.long 0x04 9. " LUT9_CMPLT_IRQ_SET ,LUT9 complete interrupt set" "No effect,Set" bitfld.long 0x04 8. " LUT8_CMPLT_IRQ_SET ,LUT8 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 7. " LUT7_CMPLT_IRQ_SET ,LUT7 complete interrupt set" "No effect,Set" bitfld.long 0x04 6. " LUT6_CMPLT_IRQ_SET ,LUT6 complete interrupt set" "No effect,Set" bitfld.long 0x04 5. " LUT5_CMPLT_IRQ_SET ,LUT5 complete interrupt set" "No effect,Set" bitfld.long 0x04 4. " LUT4_CMPLT_IRQ_SET ,LUT4 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x04 3. " LUT3_CMPLT_IRQ_SET ,LUT3 complete interrupt set" "No effect,Set" bitfld.long 0x04 2. " LUT2_CMPLT_IRQ_SET ,LUT2 complete interrupt set" "No effect,Set" bitfld.long 0x04 1. " LUT1_CMPLT_IRQ_SET ,LUT1 complete interrupt set" "No effect,Set" bitfld.long 0x04 0. " LUT0_CMPLT_IRQ_SET ,LUT0 complete interrupt set" "No effect,Set" line.long 0x08 "IRQ_MASK1_CLR,EPDC IRQ Mask Clear Register For LUT 0-31" bitfld.long 0x08 31. " LUT31_CMPLT_IRQ_CLR ,LUT31 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 30. " LUT30_CMPLT_IRQ_CLR ,LUT30 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 29. " LUT29_CMPLT_IRQ_CLR ,LUT29 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 28. " LUT28_CMPLT_IRQ_CLR ,LUT28 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 27. " LUT27_CMPLT_IRQ_CLR ,LUT27 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 26. " LUT26_CMPLT_IRQ_CLR ,LUT26 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 25. " LUT25_CMPLT_IRQ_CLR ,LUT25 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 24. " LUT24_CMPLT_IRQ_CLR ,LUT24 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 23. " LUT23_CMPLT_IRQ_CLR ,LUT23 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 22. " LUT22_CMPLT_IRQ_CLR ,LUT22 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 21. " LUT21_CMPLT_IRQ_CLR ,LUT21 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 20. " LUT20_CMPLT_IRQ_CLR ,LUT20 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 19. " LUT19_CMPLT_IRQ_CLR ,LUT19 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 18. " LUT18_CMPLT_IRQ_CLR ,LUT18 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 17. " LUT17_CMPLT_IRQ_CLR ,LUT17 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 16. " LUT16_CMPLT_IRQ_CLR ,LUT16 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 15. " LUT15_CMPLT_IRQ_CLR ,LUT15 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 14. " LUT14_CMPLT_IRQ_CLR ,LUT14 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 13. " LUT13_CMPLT_IRQ_CLR ,LUT13 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 12. " LUT12_CMPLT_IRQ_CLR ,LUT12 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 11. " LUT11_CMPLT_IRQ_CLR ,LUT11 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 10. " LUT10_CMPLT_IRQ_CLR ,LUT10 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 9. " LUT9_CMPLT_IRQ_CLR ,LUT9 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 8. " LUT8_CMPLT_IRQ_CLR ,LUT8 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 7. " LUT7_CMPLT_IRQ_CLR ,LUT7 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 6. " LUT6_CMPLT_IRQ_CLR ,LUT6 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 5. " LUT5_CMPLT_IRQ_CLR ,LUT5 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 4. " LUT4_CMPLT_IRQ_CLR ,LUT4 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x08 3. " LUT3_CMPLT_IRQ_CLR ,LUT3 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 2. " LUT2_CMPLT_IRQ_CLR ,LUT2 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 1. " LUT1_CMPLT_IRQ_CLR ,LUT1 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 0. " LUT0_CMPLT_IRQ_CLR ,LUT0 complete interrupt clear" "No effect,Clear" line.long 0x0C "IRQ_MASK1_TOG,EPDC IRQ Mask Toggle Register For LUT 0-31" bitfld.long 0x0C 31. " LUT31_CMPLT_IRQ_TOG ,LUT31 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 30. " LUT30_CMPLT_IRQ_TOG ,LUT30 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 29. " LUT29_CMPLT_IRQ_TOG ,LUT29 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 28. " LUT28_CMPLT_IRQ_TOG ,LUT28 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 27. " LUT27_CMPLT_IRQ_TOG ,LUT27 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 26. " LUT26_CMPLT_IRQ_TOG ,LUT26 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 25. " LUT25_CMPLT_IRQ_TOG ,LUT25 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 24. " LUT24_CMPLT_IRQ_TOG ,LUT24 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " LUT23_CMPLT_IRQ_TOG ,LUT23 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " LUT22_CMPLT_IRQ_TOG ,LUT22 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 21. " LUT21_CMPLT_IRQ_TOG ,LUT21 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " LUT20_CMPLT_IRQ_TOG ,LUT20 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " LUT18_CMPLT_IRQ_TOG ,LUT19 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " LUT18_CMPLT_IRQ_TOG ,LUT18 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT17_CMPLT_IRQ_TOG ,LUT17 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " LUT16_CMPLT_IRQ_TOG ,LUT16 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 15. " LUT15_CMPLT_IRQ_TOG ,LUT15 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 14. " LUT14_CMPLT_IRQ_TOG ,LUT14 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 13. " LUT13_CMPLT_IRQ_TOG ,LUT13 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 12. " LUT12_CMPLT_IRQ_TOG ,LUT12 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " LUT11_CMPLT_IRQ_TOG ,LUT11 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 10. " LUT10_CMPLT_IRQ_TOG ,LUT10 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 9. " LUT9_CMPLT_IRQ_TOG ,LUT9 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 8. " LUT8_CMPLT_IRQ_TOG ,LUT8 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LUT7_CMPLT_IRQ_TOG ,LUT7 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 6. " LUT6_CMPLT_IRQ_TOG ,LUT6 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 5. " LUT5_CMPLT_IRQ_TOG ,LUT5 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 4. " LUT4_CMPLT_IRQ_TOG ,LUT4 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " LUT3_CMPLT_IRQ_TOG ,LUT3 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUT2_CMPLT_IRQ_TOG ,LUT2 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUT1_CMPLT_IRQ_TOG ,LUT1 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " LUT0_CMPLT_IRQ_TOG ,LUT0 complete interrupt toggle" "Not toggled,Toggled" line.long 0x10 "IRQ_MASK2,EPDC IRQ Mask Register For LUT 32-63" bitfld.long 0x10 31. " LUT63_CMPLT_IRQ_EN ,LUT63 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 30. " LUT62_CMPLT_IRQ_EN ,LUT62 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 29. " LUT61_CMPLT_IRQ_EN ,LUT61 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " LUT60_CMPLT_IRQ_EN ,LUT60 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " LUT59_CMPLT_IRQ_EN ,LUT59 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " LUT58_CMPLT_IRQ_EN ,LUT58 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 25. " LUT57_CMPLT_IRQ_EN ,LUT57 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " LUT56_CMPLT_IRQ_EN ,LUT56 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " LUT55_CMPLT_IRQ_EN ,LUT55 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " LUT54_CMPLT_IRQ_EN ,LUT54 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 21. " LUT53_CMPLT_IRQ_EN ,LUT53 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " LUT52_CMPLT_IRQ_EN ,LUT52 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " LUT51_CMPLT_IRQ_EN ,LUT51 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " LUT50_CMPLT_IRQ_EN ,LUT50 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 17. " LUT49_CMPLT_IRQ_EN ,LUT49 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 16. " LUT48_CMPLT_IRQ_EN ,LUT48 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " LUT47_CMPLT_IRQ_EN ,LUT47 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 14. " LUT46_CMPLT_IRQ_EN ,LUT46 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 13. " LUT45_CMPLT_IRQ_EN ,LUT45 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 12. " LUT44_CMPLT_IRQ_EN ,LUT44 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " LUT43_CMPLT_IRQ_EN ,LUT43 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 10. " LUT42_CMPLT_IRQ_EN ,LUT42 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 9. " LUT41_CMPLT_IRQ_EN ,LUT41 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 8. " LUT40_CMPLT_IRQ_EN ,LUT40 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " LUT39_CMPLT_IRQ_EN ,LUT39 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " LUT38_CMPLT_IRQ_EN ,LUT38 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 5. " LUT37_CMPLT_IRQ_EN ,LUT37 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " LUT36_CMPLT_IRQ_EN ,LUT36 complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " LUT35_CMPLT_IRQ_EN ,LUT35 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 2. " LUT34_CMPLT_IRQ_EN ,LUT34 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " LUT33_CMPLT_IRQ_EN ,LUT33 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " LUT32_CMPLT_IRQ_EN ,LUT32 complete interrupt enable" "Disabled,Enabled" line.long 0x14 "IRQ_MASK2_SET,EPDC IRQ Mask Set Register For LUT 32-63" bitfld.long 0x14 31. " LUT63_CMPLT_IRQ_SET ,LUT63 complete interrupt set" "No effect,Set" bitfld.long 0x14 30. " LUT62_CMPLT_IRQ_SET ,LUT62 complete interrupt set" "No effect,Set" bitfld.long 0x14 29. " LUT61_CMPLT_IRQ_SET ,LUT61 complete interrupt set" "No effect,Set" bitfld.long 0x14 28. " LUT60_CMPLT_IRQ_SET ,LUT60 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 27. " LUT59_CMPLT_IRQ_SET ,LUT59 complete interrupt set" "No effect,Set" bitfld.long 0x14 26. " LUT58_CMPLT_IRQ_SET ,LUT58 complete interrupt set" "No effect,Set" bitfld.long 0x14 25. " LUT57_CMPLT_IRQ_SET ,LUT57 complete interrupt set" "No effect,Set" bitfld.long 0x14 24. " LUT56_CMPLT_IRQ_SET ,LUT56 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 23. " LUT55_CMPLT_IRQ_SET ,LUT55 complete interrupt set" "No effect,Set" bitfld.long 0x14 22. " LUT54_CMPLT_IRQ_SET ,LUT54 complete interrupt set" "No effect,Set" bitfld.long 0x14 21. " LUT53_CMPLT_IRQ_SET ,LUT53 complete interrupt set" "No effect,Set" bitfld.long 0x14 20. " LUT52_CMPLT_IRQ_SET ,LUT52 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 19. " LUT51_CMPLT_IRQ_SET ,LUT51 complete interrupt set" "No effect,Set" bitfld.long 0x14 18. " LUT50_CMPLT_IRQ_SET ,LUT50 complete interrupt set" "No effect,Set" bitfld.long 0x14 17. " LUT49_CMPLT_IRQ_SET ,LUT49 complete interrupt set" "No effect,Set" bitfld.long 0x14 16. " LUT48_CMPLT_IRQ_SET ,LUT48 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 15. " LUT47_CMPLT_IRQ_SET ,LUT47 complete interrupt set" "No effect,Set" bitfld.long 0x14 14. " LUT46_CMPLT_IRQ_SET ,LUT46 complete interrupt set" "No effect,Set" bitfld.long 0x14 13. " LUT45_CMPLT_IRQ_SET ,LUT45 complete interrupt set" "No effect,Set" bitfld.long 0x14 12. " LUT44_CMPLT_IRQ_SET ,LUT44 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 11. " LUT43_CMPLT_IRQ_SET ,LUT43 complete interrupt set" "No effect,Set" bitfld.long 0x14 10. " LUT42_CMPLT_IRQ_SET ,LUT42 complete interrupt set" "No effect,Set" bitfld.long 0x14 9. " LUT41_CMPLT_IRQ_SET ,LUT41 complete interrupt set" "No effect,Set" bitfld.long 0x14 8. " LUT40_CMPLT_IRQ_SET ,LUT40 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 7. " LUT39_CMPLT_IRQ_SET ,LUT39 complete interrupt set" "No effect,Set" bitfld.long 0x14 6. " LUT38_CMPLT_IRQ_SET ,LUT38 complete interrupt set" "No effect,Set" bitfld.long 0x14 5. " LUT37_CMPLT_IRQ_SET ,LUT37 complete interrupt set" "No effect,Set" bitfld.long 0x14 4. " LUT36_CMPLT_IRQ_SET ,LUT36 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x14 3. " LUT35_CMPLT_IRQ_SET ,LUT35 complete interrupt set" "No effect,Set" bitfld.long 0x14 2. " LUT34_CMPLT_IRQ_SET ,LUT34 complete interrupt set" "No effect,Set" bitfld.long 0x14 1. " LUT33_CMPLT_IRQ_SET ,LUT33 complete interrupt set" "No effect,Set" bitfld.long 0x14 0. " LUT32_CMPLT_IRQ_SET ,LUT32 complete interrupt set" "No effect,Set" line.long 0x18 "IRQ_MASK2_CLR,EPDC IRQ Mask Clear Register For LUT 32-63" bitfld.long 0x18 31. " LUT63_CMPLT_IRQ_CLR ,LUT63 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 30. " LUT62_CMPLT_IRQ_CLR ,LUT62 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 29. " LUT61_CMPLT_IRQ_CLR ,LUT61 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 28. " LUT60_CMPLT_IRQ_CLR ,LUT60 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 27. " LUT59_CMPLT_IRQ_CLR ,LUT59 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 26. " LUT58_CMPLT_IRQ_CLR ,LUT58 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 25. " LUT57_CMPLT_IRQ_CLR ,LUT57 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 24. " LUT56_CMPLT_IRQ_CLR ,LUT56 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 23. " LUT55_CMPLT_IRQ_CLR ,LUT55 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 22. " LUT54_CMPLT_IRQ_CLR ,LUT54 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 21. " LUT53_CMPLT_IRQ_CLR ,LUT53 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 20. " LUT52_CMPLT_IRQ_CLR ,LUT52 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 19. " LUT51_CMPLT_IRQ_CLR ,LUT51 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 18. " LUT50_CMPLT_IRQ_CLR ,LUT50 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 17. " LUT49_CMPLT_IRQ_CLR ,LUT49 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 16. " LUT48_CMPLT_IRQ_CLR ,LUT48 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 15. " LUT47_CMPLT_IRQ_CLR ,LUT47 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 14. " LUT46_CMPLT_IRQ_CLR ,LUT46 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 13. " LUT45_CMPLT_IRQ_CLR ,LUT45 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 12. " LUT44_CMPLT_IRQ_CLR ,LUT44 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 11. " LUT43_CMPLT_IRQ_CLR ,LUT43 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 10. " LUT42_CMPLT_IRQ_CLR ,LUT42 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 9. " LUT41_CMPLT_IRQ_CLR ,LUT41 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 8. " LUT40_CMPLT_IRQ_CLR ,LUT40 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 7. " LUT39_CMPLT_IRQ_CLR ,LUT39 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 6. " LUT38_CMPLT_IRQ_CLR ,LUT38 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 5. " LUT37_CMPLT_IRQ_CLR ,LUT37 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 4. " LUT36_CMPLT_IRQ_CLR ,LUT36 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x18 3. " LUT35_CMPLT_IRQ_CLR ,LUT35 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 2. " LUT34_CMPLT_IRQ_CLR ,LUT34 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 1. " LUT33_CMPLT_IRQ_CLR ,LUT33 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 0. " LUT32_CMPLT_IRQ_CLR ,LUT32 complete interrupt clear" "No effect,Clear" line.long 0x1C "IRQ_MASK2_TOG,EPDC IRQ Mask Toggle Register For LUT 32-63" bitfld.long 0x1C 31. " LUT63_CMPLT_IRQ_TOG ,LUT63 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 30. " LUT62_CMPLT_IRQ_TOG ,LUT62 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 29. " LUT61_CMPLT_IRQ_TOG ,LUT61 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 28. " LUT60_CMPLT_IRQ_TOG ,LUT60 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 27. " LUT59_CMPLT_IRQ_TOG ,LUT59 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 26. " LUT58_CMPLT_IRQ_TOG ,LUT58 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 25. " LUT57_CMPLT_IRQ_TOG ,LUT57 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 24. " LUT56_CMPLT_IRQ_TOG ,LUT56 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 23. " LUT55_CMPLT_IRQ_TOG ,LUT55 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 22. " LUT54_CMPLT_IRQ_TOG ,LUT54 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 21. " LUT53_CMPLT_IRQ_TOG ,LUT53 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 20. " LUT52_CMPLT_IRQ_TOG ,LUT52 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 19. " LUT51_CMPLT_IRQ_TOG ,LUT51 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 18. " LUT50_CMPLT_IRQ_TOG ,LUT50 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 17. " LUT49_CMPLT_IRQ_TOG ,LUT49 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 16. " LUT48_CMPLT_IRQ_TOG ,LUT48 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 15. " LUT47_CMPLT_IRQ_TOG ,LUT47 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 14. " LUT46_CMPLT_IRQ_TOG ,LUT46 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 13. " LUT45_CMPLT_IRQ_TOG ,LUT45 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 12. " LUT44_CMPLT_IRQ_TOG ,LUT44 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 11. " LUT43_CMPLT_IRQ_TOG ,LUT43 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 10. " LUT42_CMPLT_IRQ_TOG ,LUT42 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 9. " LUT41_CMPLT_IRQ_TOG ,LUT41 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 8. " LUT40_CMPLT_IRQ_TOG ,LUT40 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 7. " LUT39_CMPLT_IRQ_TOG ,LUT39 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 6. " LUT38_CMPLT_IRQ_TOG ,LUT38 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 5. " LUT37_CMPLT_IRQ_TOG ,LUT37 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 4. " LUT36_CMPLT_IRQ_TOG ,LUT36 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x1C 3. " LUT35_CMPLT_IRQ_TOG ,LUT35 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 2. " LUT34_CMPLT_IRQ_TOG ,LUT34 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 1. " LUT33_CMPLT_IRQ_TOG ,LUT33 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 0. " LUT32_CMPLT_IRQ_TOG ,LUT32 complete interrupt toggle" "Not toggled,Toggled" line.long 0x20 "IRQ1,EPDC Interrupt Register For LUT 0-31" bitfld.long 0x20 31. " LUT31_CMPLT_IRQ ,LUT31 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 30. " LUT30_CMPLT_IRQ ,LUT30 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 29. " LUT29_CMPLT_IRQ ,LUT29 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 28. " LUT28_CMPLT_IRQ ,LUT28 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 27. " LUT27_CMPLT_IRQ ,LUT27 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 26. " LUT26_CMPLT_IRQ ,LUT26 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 25. " LUT25_CMPLT_IRQ ,LUT25 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 24. " LUT24_CMPLT_IRQ ,LUT24 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 23. " LUT23_CMPLT_IRQ ,LUT23 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 22. " LUT22_CMPLT_IRQ ,LUT22 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 21. " LUT21_CMPLT_IRQ ,LUT21 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 20. " LUT20_CMPLT_IRQ ,LUT20 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 19. " LUT19_CMPLT_IRQ ,LUT19 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 18. " LUT18_CMPLT_IRQ ,LUT18 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 17. " LUT17_CMPLT_IRQ ,LUT17 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 16. " LUT16_CMPLT_IRQ ,LUT16 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 15. " LUT15_CMPLT_IRQ ,LUT15 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 14. " LUT14_CMPLT_IRQ ,LUT14 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 13. " LUT13_CMPLT_IRQ ,LUT13 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 12. " LUT12_CMPLT_IRQ ,LUT12 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 11. " LUT11_CMPLT_IRQ ,LUT11 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 10. " LUT10_CMPLT_IRQ ,LUT10 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 9. " LUT9_CMPLT_IRQ ,LUT9 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 8. " LUT8_CMPLT_IRQ ,LUT8 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 7. " LUT7_CMPLT_IRQ ,LUT7 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 6. " LUT6_CMPLT_IRQ ,LUT6 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 5. " LUT5_CMPLT_IRQ ,LUT5 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 4. " LUT4_CMPLT_IRQ ,LUT4 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x20 3. " LUT3_CMPLT_IRQ ,LUT3 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 2. " LUT2_CMPLT_IRQ ,LUT2 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 1. " LUT1_CMPLT_IRQ ,LUT1 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 0. " LUT0_CMPLT_IRQ ,LUT0 complete interrupt" "No interrupt,Interrupt" line.long 0x24 "IRQ1_SET,EPDC Interrupt Set Register For LUT 0-31" bitfld.long 0x24 31. " LUT31_CMPLT_IRQ_SET ,LUT31 complete interrupt set" "No effect,Set" bitfld.long 0x24 30. " LUT30_CMPLT_IRQ_SET ,LUT30 complete interrupt set" "No effect,Set" bitfld.long 0x24 29. " LUT29_CMPLT_IRQ_SET ,LUT29 complete interrupt set" "No effect,Set" bitfld.long 0x24 28. " LUT28_CMPLT_IRQ_SET ,LUT28 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 27. " LUT27_CMPLT_IRQ_SET ,LUT27 complete interrupt set" "No effect,Set" bitfld.long 0x24 26. " LUT26_CMPLT_IRQ_SET ,LUT26 complete interrupt set" "No effect,Set" bitfld.long 0x24 25. " LUT25_CMPLT_IRQ_SET ,LUT25 complete interrupt set" "No effect,Set" bitfld.long 0x24 24. " LUT24_CMPLT_IRQ_SET ,LUT24 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 23. " LUT23_CMPLT_IRQ_SET ,LUT23 complete interrupt set" "No effect,Set" bitfld.long 0x24 22. " LUT22_CMPLT_IRQ_SET ,LUT22 complete interrupt set" "No effect,Set" bitfld.long 0x24 21. " LUT21_CMPLT_IRQ_SET ,LUT21 complete interrupt set" "No effect,Set" bitfld.long 0x24 20. " LUT20_CMPLT_IRQ_SET ,LUT20 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 19. " LUT19_CMPLT_IRQ_SET ,LUT19 complete interrupt set" "No effect,Set" bitfld.long 0x24 18. " LUT18_CMPLT_IRQ_SET ,LUT18 complete interrupt set" "No effect,Set" bitfld.long 0x24 17. " LUT17_CMPLT_IRQ_SET ,LUT17 complete interrupt set" "No effect,Set" bitfld.long 0x24 16. " LUT16_CMPLT_IRQ_SET ,LUT16 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 15. " LUT15_CMPLT_IRQ_SET ,LUT15 complete interrupt set" "No effect,Set" bitfld.long 0x24 14. " LUT14_CMPLT_IRQ_SET ,LUT14 complete interrupt set" "No effect,Set" bitfld.long 0x24 13. " LUT13_CMPLT_IRQ_SET ,LUT13 complete interrupt set" "No effect,Set" bitfld.long 0x24 12. " LUT12_CMPLT_IRQ_SET ,LUT12 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 11. " LUT11_CMPLT_IRQ_SET ,LUT11 complete interrupt set" "No effect,Set" bitfld.long 0x24 10. " LUT10_CMPLT_IRQ_SET ,LUT10 complete interrupt set" "No effect,Set" bitfld.long 0x24 9. " LUT9_CMPLT_IRQ_SET ,LUT9 complete interrupt set" "No effect,Set" bitfld.long 0x24 8. " LUT8_CMPLT_IRQ_SET ,LUT8 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 7. " LUT7_CMPLT_IRQ_SET ,LUT7 complete interrupt set" "No effect,Set" bitfld.long 0x24 6. " LUT6_CMPLT_IRQ_SET ,LUT6 complete interrupt set" "No effect,Set" bitfld.long 0x24 5. " LUT5_CMPLT_IRQ_SET ,LUT5 complete interrupt set" "No effect,Set" bitfld.long 0x24 4. " LUT4_CMPLT_IRQ_SET ,LUT4 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x24 3. " LUT3_CMPLT_IRQ_SET ,LUT3 complete interrupt set" "No effect,Set" bitfld.long 0x24 2. " LUT2_CMPLT_IRQ_SET ,LUT2 complete interrupt set" "No effect,Set" bitfld.long 0x24 1. " LUT1_CMPLT_IRQ_SET ,LUT1 complete interrupt set" "No effect,Set" bitfld.long 0x24 0. " LUT0_CMPLT_IRQ_SET ,LUT0 complete interrupt set" "No effect,Set" line.long 0x28 "IRQ1_CLR,EPDC Interrupt Clear Register For LUT 0-31" bitfld.long 0x28 31. " LUT31_CMPLT_IRQ_CLR ,LUT31 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 30. " LUT30_CMPLT_IRQ_CLR ,LUT30 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 29. " LUT29_CMPLT_IRQ_CLR ,LUT29 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 28. " LUT28_CMPLT_IRQ_CLR ,LUT28 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 27. " LUT27_CMPLT_IRQ_CLR ,LUT27 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 26. " LUT26_CMPLT_IRQ_CLR ,LUT26 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 25. " LUT25_CMPLT_IRQ_CLR ,LUT25 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 24. " LUT24_CMPLT_IRQ_CLR ,LUT24 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 23. " LUT23_CMPLT_IRQ_CLR ,LUT23 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 22. " LUT22_CMPLT_IRQ_CLR ,LUT22 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 21. " LUT21_CMPLT_IRQ_CLR ,LUT21 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 20. " LUT20_CMPLT_IRQ_CLR ,LUT20 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 19. " LUT19_CMPLT_IRQ_CLR ,LUT19 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 18. " LUT18_CMPLT_IRQ_CLR ,LUT18 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 17. " LUT17_CMPLT_IRQ_CLR ,LUT17 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 16. " LUT16_CMPLT_IRQ_CLR ,LUT16 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 15. " LUT15_CMPLT_IRQ_CLR ,LUT15 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 14. " LUT14_CMPLT_IRQ_CLR ,LUT14 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 13. " LUT13_CMPLT_IRQ_CLR ,LUT13 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 12. " LUT12_CMPLT_IRQ_CLR ,LUT12 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 11. " LUT11_CMPLT_IRQ_CLR ,LUT11 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 10. " LUT10_CMPLT_IRQ_CLR ,LUT10 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 9. " LUT9_CMPLT_IRQ_CLR ,LUT9 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 8. " LUT8_CMPLT_IRQ_CLR ,LUT8 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 7. " LUT7_CMPLT_IRQ_CLR ,LUT7 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 6. " LUT6_CMPLT_IRQ_CLR ,LUT6 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 5. " LUT5_CMPLT_IRQ_CLR ,LUT5 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 4. " LUT4_CMPLT_IRQ_CLR ,LUT4 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x28 3. " LUT3_CMPLT_IRQ_CLR ,LUT3 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 2. " LUT2_CMPLT_IRQ_CLR ,LUT2 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 1. " LUT1_CMPLT_IRQ_CLR ,LUT1 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 0. " LUT0_CMPLT_IRQ_CLR ,LUT0 complete interrupt clear" "No effect,Clear" line.long 0x2C "IRQ1_TOG,EPDC Interrupt Toggle Register For LUT 0-31" bitfld.long 0x2C 31. " LUT31_CMPLT_IRQ_TOG ,LUT31 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 30. " LUT30_CMPLT_IRQ_TOG ,LUT30 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 29. " LUT29_CMPLT_IRQ_TOG ,LUT29 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 28. " LUT28_CMPLT_IRQ_TOG ,LUT28 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 27. " LUT27_CMPLT_IRQ_TOG ,LUT27 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 26. " LUT26_CMPLT_IRQ_TOG ,LUT26 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 25. " LUT25_CMPLT_IRQ_TOG ,LUT25 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 24. " LUT24_CMPLT_IRQ_TOG ,LUT24 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 23. " LUT23_CMPLT_IRQ_TOG ,LUT23 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 22. " LUT22_CMPLT_IRQ_TOG ,LUT22 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 21. " LUT21_CMPLT_IRQ_TOG ,LUT21 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 20. " LUT20_CMPLT_IRQ_TOG ,LUT20 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 19. " LUT19_CMPLT_IRQ_TOG ,LUT19 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 18. " LUT18_CMPLT_IRQ_TOG ,LUT18 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 17. " LUT17_CMPLT_IRQ_TOG ,LUT17 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 16. " LUT16_CMPLT_IRQ_TOG ,LUT16 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 15. " LUT15_CMPLT_IRQ_TOG ,LUT15 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 14. " LUT14_CMPLT_IRQ_TOG ,LUT14 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 13. " LUT13_CMPLT_IRQ_TOG ,LUT13 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 12. " LUT12_CMPLT_IRQ_TOG ,LUT12 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 11. " LUT11_CMPLT_IRQ_TOG ,LUT11 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 10. " LUT10_CMPLT_IRQ_TOG ,LUT10 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 9. " LUT9_CMPLT_IRQ_TOG ,LUT9 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 8. " LUT8_CMPLT_IRQ_TOG ,LUT8 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 7. " LUT7_CMPLT_IRQ_TOG ,LUT7 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 6. " LUT6_CMPLT_IRQ_TOG ,LUT6 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 5. " LUT5_CMPLT_IRQ_TOG ,LUT5 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 4. " LUT4_CMPLT_IRQ_TOG ,LUT4 complete interrupt toggle" "Not toggled,Toggled" textline " " bitfld.long 0x2C 3. " LUT3_CMPLT_IRQ_TOG ,LUT3 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 2. " LUT2_CMPLT_IRQ_TOG ,LUT2 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 1. " LUT1_CMPLT_IRQ_TOG ,LUT1 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 0. " LUT0_CMPLT_IRQ_TOG ,LUT0 complete interrupt toggle" "Not toggled,Toggled" line.long 0x30 "IRQ2,EPDC Interrupt Registerr For LUT 32-63" bitfld.long 0x30 31. " LUT63_CMPLT_IRQ ,LUT63 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 30. " LUT62_CMPLT_IRQ ,LUT62 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 29. " LUT61_CMPLT_IRQ ,LUT61 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 28. " LUT60_CMPLT_IRQ ,LUT60 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 27. " LUT59_CMPLT_IRQ ,LUT59 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 26. " LUT58_CMPLT_IRQ ,LUT58 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 25. " LUT57_CMPLT_IRQ ,LUT57 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 24. " LUT56_CMPLT_IRQ ,LUT56 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 23. " LUT55_CMPLT_IRQ ,LUT55 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 22. " LUT54_CMPLT_IRQ ,LUT54 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 21. " LUT53_CMPLT_IRQ ,LUT53 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 20. " LUT52_CMPLT_IRQ ,LUT52 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 19. " LUT51_CMPLT_IRQ ,LUT51 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 18. " LUT50_CMPLT_IRQ ,LUT50 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 17. " LUT49_CMPLT_IRQ ,LUT49 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 16. " LUT48_CMPLT_IRQ ,LUT48 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 15. " LUT47_CMPLT_IRQ ,LUT47 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 14. " LUT46_CMPLT_IRQ ,LUT46 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 13. " LUT45_CMPLT_IRQ ,LUT45 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 12. " LUT44_CMPLT_IRQ ,LUT44 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 11. " LUT43_CMPLT_IRQ ,LUT43 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 10. " LUT42_CMPLT_IRQ ,LUT42 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 9. " LUT41_CMPLT_IRQ ,LUT41 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 8. " LUT40_CMPLT_IRQ ,LUT40 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 7. " LUT39_CMPLT_IRQ ,LUT39 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 6. " LUT38_CMPLT_IRQ ,LUT38 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 5. " LUT37_CMPLT_IRQ ,LUT37 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 4. " LUT36_CMPLT_IRQ ,LUT36 complete interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x30 3. " LUT35_CMPLT_IRQ ,LUT35 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 2. " LUT34_CMPLT_IRQ ,LUT34 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 1. " LUT33_CMPLT_IRQ ,LUT33 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 0. " LUT32_CMPLT_IRQ ,LUT32 complete interrupt" "No interrupt,Interrupt" line.long 0x34 "IRQ2_SET,EPDC Interrupt Set Registerr For LUT 32-63" bitfld.long 0x34 31. " LUT63_CMPLT_IRQ_SET ,LUT63 complete interrupt set" "No effect,Set" bitfld.long 0x34 30. " LUT62_CMPLT_IRQ_SET ,LUT62 complete interrupt set" "No effect,Set" bitfld.long 0x34 29. " LUT61_CMPLT_IRQ_SET ,LUT61 complete interrupt set" "No effect,Set" bitfld.long 0x34 28. " LUT60_CMPLT_IRQ_SET ,LUT60 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 27. " LUT59_CMPLT_IRQ_SET ,LUT59 complete interrupt set" "No effect,Set" bitfld.long 0x34 26. " LUT58_CMPLT_IRQ_SET ,LUT58 complete interrupt set" "No effect,Set" bitfld.long 0x34 25. " LUT57_CMPLT_IRQ_SET ,LUT57 complete interrupt set" "No effect,Set" bitfld.long 0x34 24. " LUT56_CMPLT_IRQ_SET ,LUT56 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 23. " LUT55_CMPLT_IRQ_SET ,LUT55 complete interrupt set" "No effect,Set" bitfld.long 0x34 22. " LUT54_CMPLT_IRQ_SET ,LUT54 complete interrupt set" "No effect,Set" bitfld.long 0x34 21. " LUT53_CMPLT_IRQ_SET ,LUT53 complete interrupt set" "No effect,Set" bitfld.long 0x34 20. " LUT52_CMPLT_IRQ_SET ,LUT52 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 19. " LUT51_CMPLT_IRQ_SET ,LUT51 complete interrupt set" "No effect,Set" bitfld.long 0x34 18. " LUT50_CMPLT_IRQ_SET ,LUT50 complete interrupt set" "No effect,Set" bitfld.long 0x34 17. " LUT49_CMPLT_IRQ_SET ,LUT49 complete interrupt set" "No effect,Set" bitfld.long 0x34 16. " LUT48_CMPLT_IRQ_SET ,LUT48 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 15. " LUT47_CMPLT_IRQ_SET ,LUT47 complete interrupt set" "No effect,Set" bitfld.long 0x34 14. " LUT46_CMPLT_IRQ_SET ,LUT46 complete interrupt set" "No effect,Set" bitfld.long 0x34 13. " LUT45_CMPLT_IRQ_SET ,LUT45 complete interrupt set" "No effect,Set" bitfld.long 0x34 12. " LUT44_CMPLT_IRQ_SET ,LUT44 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 11. " LUT43_CMPLT_IRQ_SET ,LUT43 complete interrupt set" "No effect,Set" bitfld.long 0x34 10. " LUT42_CMPLT_IRQ_SET ,LUT42 complete interrupt set" "No effect,Set" bitfld.long 0x34 9. " LUT41_CMPLT_IRQ_SET ,LUT41 complete interrupt set" "No effect,Set" bitfld.long 0x34 8. " LUT40_CMPLT_IRQ_SET ,LUT40 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 7. " LUT39_CMPLT_IRQ_SET ,LUT39 complete interrupt set" "No effect,Set" bitfld.long 0x34 6. " LUT38_CMPLT_IRQ_SET ,LUT38 complete interrupt set" "No effect,Set" bitfld.long 0x34 5. " LUT37_CMPLT_IRQ_SET ,LUT37 complete interrupt set" "No effect,Set" bitfld.long 0x34 4. " LUT36_CMPLT_IRQ_SET ,LUT36 complete interrupt set" "No effect,Set" textline " " bitfld.long 0x34 3. " LUT35_CMPLT_IRQ_SET ,LUT35 complete interrupt set" "No effect,Set" bitfld.long 0x34 2. " LUT34_CMPLT_IRQ_SET ,LUT34 complete interrupt set" "No effect,Set" bitfld.long 0x34 1. " LUT33_CMPLT_IRQ_SET ,LUT33 complete interrupt set" "No effect,Set" bitfld.long 0x34 0. " LUT32_CMPLT_IRQ_SET ,LUT32 complete interrupt set" "No effect,Set" line.long 0x38 "IRQ2_CLR,EPDC Interrupt Clear Registerr For LUT 32-63" bitfld.long 0x38 31. " LUT63_CMPLT_IRQ_CLR ,LUT63 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 30. " LUT62_CMPLT_IRQ_CLR ,LUT62 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 29. " LUT61_CMPLT_IRQ_CLR ,LUT61 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 28. " LUT60_CMPLT_IRQ_CLR ,LUT60 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 27. " LUT59_CMPLT_IRQ_CLR ,LUT59 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 26. " LUT58_CMPLT_IRQ_CLR ,LUT58 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 25. " LUT57_CMPLT_IRQ_CLR ,LUT57 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 24. " LUT56_CMPLT_IRQ_CLR ,LUT56 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 23. " LUT55_CMPLT_IRQ_CLR ,LUT55 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 22. " LUT54_CMPLT_IRQ_CLR ,LUT54 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 21. " LUT53_CMPLT_IRQ_CLR ,LUT53 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 20. " LUT52_CMPLT_IRQ_CLR ,LUT52 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 19. " LUT51_CMPLT_IRQ_CLR ,LUT51 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 18. " LUT50_CMPLT_IRQ_CLR ,LUT50 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 17. " LUT49_CMPLT_IRQ_CLR ,LUT49 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 16. " LUT48_CMPLT_IRQ_CLR ,LUT48 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 15. " LUT47_CMPLT_IRQ_CLR ,LUT47 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 14. " LUT46_CMPLT_IRQ_CLR ,LUT46 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 13. " LUT45_CMPLT_IRQ_CLR ,LUT45 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 12. " LUT44_CMPLT_IRQ_CLR ,LUT44 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 11. " LUT43_CMPLT_IRQ_CLR ,LUT43 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 10. " LUT42_CMPLT_IRQ_CLR ,LUT42 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 9. " LUT41_CMPLT_IRQ_CLR ,LUT41 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 8. " LUT40_CMPLT_IRQ_CLR ,LUT40 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 7. " LUT39_CMPLT_IRQ_CLR ,LUT39 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 6. " LUT38_CMPLT_IRQ_CLR ,LUT38 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 5. " LUT37_CMPLT_IRQ_CLR ,LUT37 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 4. " LUT36_CMPLT_IRQ_CLR ,LUT36 complete interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 3. " LUT35_CMPLT_IRQ_CLR ,LUT35 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 2. " LUT34_CMPLT_IRQ_CLR ,LUT34 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 1. " LUT33_CMPLT_IRQ_CLR ,LUT33 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 0. " LUT32_CMPLT_IRQ_CLR ,LUT32 complete interrupt clear" "No effect,Clear" line.long 0x3C "IRQ2_TOG,EPDC Interrupt Toggle Registerr For LUT 32-63" bitfld.long 0x3C 31. " LUT63_CMPLT_IRQ_TOG ,LUT63 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 30. " LUT62_CMPLT_IRQ_TOG ,LUT62 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 29. " LUT61_CMPLT_IRQ_TOG ,LUT61 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 28. " LUT60_CMPLT_IRQ_TOG ,LUT60 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 27. " LUT59_CMPLT_IRQ_TOG ,LUT59 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 26. " LUT58_CMPLT_IRQ_TOG ,LUT58 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 25. " LUT57_CMPLT_IRQ_TOG ,LUT57 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 24. " LUT56_CMPLT_IRQ_TOG ,LUT56 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 23. " LUT55_CMPLT_IRQ_TOG ,LUT55 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 22. " LUT54_CMPLT_IRQ_TOG ,LUT54 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 21. " LUT53_CMPLT_IRQ_TOG ,LUT53 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 20. " LUT52_CMPLT_IRQ_TOG ,LUT52 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 19. " LUT51_CMPLT_IRQ_TOG ,LUT51 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 18. " LUT50_CMPLT_IRQ_TOG ,LUT50 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 17. " LUT49_CMPLT_IRQ_TOG ,LUT49 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 16. " LUT48_CMPLT_IRQ_TOG ,LUT48 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 15. " LUT47_CMPLT_IRQ_TOG ,LUT47 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 14. " LUT46_CMPLT_IRQ_TOG ,LUT46 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 13. " LUT45_CMPLT_IRQ_TOG ,LUT45 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 12. " LUT44_CMPLT_IRQ_TOG ,LUT44 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 11. " LUT43_CMPLT_IRQ_TOG ,LUT43 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 10. " LUT42_CMPLT_IRQ_TOG ,LUT42 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 9. " LUT41_CMPLT_IRQ_TOG ,LUT41 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 8. " LUT40_CMPLT_IRQ_TOG ,LUT40 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 7. " LUT39_CMPLT_IRQ_TOG ,LUT39 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 6. " LUT38_CMPLT_IRQ_TOG ,LUT38 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 5. " LUT37_CMPLT_IRQ_TOG ,LUT37 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 4. " LUT36_CMPLT_IRQ_TOG ,LUT36 complete interrupt toogle" "Not toggled,Toggled" textline " " bitfld.long 0x3C 3. " LUT35_CMPLT_IRQ_TOG ,LUT35 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 2. " LUT34_CMPLT_IRQ_TOG ,LUT34 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 1. " LUT33_CMPLT_IRQ_TOG ,LUT33 complete interrupt toogle" "Not toggled,Toggled" bitfld.long 0x3C 0. " LUT32_CMPLT_IRQ_TOG ,LUT32 complete interrupt toogle" "Not toggled,Toggled" textline " " line.long 0x40 "IRQ_MASK,EPDC IRQ Mask Register" bitfld.long 0x40 23. " PWR_IRQ_EN ,Enable power interrupt" "Disabled,Enabled" bitfld.long 0x40 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt" "Disabled,Enabled" bitfld.long 0x40 21. " TCE_IDLE_IRQ_EN ,Enable TCE idle interrupt detection" "Disabled,Enabled" bitfld.long 0x40 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt" "Disabled,Enabled" bitfld.long 0x40 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "Disabled,Enabled" bitfld.long 0x40 17. " COL_IRQ_EN ,Enable collision detection interrupts for all luts" "Disabled,Enabled" bitfld.long 0x40 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "Disabled,Enabled" line.long 0x44 "IRQ_MASK_SET,EPDC IRQ Mask Set Register" bitfld.long 0x44 23. " PWR_IRQ_EN ,Enable power interrupt" "No effect,Set" bitfld.long 0x44 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt" "No effect,Set" bitfld.long 0x44 21. " TCE_IDLE_IRQ_EN ,Enable TCE idle interrupt detection" "No effect,Set" bitfld.long 0x44 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "No effect,Set" textline " " bitfld.long 0x44 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt" "No effect,Set" bitfld.long 0x44 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "No effect,Set" bitfld.long 0x44 17. " COL_IRQ_EN ,Enable collision detection interrupts for all luts" "No effect,Set" bitfld.long 0x44 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "No effect,Set" line.long 0x48 "IRQ_MASK_CLR,EPDC IRQ Mask Clear Register" bitfld.long 0x48 23. " PWR_IRQ_EN ,Enable power interrupt" "No effect,Clear" bitfld.long 0x48 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt" "No effect,Clear" bitfld.long 0x48 21. " TCE_IDLE_IRQ_EN ,Enable TCE idle interrupt detection" "No effect,Clear" bitfld.long 0x48 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "No effect,Clear" textline " " bitfld.long 0x48 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt" "No effect,Clear" bitfld.long 0x48 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "No effect,Clear" bitfld.long 0x48 17. " COL_IRQ_EN ,Enable collision detection interrupts for all luts" "No effect,Clear" bitfld.long 0x48 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "No effect,Clear" line.long 0x4C "IRQ_MASK_TOG,EPDC IRQ Mask Toggle Register" bitfld.long 0x4C 23. " PWR_IRQ_EN ,Enable power interrupt" "Not toggled,Toggled" bitfld.long 0x4C 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt" "Not toggled,Toggled" bitfld.long 0x4C 21. " TCE_IDLE_IRQ_EN ,Enable TCE idle interrupt detection" "Not toggled,Toggled" bitfld.long 0x4C 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "Not toggled,Toggled" textline " " bitfld.long 0x4C 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt" "Not toggled,Toggled" bitfld.long 0x4C 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "Not toggled,Toggled" bitfld.long 0x4C 17. " COL_IRQ_EN ,Enable collision detection interrupts for all luts" "Not toggled,Toggled" bitfld.long 0x4C 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "Not toggled,Toggled" group.long 0x420++0x0F line.long 0x00 "IRQ,EPDC Interrupt Register" bitfld.long 0x00 23. " PWR_IRQ ,Power interrupt" "No interrupt,Interrupt" bitfld.long 0x00 22. " UPD_DONE_IRQ ,Working buffer process complete interrupt" "No interrupt,Interrupt" bitfld.long 0x00 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state" "No interrupt,Interrupt" bitfld.long 0x00 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period" "No interrupt,Interrupt" bitfld.long 0x00 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occured" "No interrupt,Interrupt" bitfld.long 0x00 17. " LUT_COL_IRQ ,Collision detection interrupt" "No interrupt,Interrupt" bitfld.long 0x00 16. " WB_CMPLT_IRQ ,Working buffer process complete interrupt" "No interrupt,Interrupt" line.long 0x04 "IRQ_SET,EPDC Interrupt Set Register" bitfld.long 0x04 23. " PWR_IRQ ,Power interrupt set" "No effect,Set" bitfld.long 0x04 22. " UPD_DONE_IRQ ,Working buffer process complete interrupt set" "No effect,Set" bitfld.long 0x04 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state set" "No effect,Set" bitfld.long 0x04 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs set" "No effect,Set" textline " " bitfld.long 0x04 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period set" "No effect,Set" bitfld.long 0x04 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occured set" "No effect,Set" bitfld.long 0x04 17. " LUT_COL_IRQ ,Collision detection interrupt set" "No effect,Set" bitfld.long 0x04 16. " WB_CMPLT_IRQ ,Working buffer process complete interrupt set" "No effect,Set" line.long 0x08 "IRQ,EPDC Interrupt Clear Register" bitfld.long 0x08 23. " PWR_IRQ ,Power interrupt clear" "No effect,Clear" bitfld.long 0x08 22. " UPD_DONE_IRQ ,Working buffer process complete interrupt clear" "No effect,Clear" bitfld.long 0x08 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state clear" "No effect,Clear" bitfld.long 0x08 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs clear" "No effect,Clear" textline " " bitfld.long 0x08 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period clear" "No effect,Clear" bitfld.long 0x08 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occured clear" "No effect,Clear" bitfld.long 0x08 17. " LUT_COL_IRQ ,Collision detection interrupt clear" "No effect,Clear" bitfld.long 0x08 16. " WB_CMPLT_IRQ ,Working buffer process complete interrupt clear" "No effect,Clear" line.long 0x0C "IRQ,EPDC Interrupt Toggle Register" bitfld.long 0x0C 23. " PWR_IRQ ,Power interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " UPD_DONE_IRQ ,Working buffer process complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occured toggle" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT_COL_IRQ ,Collision detection interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " WB_CMPLT_IRQ ,Working buffer process complete interrupt toggle" "Not toggled,Toggled" textline " " group.long 0x440++0x1F line.long 0x00 "STATUS_LUTS1,EPDC Status Register - Luts" bitfld.long 0x00 31. " LUT31_STS ,LUT31 status" "Idle,Active" bitfld.long 0x00 30. " LUT30_STS ,LUT30 status" "Idle,Active" bitfld.long 0x00 29. " LUT29_STS ,LUT29 status" "Idle,Active" bitfld.long 0x00 28. " LUT28_STS ,LUT28 status" "Idle,Active" textline " " bitfld.long 0x00 27. " LUT27_STS ,LUT27 status" "Idle,Active" bitfld.long 0x00 26. " LUT26_STS ,LUT26 status" "Idle,Active" bitfld.long 0x00 25. " LUT25_STS ,LUT25 status" "Idle,Active" bitfld.long 0x00 24. " LUT24_STS ,LUT24 status" "Idle,Active" textline " " bitfld.long 0x00 23. " LUT23_STS ,LUT23 status" "Idle,Active" bitfld.long 0x00 22. " LUT22_STS ,LUT22 status" "Idle,Active" bitfld.long 0x00 21. " LUT21_STS ,LUT21 status" "Idle,Active" bitfld.long 0x00 20. " LUT20_STS ,LUT20 status" "Idle,Active" textline " " bitfld.long 0x00 19. " LUT19_STS ,LUT19 status" "Idle,Active" bitfld.long 0x00 18. " LUT18_STS ,LUT18 status" "Idle,Active" bitfld.long 0x00 17. " LUT17_STS ,LUT17 status" "Idle,Active" bitfld.long 0x00 16. " LUT16_STS ,LUT16 status" "Idle,Active" textline " " bitfld.long 0x00 15. " LUT15_STS ,LUT15 status" "Idle,Active" bitfld.long 0x00 14. " LUT14_STS ,LUT14 status" "Idle,Active" bitfld.long 0x00 13. " LUT13_STS ,LUT13 status" "Idle,Active" bitfld.long 0x00 12. " LUT12_STS ,LUT12 status" "Idle,Active" textline " " bitfld.long 0x00 11. " LUT11_STS ,LUT11 status" "Idle,Active" bitfld.long 0x00 10. " LUT10_STS ,LUT10 status" "Idle,Active" bitfld.long 0x00 9. " LUT9_STS ,LUT9 status" "Idle,Active" bitfld.long 0x00 8. " LUT8_STS ,LUT8 status" "Idle,Active" textline " " bitfld.long 0x00 7. " LUT7_STS ,LUT7 status" "Idle,Active" bitfld.long 0x00 6. " LUT6_STS ,LUT6 status" "Idle,Active" bitfld.long 0x00 5. " LUT5_STS ,LUT5 status" "Idle,Active" bitfld.long 0x00 4. " LUT4_STS ,LUT4 status" "Idle,Active" textline " " bitfld.long 0x00 3. " LUT3_STS ,LUT3 status" "Idle,Active" bitfld.long 0x00 2. " LUT2_STS ,LUT2 status" "Idle,Active" bitfld.long 0x00 1. " LUT1_STS ,LUT1 status" "Idle,Active" bitfld.long 0x00 0. " LUT0_STS ,LUT0 status" "Idle,Active" line.long 0x04 "STATUS_LUTS1_SET,EPDC Status Set Register - Luts" bitfld.long 0x04 31. " LUT31_STS ,LUT31 status" "No effect,Set" bitfld.long 0x04 30. " LUT30_STS ,LUT30 status" "No effect,Set" bitfld.long 0x04 29. " LUT29_STS ,LUT29 status" "No effect,Set" bitfld.long 0x04 28. " LUT28_STS ,LUT28 status" "No effect,Set" textline " " bitfld.long 0x04 27. " LUT27_STS ,LUT27 status" "No effect,Set" bitfld.long 0x04 26. " LUT26_STS ,LUT26 status" "No effect,Set" bitfld.long 0x04 25. " LUT25_STS ,LUT25 status" "No effect,Set" bitfld.long 0x04 24. " LUT24_STS ,LUT24 status" "No effect,Set" textline " " bitfld.long 0x04 23. " LUT23_STS ,LUT23 status" "No effect,Set" bitfld.long 0x04 22. " LUT22_STS ,LUT22 status" "No effect,Set" bitfld.long 0x04 21. " LUT21_STS ,LUT21 status" "No effect,Set" bitfld.long 0x04 20. " LUT20_STS ,LUT20 status" "No effect,Set" textline " " bitfld.long 0x04 19. " LUT19_STS ,LUT19 status" "No effect,Set" bitfld.long 0x04 18. " LUT18_STS ,LUT18 status" "No effect,Set" bitfld.long 0x04 17. " LUT17_STS ,LUT17 status" "No effect,Set" bitfld.long 0x04 16. " LUT16_STS ,LUT16 status" "No effect,Set" textline " " bitfld.long 0x04 15. " LUT15_STS ,LUT15 status" "No effect,Set" bitfld.long 0x04 14. " LUT14_STS ,LUT14 status" "No effect,Set" bitfld.long 0x04 13. " LUT13_STS ,LUT13 status" "No effect,Set" bitfld.long 0x04 12. " LUT12_STS ,LUT12 status" "No effect,Set" textline " " bitfld.long 0x04 11. " LUT11_STS ,LUT11 status" "No effect,Set" bitfld.long 0x04 10. " LUT10_STS ,LUT10 status" "No effect,Set" bitfld.long 0x04 9. " LUT9_STS ,LUT9 status" "No effect,Set" bitfld.long 0x04 8. " LUT8_STS ,LUT8 status" "No effect,Set" textline " " bitfld.long 0x04 7. " LUT7_STS ,LUT7 status" "No effect,Set" bitfld.long 0x04 6. " LUT6_STS ,LUT6 status" "No effect,Set" bitfld.long 0x04 5. " LUT5_STS ,LUT5 status" "No effect,Set" bitfld.long 0x04 4. " LUT4_STS ,LUT4 status" "No effect,Set" textline " " bitfld.long 0x04 3. " LUT3_STS ,LUT3 status" "No effect,Set" bitfld.long 0x04 2. " LUT2_STS ,LUT2 status" "No effect,Set" bitfld.long 0x04 1. " LUT1_STS ,LUT1 status" "No effect,Set" bitfld.long 0x04 0. " LUT0_STS ,LUT0 status" "No effect,Set" line.long 0x08 "STATUS_LUTS1_CLR,EPDC Status Clear Register - Luts" bitfld.long 0x08 31. " LUT31_STS ,LUT31 status" "No effect,Clear" bitfld.long 0x08 30. " LUT30_STS ,LUT30 status" "No effect,Clear" bitfld.long 0x08 29. " LUT29_STS ,LUT29 status" "No effect,Clear" bitfld.long 0x08 28. " LUT28_STS ,LUT28 status" "No effect,Clear" textline " " bitfld.long 0x08 27. " LUT27_STS ,LUT27 status" "No effect,Clear" bitfld.long 0x08 26. " LUT26_STS ,LUT26 status" "No effect,Clear" bitfld.long 0x08 25. " LUT25_STS ,LUT25 status" "No effect,Clear" bitfld.long 0x08 24. " LUT24_STS ,LUT24 status" "No effect,Clear" textline " " bitfld.long 0x08 23. " LUT23_STS ,LUT23 status" "No effect,Clear" bitfld.long 0x08 22. " LUT22_STS ,LUT22 status" "No effect,Clear" bitfld.long 0x08 21. " LUT21_STS ,LUT21 status" "No effect,Clear" bitfld.long 0x08 20. " LUT20_STS ,LUT20 status" "No effect,Clear" textline " " bitfld.long 0x08 19. " LUT19_STS ,LUT19 status" "No effect,Clear" bitfld.long 0x08 18. " LUT18_STS ,LUT18 status" "No effect,Clear" bitfld.long 0x08 17. " LUT17_STS ,LUT17 status" "No effect,Clear" bitfld.long 0x08 16. " LUT16_STS ,LUT16 status" "No effect,Clear" textline " " bitfld.long 0x08 15. " LUT15_STS ,LUT15 status" "No effect,Clear" bitfld.long 0x08 14. " LUT14_STS ,LUT14 status" "No effect,Clear" bitfld.long 0x08 13. " LUT13_STS ,LUT13 status" "No effect,Clear" bitfld.long 0x08 12. " LUT12_STS ,LUT12 status" "No effect,Clear" textline " " bitfld.long 0x08 11. " LUT11_STS ,LUT11 status" "No effect,Clear" bitfld.long 0x08 10. " LUT10_STS ,LUT10 status" "No effect,Clear" bitfld.long 0x08 9. " LUT9_STS ,LUT9 status" "No effect,Clear" bitfld.long 0x08 8. " LUT8_STS ,LUT8 status" "No effect,Clear" textline " " bitfld.long 0x08 7. " LUT7_STS ,LUT7 status" "No effect,Clear" bitfld.long 0x08 6. " LUT6_STS ,LUT6 status" "No effect,Clear" bitfld.long 0x08 5. " LUT5_STS ,LUT5 status" "No effect,Clear" bitfld.long 0x08 4. " LUT4_STS ,LUT4 status" "No effect,Clear" textline " " bitfld.long 0x08 3. " LUT3_STS ,LUT3 status" "No effect,Clear" bitfld.long 0x08 2. " LUT2_STS ,LUT2 status" "No effect,Clear" bitfld.long 0x08 1. " LUT1_STS ,LUT1 status" "No effect,Clear" bitfld.long 0x08 0. " LUT0_STS ,LUT0 status" "No effect,Clear" line.long 0x0C "STATUS_LUTS1_TOG,EPDC Status Toggle Register - Luts" bitfld.long 0x0C 31. " LUT31_STS ,LUT31 status" "Not toggled,Toggled" bitfld.long 0x0C 30. " LUT30_STS ,LUT30 status" "Not toggled,Toggled" bitfld.long 0x0C 29. " LUT29_STS ,LUT29 status" "Not toggled,Toggled" bitfld.long 0x0C 28. " LUT28_STS ,LUT28 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 27. " LUT27_STS ,LUT27 status" "Not toggled,Toggled" bitfld.long 0x0C 26. " LUT26_STS ,LUT26 status" "Not toggled,Toggled" bitfld.long 0x0C 25. " LUT25_STS ,LUT25 status" "Not toggled,Toggled" bitfld.long 0x0C 24. " LUT24_STS ,LUT24 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " LUT23_STS ,LUT23 status" "Not toggled,Toggled" bitfld.long 0x0C 22. " LUT22_STS ,LUT22 status" "Not toggled,Toggled" bitfld.long 0x0C 21. " LUT21_STS ,LUT21 status" "Not toggled,Toggled" bitfld.long 0x0C 20. " LUT20_STS ,LUT20 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " LUT19_STS ,LUT19 status" "Not toggled,Toggled" bitfld.long 0x0C 18. " LUT18_STS ,LUT18 status" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT17_STS ,LUT17 status" "Not toggled,Toggled" bitfld.long 0x0C 16. " LUT16_STS ,LUT16 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 15. " LUT15_STS ,LUT15 status" "Not toggled,Toggled" bitfld.long 0x0C 14. " LUT14_STS ,LUT14 status" "Not toggled,Toggled" bitfld.long 0x0C 13. " LUT13_STS ,LUT13 status" "Not toggled,Toggled" bitfld.long 0x0C 12. " LUT12_STS ,LUT12 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " LUT11_STS ,LUT11 status" "Not toggled,Toggled" bitfld.long 0x0C 10. " LUT10_STS ,LUT10 status" "Not toggled,Toggled" bitfld.long 0x0C 9. " LUT9_STS ,LUT9 status" "Not toggled,Toggled" bitfld.long 0x0C 8. " LUT8_STS ,LUT8 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LUT7_STS ,LUT7 status" "Not toggled,Toggled" bitfld.long 0x0C 6. " LUT6_STS ,LUT6 status" "Not toggled,Toggled" bitfld.long 0x0C 5. " LUT5_STS ,LUT5 status" "Not toggled,Toggled" bitfld.long 0x0C 4. " LUT4_STS ,LUT4 status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " LUT3_STS ,LUT3 status" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUT2_STS ,LUT2 status" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUT1_STS ,LUT1 status" "Not toggled,Toggled" bitfld.long 0x0C 0. " LUT0_STS ,LUT0 status" "Not toggled,Toggled" line.long 0x10 "STATUS_LUTS2,EPDC Status Register - Luts" bitfld.long 0x10 31. " LUT63_STS ,LUT63 status" "Idle,Active" bitfld.long 0x10 30. " LUT62_STS ,LUT62 status" "Idle,Active" bitfld.long 0x10 29. " LUT61_STS ,LUT61 status" "Idle,Active" bitfld.long 0x10 28. " LUT60_STS ,LUT60 status" "Idle,Active" textline " " bitfld.long 0x10 27. " LUT59_STS ,LUT59 status" "Idle,Active" bitfld.long 0x10 26. " LUT58_STS ,LUT58 status" "Idle,Active" bitfld.long 0x10 25. " LUT57_STS ,LUT57 status" "Idle,Active" bitfld.long 0x10 24. " LUT56_STS ,LUT56 status" "Idle,Active" textline " " bitfld.long 0x10 23. " LUT55_STS ,LUT55 status" "Idle,Active" bitfld.long 0x10 22. " LUT54_STS ,LUT54 status" "Idle,Active" bitfld.long 0x10 21. " LUT53_STS ,LUT53 status" "Idle,Active" bitfld.long 0x10 20. " LUT52_STS ,LUT52 status" "Idle,Active" textline " " bitfld.long 0x10 19. " LUT51_STS ,LUT51 status" "Idle,Active" bitfld.long 0x10 18. " LUT50_STS ,LUT50 status" "Idle,Active" bitfld.long 0x10 17. " LUT49_STS ,LUT49 status" "Idle,Active" bitfld.long 0x10 16. " LUT48_STS ,LUT48 status" "Idle,Active" textline " " bitfld.long 0x10 15. " LUT47_STS ,LUT47 status" "Idle,Active" bitfld.long 0x10 14. " LUT46_STS ,LUT46 status" "Idle,Active" bitfld.long 0x10 13. " LUT45_STS ,LUT45 status" "Idle,Active" bitfld.long 0x10 12. " LUT44_STS ,LUT44 status" "Idle,Active" textline " " bitfld.long 0x10 11. " LUT43_STS ,LUT43 status" "Idle,Active" bitfld.long 0x10 10. " LUT42_STS ,LUT42 status" "Idle,Active" bitfld.long 0x10 9. " LUT41_STS ,LUT41 status" "Idle,Active" bitfld.long 0x10 8. " LUT40_STS ,LUT40 status" "Idle,Active" textline " " bitfld.long 0x10 7. " LUT39_STS ,LUT39 status" "Idle,Active" bitfld.long 0x10 6. " LUT38_STS ,LUT38 status" "Idle,Active" bitfld.long 0x10 5. " LUT37_STS ,LUT37 status" "Idle,Active" bitfld.long 0x10 4. " LUT36_STS ,LUT36 status" "Idle,Active" textline " " bitfld.long 0x10 3. " LUT35_STS ,LUT35 status" "Idle,Active" bitfld.long 0x10 2. " LUT34_STS ,LUT34 status" "Idle,Active" bitfld.long 0x10 1. " LUT33_STS ,LUT33 status" "Idle,Active" bitfld.long 0x10 0. " LUT32_STS ,LUT32 status" "Idle,Active" line.long 0x14 "STATUS_LUTS2_SET,EPDC Status Set Register - Luts" bitfld.long 0x14 31. " LUTN_ST63 ,LUT63 status" "No effect,Set" bitfld.long 0x14 30. " LUT62_STS ,LUT62 status" "No effect,Set" bitfld.long 0x14 29. " LUT61_STS ,LUT61 status" "No effect,Set" bitfld.long 0x14 28. " LUT60_STS ,LUT60 status" "No effect,Set" textline " " bitfld.long 0x14 27. " LUT59_STS ,LUT59 status" "No effect,Set" bitfld.long 0x14 26. " LUT58_STS ,LUT58 status" "No effect,Set" bitfld.long 0x14 25. " LUT57_STS ,LUT57 status" "No effect,Set" bitfld.long 0x14 24. " LUT56_STS ,LUT56 status" "No effect,Set" textline " " bitfld.long 0x14 23. " LUT55_STS ,LUT55 status" "No effect,Set" bitfld.long 0x14 22. " LUT54_STS ,LUT54 status" "No effect,Set" bitfld.long 0x14 21. " LUT53_STS ,LUT53 status" "No effect,Set" bitfld.long 0x14 20. " LUT52_STS ,LUT52 status" "No effect,Set" textline " " bitfld.long 0x14 19. " LUT51_STS ,LUT51 status" "No effect,Set" bitfld.long 0x14 18. " LUT50_STS ,LUT50 status" "No effect,Set" bitfld.long 0x14 17. " LUT49_STS ,LUT49 status" "No effect,Set" bitfld.long 0x14 16. " LUT48_STS ,LUT48 status" "No effect,Set" textline " " bitfld.long 0x14 15. " LUT47_STS ,LUT47 status" "No effect,Set" bitfld.long 0x14 14. " LUT46_STS ,LUT46 status" "No effect,Set" bitfld.long 0x14 13. " LUT45_STS ,LUT45 status" "No effect,Set" bitfld.long 0x14 12. " LUT44_STS ,LUT44 status" "No effect,Set" textline " " bitfld.long 0x14 11. " LUT43_STS ,LUT43 status" "No effect,Set" bitfld.long 0x14 10. " LUT42_STS ,LUT42 status" "No effect,Set" bitfld.long 0x14 9. " LUT41_STS ,LUT41 status" "No effect,Set" bitfld.long 0x14 8. " LUT40_STS ,LUT40 status" "No effect,Set" textline " " bitfld.long 0x14 7. " LUT39_STS ,LUT39 status" "No effect,Set" bitfld.long 0x14 6. " LUT38_STS ,LUT38 status" "No effect,Set" bitfld.long 0x14 5. " LUT37_STS ,LUT37 status" "No effect,Set" bitfld.long 0x14 4. " LUT36_STS ,LUT36 status" "No effect,Set" textline " " bitfld.long 0x14 3. " LUT35_STS ,LUT35 status" "No effect,Set" bitfld.long 0x14 2. " LUT34_STS ,LUT34 status" "No effect,Set" bitfld.long 0x14 1. " LUT33_STS ,LUT33 status" "No effect,Set" bitfld.long 0x14 0. " LUT32_STS ,LUT32 status" "No effect,Set" line.long 0x18 "STATUS_LUTS2_CLR,EPDC status Register - Luts" bitfld.long 0x18 31. " LUT63_STS ,LUT63 status" "No effect,Clear" bitfld.long 0x18 30. " LUT62_STS ,LUT62 status" "No effect,Clear" bitfld.long 0x18 29. " LUT61_STS ,LUT61 status" "No effect,Clear" bitfld.long 0x18 28. " LUT60_STS ,LUT60 status" "No effect,Clear" textline " " bitfld.long 0x18 27. " LUT59_STS ,LUT59 status" "No effect,Clear" bitfld.long 0x18 26. " LUT58_STS ,LUT58 status" "No effect,Clear" bitfld.long 0x18 25. " LUT57_STS ,LUT57 status" "No effect,Clear" bitfld.long 0x18 24. " LUT56_STS ,LUT56 status" "No effect,Clear" textline " " bitfld.long 0x18 23. " LUT55_STS ,LUT55 status" "No effect,Clear" bitfld.long 0x18 22. " LUT54_STS ,LUT54 status" "No effect,Clear" bitfld.long 0x18 21. " LUT53_STS ,LUT53 status" "No effect,Clear" bitfld.long 0x18 20. " LUT52_STS ,LUT52 status" "No effect,Clear" textline " " bitfld.long 0x18 19. " LUT51_STS ,LUT51 status" "No effect,Clear" bitfld.long 0x18 18. " LUT50_STS ,LUT50 status" "No effect,Clear" bitfld.long 0x18 17. " LUT49_STS ,LUT49 status" "No effect,Clear" bitfld.long 0x18 16. " LUT48_STS ,LUT48 status" "No effect,Clear" textline " " bitfld.long 0x18 15. " LUT47_STS ,LUT47 status" "No effect,Clear" bitfld.long 0x18 14. " LUT46_STS ,LUT46 status" "No effect,Clear" bitfld.long 0x18 13. " LUT45_STS ,LUT45 status" "No effect,Clear" bitfld.long 0x18 12. " LUT44_STS ,LUT44 status" "No effect,Clear" textline " " bitfld.long 0x18 11. " LUT43_STS ,LUT43 status" "No effect,Clear" bitfld.long 0x18 10. " LUT42_STS ,LUT42 status" "No effect,Clear" bitfld.long 0x18 9. " LUT41_STS ,LUT41 status" "No effect,Clear" bitfld.long 0x18 8. " LUT40_STS ,LUT40 status" "No effect,Clear" textline " " bitfld.long 0x18 7. " LUT39_STS ,LUT39 status" "No effect,Clear" bitfld.long 0x18 6. " LUT38_STS ,LUT38 status" "No effect,Clear" bitfld.long 0x18 5. " LUT37_STS ,LUT37 status" "No effect,Clear" bitfld.long 0x18 4. " LUT36_STS ,LUT36 status" "No effect,Clear" textline " " bitfld.long 0x18 3. " LUT35_STS ,LUT35 status" "No effect,Clear" bitfld.long 0x18 2. " LUT34_STS ,LUT34 status" "No effect,Clear" bitfld.long 0x18 1. " LUT33_STS ,LUT33 status" "No effect,Clear" bitfld.long 0x18 0. " LUT32_STS ,LUT32 status" "No effect,Clear" line.long 0x1C "STATUS_LUTS2_TOG,EPDC status toggle Register - Luts" bitfld.long 0x1C 31. " LUT63_STS ,LUT63 status" "Not toggled,Toggled" bitfld.long 0x1C 30. " LUT62_STS ,LUT62 status" "Not toggled,Toggled" bitfld.long 0x1C 29. " LUT61_STS ,LUT61 status" "Not toggled,Toggled" bitfld.long 0x1C 28. " LUT60_STS ,LUT60 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 27. " LUT59_STS ,LUT59 status" "Not toggled,Toggled" bitfld.long 0x1C 26. " LUT58_STS ,LUT58 status" "Not toggled,Toggled" bitfld.long 0x1C 25. " LUT57_STS ,LUT57 status" "Not toggled,Toggled" bitfld.long 0x1C 24. " LUT56_STS ,LUT56 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 23. " LUT55_STS ,LUT55 status" "Not toggled,Toggled" bitfld.long 0x1C 22. " LUT54_STS ,LUT54 status" "Not toggled,Toggled" bitfld.long 0x1C 21. " LUT53_STS ,LUT53 status" "Not toggled,Toggled" bitfld.long 0x1C 20. " LUT52_STS ,LUT52 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 19. " LUT51_STS ,LUT51 status" "Not toggled,Toggled" bitfld.long 0x1C 18. " LUT50_STS ,LUT50 status" "Not toggled,Toggled" bitfld.long 0x1C 17. " LUT49_STS ,LUT49 status" "Not toggled,Toggled" bitfld.long 0x1C 16. " LUT48_STS ,LUT48 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 15. " LUT47_STS ,LUT47 status" "Not toggled,Toggled" bitfld.long 0x1C 14. " LUT46_STS ,LUT46 status" "Not toggled,Toggled" bitfld.long 0x1C 13. " LUT45_STS ,LUT45 status" "Not toggled,Toggled" bitfld.long 0x1C 12. " LUT44_STS ,LUT44 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 11. " LUT43_STS ,LUT43 status" "Not toggled,Toggled" bitfld.long 0x1C 10. " LUT42_STS ,LUT42 status" "Not toggled,Toggled" bitfld.long 0x1C 9. " LUT41_STS ,LUT41 status" "Not toggled,Toggled" bitfld.long 0x1C 8. " LUT40_STS ,LUT40 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 7. " LUT39_STS ,LUT39 status" "Not toggled,Toggled" bitfld.long 0x1C 6. " LUT38_STS ,LUT38 status" "Not toggled,Toggled" bitfld.long 0x1C 5. " LUT37_STS ,LUT37 status" "Not toggled,Toggled" bitfld.long 0x1C 4. " LUT36_STS ,LUT36 status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 3. " LUT35_STS ,LUT35 status" "Not toggled,Toggled" bitfld.long 0x1C 2. " LUT34_STS ,LUT34 status" "Not toggled,Toggled" bitfld.long 0x1C 1. " LUT33_STS ,LUT33 status" "Not toggled,Toggled" bitfld.long 0x1C 0. " LUT32_STS ,LUT32 status" "Not toggled,Toggled" rgroup.long 0x460++0x03 line.long 0x00 "STATUS_NEXTLUT,EPDC Status Register - Next Available LUT" bitfld.long 0x00 8. " NEXT_LUT_VALID ,Checks against a luts full condition" "Not checked,Checked" bitfld.long 0x00 0.--5. " NEXT_LUT ,Next available LUT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x480++0x1F line.long 0x00 "STATUS_COL1,EPDC LUT Collision Status" bitfld.long 0x00 31. " LUT31_COL_STS ,LUT31 collision status" "No collision,Collision" bitfld.long 0x00 30. " LUT30_COL_STS ,LUT30 collision status" "No collision,Collision" bitfld.long 0x00 29. " LUT29_COL_STS ,LUT29 collision status" "No collision,Collision" bitfld.long 0x00 28. " LUT28_COL_STS ,LUT28 collision status" "No collision,Collision" textline " " bitfld.long 0x00 27. " LUT27_COL_STS ,LUT27 collision status" "No collision,Collision" bitfld.long 0x00 26. " LUT26_COL_STS ,LUT26 collision status" "No collision,Collision" bitfld.long 0x00 25. " LUT25_COL_STS ,LUT25 collision status" "No collision,Collision" bitfld.long 0x00 24. " LUT24_COL_STS ,LUT24 collision status" "No collision,Collision" textline " " bitfld.long 0x00 23. " LUT23_COL_STS ,LUT23 collision status" "No collision,Collision" bitfld.long 0x00 22. " LUT22_COL_STS ,LUT22 collision status" "No collision,Collision" bitfld.long 0x00 21. " LUT21_COL_STS ,LUT21 collision status" "No collision,Collision" bitfld.long 0x00 20. " LUT20_COL_STS ,LUT20 collision status" "No collision,Collision" textline " " bitfld.long 0x00 19. " LUT19_COL_STS ,LUT19 collision status" "No collision,Collision" bitfld.long 0x00 18. " LUT18_COL_STS ,LUT18 collision status" "No collision,Collision" bitfld.long 0x00 17. " LUT17_COL_STS ,LUT17 collision status" "No collision,Collision" bitfld.long 0x00 16. " LUT16_COL_STS ,LUT16 collision status" "No collision,Collision" textline " " bitfld.long 0x00 15. " LUT15_COL_STS ,LUT15 collision status" "No collision,Collision" bitfld.long 0x00 14. " LUT14_COL_STS ,LUT14 collision status" "No collision,Collision" bitfld.long 0x00 13. " LUT13_COL_STS ,LUT13 collision status" "No collision,Collision" bitfld.long 0x00 12. " LUT12_COL_STS ,LUT12 collision status" "No collision,Collision" textline " " bitfld.long 0x00 11. " LUT11_COL_STS ,LUT11 collision status" "No collision,Collision" bitfld.long 0x00 10. " LUT10_COL_STS ,LUT10 collision status" "No collision,Collision" bitfld.long 0x00 9. " LUT9_COL_STS ,LUT9 collision status" "No collision,Collision" bitfld.long 0x00 8. " LUT8_COL_STS ,LUT8 collision status" "No collision,Collision" textline " " bitfld.long 0x00 7. " LUT7_COL_STS ,LUT7 collision status" "No collision,Collision" bitfld.long 0x00 6. " LUT6_COL_STS ,LUT6 collision status" "No collision,Collision" bitfld.long 0x00 5. " LUT5_COL_STS ,LUT5 collision status" "No collision,Collision" bitfld.long 0x00 4. " LUT4_COL_STS ,LUT4 collision status" "No collision,Collision" textline " " bitfld.long 0x00 3. " LUT3_COL_STS ,LUT3 collision status" "No collision,Collision" bitfld.long 0x00 2. " LUT2_COL_STS ,LUT2 collision status" "No collision,Collision" bitfld.long 0x00 1. " LUT1_COL_STS ,LUT1 collision status" "No collision,Collision" bitfld.long 0x00 0. " LUT0_COL_STS ,LUT0 collision status" "No collision,Collision" line.long 0x04 "STATUS_COL1_SET,EPDC LUT Collision Status Set" bitfld.long 0x04 31. " LUT31_COL_STS ,LUT31 collision status" "No effect,Set" bitfld.long 0x04 30. " LUT30_COL_STS ,LUT30 collision status" "No effect,Set" bitfld.long 0x04 29. " LUT29_COL_STS ,LUT29 collision status" "No effect,Set" bitfld.long 0x04 28. " LUT28_COL_STS ,LUT28 collision status" "No effect,Set" textline " " bitfld.long 0x04 27. " LUT27_COL_STS ,LUT27 collision status" "No effect,Set" bitfld.long 0x04 26. " LUT26_COL_STS ,LUT26 collision status" "No effect,Set" bitfld.long 0x04 25. " LUT25_COL_STS ,LUT25 collision status" "No effect,Set" bitfld.long 0x04 24. " LUT24_COL_STS ,LUT24 collision status" "No effect,Set" textline " " bitfld.long 0x04 23. " LUT23_COL_STS ,LUT23 collision status" "No effect,Set" bitfld.long 0x04 22. " LUT22_COL_STS ,LUT22 collision status" "No effect,Set" bitfld.long 0x04 21. " LUT21_COL_STS ,LUT21 collision status" "No effect,Set" bitfld.long 0x04 20. " LUT20_COL_STS ,LUT20 collision status" "No effect,Set" textline " " bitfld.long 0x04 19. " LUT19_COL_STS ,LUT19 collision status" "No effect,Set" bitfld.long 0x04 18. " LUT18_COL_STS ,LUT18 collision status" "No effect,Set" bitfld.long 0x04 17. " LUT17_COL_STS ,LUT17 collision status" "No effect,Set" bitfld.long 0x04 16. " LUT16_COL_STS ,LUT16 collision status" "No effect,Set" textline " " bitfld.long 0x04 15. " LUT15_COL_STS ,LUT15 collision status" "No effect,Set" bitfld.long 0x04 14. " LUT14_COL_STS ,LUT14 collision status" "No effect,Set" bitfld.long 0x04 13. " LUT13_COL_STS ,LUT13 collision status" "No effect,Set" bitfld.long 0x04 12. " LUT12_COL_STS ,LUT12 collision status" "No effect,Set" textline " " bitfld.long 0x04 11. " LUT11_COL_STS ,LUT11 collision status" "No effect,Set" bitfld.long 0x04 10. " LUT10_COL_STS ,LUT10 collision status" "No effect,Set" bitfld.long 0x04 9. " LUT9_COL_STS ,LUT9 collision status" "No effect,Set" bitfld.long 0x04 8. " LUT8_COL_STS ,LUT8 collision status" "No effect,Set" textline " " bitfld.long 0x04 7. " LUT7_COL_STS ,LUT7 collision status" "No effect,Set" bitfld.long 0x04 6. " LUT6_COL_STS ,LUT6 collision status" "No effect,Set" bitfld.long 0x04 5. " LUT5_COL_STS ,LUT5 collision status" "No effect,Set" bitfld.long 0x04 4. " LUT4_COL_STS ,LUT4 collision status" "No effect,Set" textline " " bitfld.long 0x04 3. " LUT3_COL_STS ,LUT3 collision status" "No effect,Set" bitfld.long 0x04 2. " LUT2_COL_STS ,LUT2 collision status" "No effect,Set" bitfld.long 0x04 1. " LUT1_COL_STS ,LUT1 collision status" "No effect,Set" bitfld.long 0x04 0. " LUT0_COL_STS ,LUT0 collision status" "No effect,Set" line.long 0x08 "STATUS_COL1_CLR,EPDC LUT Collision Status Clear" bitfld.long 0x08 31. " LUT31_COL_STS ,LUT31 collision status" "No effect,Clear" bitfld.long 0x08 30. " LUT30_COL_STS ,LUT30 collision status" "No effect,Clear" bitfld.long 0x08 29. " LUT29_COL_STS ,LUT29 collision status" "No effect,Clear" bitfld.long 0x08 28. " LUT28_COL_STS ,LUT28 collision status" "No effect,Clear" textline " " bitfld.long 0x08 27. " LUT27_COL_STS ,LUT27 collision status" "No effect,Clear" bitfld.long 0x08 26. " LUT26_COL_STS ,LUT26 collision status" "No effect,Clear" bitfld.long 0x08 25. " LUT25_COL_STS ,LUT25 collision status" "No effect,Clear" bitfld.long 0x08 24. " LUT24_COL_STS ,LUT24 collision status" "No effect,Clear" textline " " bitfld.long 0x08 23. " LUT23_COL_STS ,LUT23 collision status" "No effect,Clear" bitfld.long 0x08 22. " LUT22_COL_STS ,LUT22 collision status" "No effect,Clear" bitfld.long 0x08 21. " LUT21_COL_STS ,LUT21 collision status" "No effect,Clear" bitfld.long 0x08 20. " LUT20_COL_STS ,LUT20 collision status" "No effect,Clear" textline " " bitfld.long 0x08 19. " LUT19_COL_STS ,LUT19 collision status" "No effect,Clear" bitfld.long 0x08 18. " LUT18_COL_STS ,LUT18 collision status" "No effect,Clear" bitfld.long 0x08 17. " LUT17_COL_STS ,LUT17 collision status" "No effect,Clear" bitfld.long 0x08 16. " LUT16_COL_STS ,LUT16 collision status" "No effect,Clear" textline " " bitfld.long 0x08 15. " LUT15_COL_STS ,LUT15 collision status" "No effect,Clear" bitfld.long 0x08 14. " LUT14_COL_STS ,LUT14 collision status" "No effect,Clear" bitfld.long 0x08 13. " LUT13_COL_STS ,LUT13 collision status" "No effect,Clear" bitfld.long 0x08 12. " LUT12_COL_STS ,LUT12 collision status" "No effect,Clear" textline " " bitfld.long 0x08 11. " LUT11_COL_STS ,LUT11 collision status" "No effect,Clear" bitfld.long 0x08 10. " LUT10_COL_STS ,LUT10 collision status" "No effect,Clear" bitfld.long 0x08 9. " LUT9_COL_STS ,LUT9 collision status" "No effect,Clear" bitfld.long 0x08 8. " LUT8_COL_STS ,LUT8 collision status" "No effect,Clear" textline " " bitfld.long 0x08 7. " LUT7_COL_STS ,LUT7 collision status" "No effect,Clear" bitfld.long 0x08 6. " LUT6_COL_STS ,LUT6 collision status" "No effect,Clear" bitfld.long 0x08 5. " LUT5_COL_STS ,LUT5 collision status" "No effect,Clear" bitfld.long 0x08 4. " LUT4_COL_STS ,LUT4 collision status" "No effect,Clear" textline " " bitfld.long 0x08 3. " LUT3_COL_STS ,LUT3 collision status" "No effect,Clear" bitfld.long 0x08 2. " LUT2_COL_STS ,LUT2 collision status" "No effect,Clear" bitfld.long 0x08 1. " LUT1_COL_STS ,LUT1 collision status" "No effect,Clear" bitfld.long 0x08 0. " LUT0_COL_STS ,LUT0 collision status" "No effect,Clear" line.long 0x0C "STATUS_COL1_TOG,EPDC LUT Collision Status Toggle" bitfld.long 0x0C 31. " LUT31_COL_STS ,LUT31 collision status" "Not toggled,Toggled" bitfld.long 0x0C 30. " LUT30_COL_STS ,LUT30 collision status" "Not toggled,Toggled" bitfld.long 0x0C 29. " LUT29_COL_STS ,LUT29 collision status" "Not toggled,Toggled" bitfld.long 0x0C 28. " LUT28_COL_STS ,LUT28 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 27. " LUT27_COL_STS ,LUT27 collision status" "Not toggled,Toggled" bitfld.long 0x0C 26. " LUT26_COL_STS ,LUT26 collision status" "Not toggled,Toggled" bitfld.long 0x0C 25. " LUT25_COL_STS ,LUT25 collision status" "Not toggled,Toggled" bitfld.long 0x0C 24. " LUT24_COL_STS ,LUT24 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " LUT23_COL_STS ,LUT23 collision status" "Not toggled,Toggled" bitfld.long 0x0C 22. " LUT22_COL_STS ,LUT22 collision status" "Not toggled,Toggled" bitfld.long 0x0C 21. " LUT21_COL_STS ,LUT21 collision status" "Not toggled,Toggled" bitfld.long 0x0C 20. " LUT20_COL_STS ,LUT20 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " LUT19_COL_STS ,LUT19 collision status" "Not toggled,Toggled" bitfld.long 0x0C 18. " LUT18_COL_STS ,LUT18 collision status" "Not toggled,Toggled" bitfld.long 0x0C 17. " LUT17_COL_STS ,LUT17 collision status" "Not toggled,Toggled" bitfld.long 0x0C 16. " LUT16_COL_STS ,LUT16 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 15. " LUT15_COL_STS ,LUT15 collision status" "Not toggled,Toggled" bitfld.long 0x0C 14. " LUT14_COL_STS ,LUT14 collision status" "Not toggled,Toggled" bitfld.long 0x0C 13. " LUT13_COL_STS ,LUT13 collision status" "Not toggled,Toggled" bitfld.long 0x0C 12. " LUT12_COL_STS ,LUT12 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " LUT11_COL_STS ,LUT11 collision status" "Not toggled,Toggled" bitfld.long 0x0C 10. " LUT10_COL_STS ,LUT10 collision status" "Not toggled,Toggled" bitfld.long 0x0C 9. " LUT9_COL_STS ,LUT9 collision status" "Not toggled,Toggled" bitfld.long 0x0C 8. " LUT8_COL_STS ,LUT8 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 7. " LUT7_COL_STS ,LUT7 collision status" "Not toggled,Toggled" bitfld.long 0x0C 6. " LUT6_COL_STS ,LUT6 collision status" "Not toggled,Toggled" bitfld.long 0x0C 5. " LUT5_COL_STS ,LUT5 collision status" "Not toggled,Toggled" bitfld.long 0x0C 4. " LUT4_COL_STS ,LUT4 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x0C 3. " LUT3_COL_STS ,LUT3 collision status" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUT2_COL_STS ,LUT2 collision status" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUT1_COL_STS ,LUT1 collision status" "Not toggled,Toggled" bitfld.long 0x0C 0. " LUT0_COL_STS ,LUT0 collision status" "Not toggled,Toggled" line.long 0x10 "STATUS_COL2,EPDC LUT Collision Status" bitfld.long 0x10 31. " LUT63_COL_STS ,LUT63 collision status" "No collision,Collision" bitfld.long 0x10 30. " LUT62_COL_STS ,LUT62 collision status" "No collision,Collision" bitfld.long 0x10 29. " LUT61_COL_STS ,LUT61 collision status" "No collision,Collision" bitfld.long 0x10 28. " LUT60_COL_STS ,LUT60 collision status" "No collision,Collision" textline " " bitfld.long 0x10 27. " LUT59_COL_STS ,LUT59 collision status" "No collision,Collision" bitfld.long 0x10 26. " LUT58_COL_STS ,LUT58 collision status" "No collision,Collision" bitfld.long 0x10 25. " LUT57_COL_STS ,LUT57 collision status" "No collision,Collision" bitfld.long 0x10 24. " LUT56_COL_STS ,LUT56 collision status" "No collision,Collision" textline " " bitfld.long 0x10 23. " LUT55_COL_STS ,LUT55 collision status" "No collision,Collision" bitfld.long 0x10 22. " LUT54_COL_STS ,LUT54 collision status" "No collision,Collision" bitfld.long 0x10 21. " LUT53_COL_STS ,LUT53 collision status" "No collision,Collision" bitfld.long 0x10 20. " LUT52_COL_STS ,LUT52 collision status" "No collision,Collision" textline " " bitfld.long 0x10 19. " LUT51_COL_STS ,LUT51 collision status" "No collision,Collision" bitfld.long 0x10 18. " LUT50_COL_STS ,LUT50 collision status" "No collision,Collision" bitfld.long 0x10 17. " LUT49_COL_STS ,LUT49 collision status" "No collision,Collision" bitfld.long 0x10 16. " LUT48_COL_STS ,LUT48 collision status" "No collision,Collision" textline " " bitfld.long 0x10 15. " LUT47_COL_STS ,LUT47 collision status" "No collision,Collision" bitfld.long 0x10 14. " LUT46_COL_STS ,LUT46 collision status" "No collision,Collision" bitfld.long 0x10 13. " LUT45_COL_STS ,LUT45 collision status" "No collision,Collision" bitfld.long 0x10 12. " LUT44_COL_STS ,LUT44 collision status" "No collision,Collision" textline " " bitfld.long 0x10 11. " LUT43_COL_STS ,LUT43 collision status" "No collision,Collision" bitfld.long 0x10 10. " LUT42_COL_STS ,LUT42 collision status" "No collision,Collision" bitfld.long 0x10 9. " LUT41_COL_STS ,LUT41 collision status" "No collision,Collision" bitfld.long 0x10 8. " LUT40_COL_STS ,LUT40 collision status" "No collision,Collision" textline " " bitfld.long 0x10 7. " LUT39_COL_STS ,LUT39 collision status" "No collision,Collision" bitfld.long 0x10 6. " LUT38_COL_STS ,LUT38 collision status" "No collision,Collision" bitfld.long 0x10 5. " LUT37_COL_STS ,LUT37 collision status" "No collision,Collision" bitfld.long 0x10 4. " LUT36_COL_STS ,LUT36 collision status" "No collision,Collision" textline " " bitfld.long 0x10 3. " LUT35_COL_STS ,LUT35 collision status" "No collision,Collision" bitfld.long 0x10 2. " LUT34_COL_STS ,LUT34 collision status" "No collision,Collision" bitfld.long 0x10 1. " LUT33_COL_STS ,LUT33 collision status" "No collision,Collision" bitfld.long 0x10 0. " LUT32_COL_STS ,LUT32 collision status" "No collision,Collision" line.long 0x14 "STATUS_COL2_SET,EPDC LUT Collision Status Set" bitfld.long 0x14 31. " LUT63_COL_STS ,LUT63 collision status" "No effect,Set" bitfld.long 0x14 30. " LUT62_COL_STS ,LUT62 collision status" "No effect,Set" bitfld.long 0x14 29. " LUT61_COL_STS ,LUT61 collision status" "No effect,Set" bitfld.long 0x14 28. " LUT60_COL_STS ,LUT60 collision status" "No effect,Set" textline " " bitfld.long 0x14 27. " LUT59_COL_STS ,LUT59 collision status" "No effect,Set" bitfld.long 0x14 26. " LUT58_COL_STS ,LUT58 collision status" "No effect,Set" bitfld.long 0x14 25. " LUT57_COL_STS ,LUT57 collision status" "No effect,Set" bitfld.long 0x14 24. " LUT56_COL_STS ,LUT56 collision status" "No effect,Set" textline " " bitfld.long 0x14 23. " LUT55_COL_STS ,LUT55 collision status" "No effect,Set" bitfld.long 0x14 22. " LUT54_COL_STS ,LUT54 collision status" "No effect,Set" bitfld.long 0x14 21. " LUT53_COL_STS ,LUT53 collision status" "No effect,Set" bitfld.long 0x14 20. " LUT52_COL_STS ,LUT52 collision status" "No effect,Set" textline " " bitfld.long 0x14 19. " LUT51_COL_STS ,LUT51 collision status" "No effect,Set" bitfld.long 0x14 18. " LUT50_COL_STS ,LUT50 collision status" "No effect,Set" bitfld.long 0x14 17. " LUT49_COL_STS ,LUT49 collision status" "No effect,Set" bitfld.long 0x14 16. " LUT48_COL_STS ,LUT48 collision status" "No effect,Set" textline " " bitfld.long 0x14 15. " LUT47_COL_STS ,LUT47 collision status" "No effect,Set" bitfld.long 0x14 14. " LUT46_COL_STS ,LUT46 collision status" "No effect,Set" bitfld.long 0x14 13. " LUT45_COL_STS ,LUT45 collision status" "No effect,Set" bitfld.long 0x14 12. " LUT44_COL_STS ,LUT44 collision status" "No effect,Set" textline " " bitfld.long 0x14 11. " LUT43_COL_STS ,LUT43 collision status" "No effect,Set" bitfld.long 0x14 10. " LUT42_COL_STS ,LUT42 collision status" "No effect,Set" bitfld.long 0x14 9. " LUT41_COL_STS ,LUT41 collision status" "No effect,Set" bitfld.long 0x14 8. " LUT40_COL_STS ,LUT40 collision status" "No effect,Set" textline " " bitfld.long 0x14 7. " LUT39_COL_STS ,LUT39 collision status" "No effect,Set" bitfld.long 0x14 6. " LUT38_COL_STS ,LUT38 collision status" "No effect,Set" bitfld.long 0x14 5. " LUT37_COL_STS ,LUT37 collision status" "No effect,Set" bitfld.long 0x14 4. " LUT36_COL_STS ,LUT36 collision status" "No effect,Set" textline " " bitfld.long 0x14 3. " LUT35_COL_STS ,LUT35 collision status" "No effect,Set" bitfld.long 0x14 2. " LUT34_COL_STS ,LUT34 collision status" "No effect,Set" bitfld.long 0x14 1. " LUT33_COL_STS ,LUT33 collision status" "No effect,Set" bitfld.long 0x14 0. " LUT32_COL_STS ,LUT32 collision status" "No effect,Set" line.long 0x18 "STATUS_COL2_CLR,EPDC LUT Collision status clear" bitfld.long 0x18 31. " LUT63_COL_STS ,LUT63 collision status" "No effect,Clear" bitfld.long 0x18 30. " LUT62_COL_STS ,LUT62 collision status" "No effect,Clear" bitfld.long 0x18 29. " LUT61_COL_STS ,LUT61 collision status" "No effect,Clear" bitfld.long 0x18 28. " LUT60_COL_STS ,LUT60 collision status" "No effect,Clear" textline " " bitfld.long 0x18 27. " LUT59_COL_STS ,LUT59 collision status" "No effect,Clear" bitfld.long 0x18 26. " LUT58_COL_STS ,LUT58 collision status" "No effect,Clear" bitfld.long 0x18 25. " LUT57_COL_STS ,LUT57 collision status" "No effect,Clear" bitfld.long 0x18 24. " LUT56_COL_STS ,LUT56 collision status" "No effect,Clear" textline " " bitfld.long 0x18 23. " LUT55_COL_STS ,LUT55 collision status" "No effect,Clear" bitfld.long 0x18 22. " LUT54_COL_STS ,LUT54 collision status" "No effect,Clear" bitfld.long 0x18 21. " LUT53_COL_STS ,LUT53 collision status" "No effect,Clear" bitfld.long 0x18 20. " LUT52_COL_STS ,LUT52 collision status" "No effect,Clear" textline " " bitfld.long 0x18 19. " LUT51_COL_STS ,LUT51 collision status" "No effect,Clear" bitfld.long 0x18 18. " LUT50_COL_STS ,LUT50 collision status" "No effect,Clear" bitfld.long 0x18 17. " LUT49_COL_STS ,LUT49 collision status" "No effect,Clear" bitfld.long 0x18 16. " LUT48_COL_STS ,LUT48 collision status" "No effect,Clear" textline " " bitfld.long 0x18 15. " LUT47_COL_STS ,LUT47 collision status" "No effect,Clear" bitfld.long 0x18 14. " LUT46_COL_STS ,LUT46 collision status" "No effect,Clear" bitfld.long 0x18 13. " LUT45_COL_STS ,LUT45 collision status" "No effect,Clear" bitfld.long 0x18 12. " LUT44_COL_STS ,LUT44 collision status" "No effect,Clear" textline " " bitfld.long 0x18 11. " LUT43_COL_STS ,LUT43 collision status" "No effect,Clear" bitfld.long 0x18 10. " LUT42_COL_STS ,LUT42 collision status" "No effect,Clear" bitfld.long 0x18 9. " LUT41_COL_STS ,LUT41 collision status" "No effect,Clear" bitfld.long 0x18 8. " LUT40_COL_STS ,LUT40 collision status" "No effect,Clear" textline " " bitfld.long 0x18 7. " LUT39_COL_STS ,LUT39 collision status" "No effect,Clear" bitfld.long 0x18 6. " LUT38_COL_STS ,LUT38 collision status" "No effect,Clear" bitfld.long 0x18 5. " LUT37_COL_STS ,LUT37 collision status" "No effect,Clear" bitfld.long 0x18 4. " LUT36_COL_STS ,LUT36 collision status" "No effect,Clear" textline " " bitfld.long 0x18 3. " LUT35_COL_STS ,LUT35 collision status" "No effect,Clear" bitfld.long 0x18 2. " LUT34_COL_STS ,LUT34 collision status" "No effect,Clear" bitfld.long 0x18 1. " LUT33_COL_STS ,LUT33 collision status" "No effect,Clear" bitfld.long 0x18 0. " LUT32_COL_STS ,LUT32 collision status" "No effect,Clear" line.long 0x1C "STATUS_COL2_TOG,EPDC LUT Collision Status Toggle" bitfld.long 0x1C 31. " LUT63_COL_STS ,LUT63 collision status" "Not toggled,Toggled" bitfld.long 0x1C 30. " LUT62_COL_STS ,LUT62 collision status" "Not toggled,Toggled" bitfld.long 0x1C 29. " LUT61_COL_STS ,LUT61 collision status" "Not toggled,Toggled" bitfld.long 0x1C 28. " LUT60_COL_STS ,LUT60 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 27. " LUT59_COL_STS ,LUT59 collision status" "Not toggled,Toggled" bitfld.long 0x1C 26. " LUT58_COL_STS ,LUT58 collision status" "Not toggled,Toggled" bitfld.long 0x1C 25. " LUT57_COL_STS ,LUT57 collision status" "Not toggled,Toggled" bitfld.long 0x1C 24. " LUT56_COL_STS ,LUT56 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 23. " LUT55_COL_STS ,LUT55 collision status" "Not toggled,Toggled" bitfld.long 0x1C 22. " LUT54_COL_STS ,LUT54 collision status" "Not toggled,Toggled" bitfld.long 0x1C 21. " LUT53_COL_STS ,LUT53 collision status" "Not toggled,Toggled" bitfld.long 0x1C 20. " LUT52_COL_STS ,LUT52 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 19. " LUT51_COL_STS ,LUT51 collision status" "Not toggled,Toggled" bitfld.long 0x1C 18. " LUT50_COL_STS ,LUT50 collision status" "Not toggled,Toggled" bitfld.long 0x1C 17. " LUT49_COL_STS ,LUT49 collision status" "Not toggled,Toggled" bitfld.long 0x1C 16. " LUT48_COL_STS ,LUT48 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 15. " LUT47_COL_STS ,LUT47 collision status" "Not toggled,Toggled" bitfld.long 0x1C 14. " LUT46_COL_STS ,LUT46 collision status" "Not toggled,Toggled" bitfld.long 0x1C 13. " LUT45_COL_STS ,LUT45 collision status" "Not toggled,Toggled" bitfld.long 0x1C 12. " LUT44_COL_STS ,LUT44 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 11. " LUT43_COL_STS ,LUT43 collision status" "Not toggled,Toggled" bitfld.long 0x1C 10. " LUT42_COL_STS ,LUT42 collision status" "Not toggled,Toggled" bitfld.long 0x1C 9. " LUT41_COL_STS ,LUT41 collision status" "Not toggled,Toggled" bitfld.long 0x1C 8. " LUT40_COL_STS ,LUT40 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 7. " LUT39_COL_STS ,LUT39 collision status" "Not toggled,Toggled" bitfld.long 0x1C 6. " LUT38_COL_STS ,LUT38 collision status" "Not toggled,Toggled" bitfld.long 0x1C 5. " LUT37_COL_STS ,LUT37 collision status" "Not toggled,Toggled" bitfld.long 0x1C 4. " LUT36_COL_STS ,LUT36 collision status" "Not toggled,Toggled" textline " " bitfld.long 0x1C 3. " LUT35_COL_STS ,LUT35 collision status" "Not toggled,Toggled" bitfld.long 0x1C 2. " LUT34_COL_STS ,LUT34 collision status" "Not toggled,Toggled" bitfld.long 0x1C 1. " LUT33_COL_STS ,LUT33 collision status" "Not toggled,Toggled" bitfld.long 0x1C 0. " LUT32_COL_STS ,LUT32 collision status" "Not toggled,Toggled" textline " " group.long 0x4A0++0x0F line.long 0x00 "STATUS,EPDC General Status Register" bitfld.long 0x00 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (Black/white) histogram" "Not contained,Contained" bitfld.long 0x00 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (Single color) histogram" "Not contained,Contained" textline " " bitfld.long 0x00 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (Black/white) histogram" "Not contained,Contained" bitfld.long 0x00 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (Single color) histogram" "Not contained,Contained" textline " " rbitfld.long 0x00 3. " UPD_VOID ,Indicates that the update buffer is void" "Not void,Void" rbitfld.long 0x00 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time" rbitfld.long 0x00 1. " LUTS_BUSY ,Status of luts" "Not busy,Busy" rbitfld.long 0x00 0. " WB_BUSY ,Working buffer process" "Not busy,Busy" line.long 0x04 "STATUS_SET,EPDC General Status Set Register" bitfld.long 0x04 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (Black/white) histogram" "No effect,Set" bitfld.long 0x04 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (Single color) histogram" "No effect,Set" textline " " bitfld.long 0x04 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (Black/white) histogram" "No effect,Set" bitfld.long 0x04 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (Single color) histogram" "No effect,Set" textline " " bitfld.long 0x04 3. " UPD_VOID ,Indicates that the update buffer is void" "No effect,Set" bitfld.long 0x04 2. " LUTS_UNDERRUN ,Status of LUT fill" "No effect,Set" bitfld.long 0x04 1. " LUTS_BUSY ,Status of luts" "No effect,Set" bitfld.long 0x04 0. " WB_BUSY ,Working buffer process" "No effect,Set" line.long 0x08 "STATUS_CLR,EPDC General Status Clear Register" bitfld.long 0x08 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (Black/white) histogram" "No effect,Clear" bitfld.long 0x08 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (Single color) histogram" "No effect,Clear" textline " " bitfld.long 0x08 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (Black/white) histogram" "No effect,Clear" bitfld.long 0x08 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (Single color) histogram" "No effect,Clear" textline " " bitfld.long 0x08 3. " UPD_VOID ,Indicates that the update buffer is void" "No effect,Clear" bitfld.long 0x08 2. " LUTS_UNDERRUN ,Status of LUT fill" "No effect,Clear" bitfld.long 0x08 1. " LUTS_BUSY ,Status of luts" "No effect,Clear" bitfld.long 0x08 0. " WB_BUSY ,Working buffer process" "No effect,Clear" line.long 0x0C "STATUS_TOG,EPDC General Status Toggle Register" bitfld.long 0x0C 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (Black/white) histogram" "No effect,Toggled" bitfld.long 0x0C 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (Single color) histogram" "No effect,Toggled" textline " " bitfld.long 0x0C 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (Black/white) histogram" "No effect,Toggled" bitfld.long 0x0C 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (Single color) histogram" "No effect,Toggled" textline " " bitfld.long 0x0C 3. " UPD_VOID ,Indicates that the update buffer is void" "Not toggled,Toggled" bitfld.long 0x0C 2. " LUTS_UNDERRUN ,Status of LUT fill" "Not toggled,Toggled" bitfld.long 0x0C 1. " LUTS_BUSY ,Status of luts" "Not toggled,Toggled" bitfld.long 0x0C 0. " WB_BUSY ,Working buffer process" "Not toggled,Toggled" rgroup.long 0x4C0++0x03 line.long 0x00 "UPD_COL_CORD,EPDC Collision Region Co-ordinate" hexmask.long.word 0x00 16.--28. 1. " YCORD ,Y co-ordinate for collision region of the latest completed update" hexmask.long.word 0x00 0.--12. 1. " XCORD ,X co-ordinate for collision region of the latest completed update" rgroup.long 0x4E0++0x03 line.long 0x00 "UPD_COL_SIZE,EPDC Collision Region Size" hexmask.long.word 0x00 16.--28. 1. " HEIGHT ,Height (In pixels)" hexmask.long.word 0x00 0.--12. 1. " WIDTH ,Width (In pixels)" textline " " group.long 0x600++0x03 line.long 0x00 "HIST1_PARAM,1-level Histogram Parameter Register" bitfld.long 0x00 0.--4. " VALUE0 ,Value for 1-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x610++0x03 line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register" bitfld.long 0x00 8.--12. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x620++0x03 line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x630++0x03 line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "HIST8_PARAM1,8-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x650++0x03 line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x660++0x03 line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x670++0x03 line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--28. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x680++0x03 line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--28. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " group.long 0x700++0x0F line.long 0x00 "GPIO,EPDC General Purpose I/O Debug Register" rbitfld.long 0x00 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "Low,High" bitfld.long 0x00 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "Low,High" bitfld.long 0x00 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "Low,High" textline " " bitfld.long 0x00 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "Low,High" bitfld.long 0x00 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "Low,High" bitfld.long 0x00 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "Low,High" bitfld.long 0x00 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "Low,High" textline " " bitfld.long 0x00 1. " BDR1 ,IPP_EPDC_BDR[1] output" "Low,High" bitfld.long 0x00 0. " BDR0 ,IPP_EPDC_BDR[0] output" "Low,High" line.long 0x04 "GPIO_SET,EPDC General Purpose I/O Debug Set Register" bitfld.long 0x04 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "No effect,Set" bitfld.long 0x04 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "No effect,Set" bitfld.long 0x04 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "No effect,Set" textline " " bitfld.long 0x04 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "No effect,Set" bitfld.long 0x04 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "No effect,Set" bitfld.long 0x04 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "No effect,Set" bitfld.long 0x04 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "No effect,Set" textline " " bitfld.long 0x04 1. " BDR1 ,IPP_EPDC_BDR[1] output" "No effect,Set" bitfld.long 0x04 0. " BDR0 ,IPP_EPDC_BDR[0] output" "No effect,Set" line.long 0x08 "GPIO_CLR,EPDC General Purpose I/O Debug Clear Register" bitfld.long 0x08 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "No effect,Clear" bitfld.long 0x08 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "No effect,Clear" bitfld.long 0x08 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "No effect,Clear" textline " " bitfld.long 0x08 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "No effect,Clear" bitfld.long 0x08 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "No effect,Clear" bitfld.long 0x08 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "No effect,Clear" bitfld.long 0x08 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "No effect,Clear" textline " " bitfld.long 0x08 1. " BDR1 ,IPP_EPDC_BDR[1] output" "No effect,Clear" bitfld.long 0x08 0. " BDR0 ,IPP_EPDC_BDR[0] output" "No effect,Clear" line.long 0x0C "GPIO_TOG,EPDC General Purpose I/O Debug Toggle Register" bitfld.long 0x0C 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "Not toggled,Toggled" bitfld.long 0x0C 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "Not toggled,Toggled" bitfld.long 0x0C 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "Not toggled,Toggled" textline " " bitfld.long 0x0C 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "Not toggled,Toggled" bitfld.long 0x0C 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "Not toggled,Toggled" bitfld.long 0x0C 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "Not toggled,Toggled" bitfld.long 0x0C 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "Not toggled,Toggled" textline " " bitfld.long 0x0C 1. " BDR1 ,IPP_EPDC_BDR[1] output" "Not toggled,Toggled" bitfld.long 0x0C 0. " BDR0 ,IPP_EPDC_BDR[0] output" "Not toggled,Toggled" group.long 0x7F0++0x03 line.long 0x00 "VERSION,EPDC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" textline " " group.long 0x800++0x03 line.long 0x00 "PIGEON_0_0,Panel Interface Signal Generator Register 0_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x800+0x10)++0x03 line.long 0x00 "PIGEON_0_1,Panel Interface Signal Generator Register 0_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x800+0x20)++0x03 line.long 0x00 "PIGEON_0_2,Panel Interface Signal Generator Register 0_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x840++0x03 line.long 0x00 "PIGEON_1_0,Panel Interface Signal Generator Register 1_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x840+0x10)++0x03 line.long 0x00 "PIGEON_1_1,Panel Interface Signal Generator Register 1_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x840+0x20)++0x03 line.long 0x00 "PIGEON_1_2,Panel Interface Signal Generator Register 1_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x880++0x03 line.long 0x00 "PIGEON_2_0,Panel Interface Signal Generator Register 2_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x880+0x10)++0x03 line.long 0x00 "PIGEON_2_1,Panel Interface Signal Generator Register 2_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x880+0x20)++0x03 line.long 0x00 "PIGEON_2_2,Panel Interface Signal Generator Register 2_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x8C0++0x03 line.long 0x00 "PIGEON_3_0,Panel Interface Signal Generator Register 3_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x8C0+0x10)++0x03 line.long 0x00 "PIGEON_3_1,Panel Interface Signal Generator Register 3_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x8C0+0x20)++0x03 line.long 0x00 "PIGEON_3_2,Panel Interface Signal Generator Register 3_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x900++0x03 line.long 0x00 "PIGEON_4_0,Panel Interface Signal Generator Register 4_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x900+0x10)++0x03 line.long 0x00 "PIGEON_4_1,Panel Interface Signal Generator Register 4_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x900+0x20)++0x03 line.long 0x00 "PIGEON_4_2,Panel Interface Signal Generator Register 4_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x940++0x03 line.long 0x00 "PIGEON_5_0,Panel Interface Signal Generator Register 5_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x940+0x10)++0x03 line.long 0x00 "PIGEON_5_1,Panel Interface Signal Generator Register 5_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x940+0x20)++0x03 line.long 0x00 "PIGEON_5_2,Panel Interface Signal Generator Register 5_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x980++0x03 line.long 0x00 "PIGEON_6_0,Panel Interface Signal Generator Register 6_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x980+0x10)++0x03 line.long 0x00 "PIGEON_6_1,Panel Interface Signal Generator Register 6_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x980+0x20)++0x03 line.long 0x00 "PIGEON_6_2,Panel Interface Signal Generator Register 6_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0x9C0++0x03 line.long 0x00 "PIGEON_7_0,Panel Interface Signal Generator Register 7_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x9C0+0x10)++0x03 line.long 0x00 "PIGEON_7_1,Panel Interface Signal Generator Register 7_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x9C0+0x20)++0x03 line.long 0x00 "PIGEON_7_2,Panel Interface Signal Generator Register 7_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xA00++0x03 line.long 0x00 "PIGEON_8_0,Panel Interface Signal Generator Register 8_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA00+0x10)++0x03 line.long 0x00 "PIGEON_8_1,Panel Interface Signal Generator Register 8_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA00+0x20)++0x03 line.long 0x00 "PIGEON_8_2,Panel Interface Signal Generator Register 8_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xA40++0x03 line.long 0x00 "PIGEON_9_0,Panel Interface Signal Generator Register 9_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA40+0x10)++0x03 line.long 0x00 "PIGEON_9_1,Panel Interface Signal Generator Register 9_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA40+0x20)++0x03 line.long 0x00 "PIGEON_9_2,Panel Interface Signal Generator Register 9_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xA80++0x03 line.long 0x00 "PIGEON_10_0,Panel Interface Signal Generator Register 10_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA80+0x10)++0x03 line.long 0x00 "PIGEON_10_1,Panel Interface Signal Generator Register 10_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA80+0x20)++0x03 line.long 0x00 "PIGEON_10_2,Panel Interface Signal Generator Register 10_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xAC0++0x03 line.long 0x00 "PIGEON_11_0,Panel Interface Signal Generator Register 11_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xAC0+0x10)++0x03 line.long 0x00 "PIGEON_11_1,Panel Interface Signal Generator Register 11_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xAC0+0x20)++0x03 line.long 0x00 "PIGEON_11_2,Panel Interface Signal Generator Register 11_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xB00++0x03 line.long 0x00 "PIGEON_12_0,Panel Interface Signal Generator Register 12_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB00+0x10)++0x03 line.long 0x00 "PIGEON_12_1,Panel Interface Signal Generator Register 12_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB00+0x20)++0x03 line.long 0x00 "PIGEON_12_2,Panel Interface Signal Generator Register 12_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xB40++0x03 line.long 0x00 "PIGEON_13_0,Panel Interface Signal Generator Register 13_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB40+0x10)++0x03 line.long 0x00 "PIGEON_13_1,Panel Interface Signal Generator Register 13_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB40+0x20)++0x03 line.long 0x00 "PIGEON_13_2,Panel Interface Signal Generator Register 13_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xB80++0x03 line.long 0x00 "PIGEON_14_0,Panel Interface Signal Generator Register 14_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB80+0x10)++0x03 line.long 0x00 "PIGEON_14_1,Panel Interface Signal Generator Register 14_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB80+0x20)++0x03 line.long 0x00 "PIGEON_14_2,Panel Interface Signal Generator Register 14_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xBC0++0x03 line.long 0x00 "PIGEON_15_0,Panel Interface Signal Generator Register 15_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xBC0+0x10)++0x03 line.long 0x00 "PIGEON_15_1,Panel Interface Signal Generator Register 15_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xBC0+0x20)++0x03 line.long 0x00 "PIGEON_15_2,Panel Interface Signal Generator Register 15_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." textline " " group.long 0xC00++0x03 line.long 0x00 "PIGEON_16_0,Panel Interface Signal Generator Register 16_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " INC_SEL ,Event to incrment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xC00+0x10)++0x03 line.long 0x00 "PIGEON_16_1,Panel Interface Signal Generator Register 16_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xC00+0x20)++0x03 line.long 0x00 "PIGEON_16_2,Panel Interface Signal Generator Register 16_1" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." width 0x0B tree.end endif tree "PXP (Pixel Pipeline)" base ad:0x30700000 width 25. group.long 0x00++0x33 line.long 0x00 "CTRL,Control Register 0" bitfld.long 0x00 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated" bitfld.long 0x00 28. " EN_REPEAT ,Enable the PXP to run continuously" "Disabled,Enabled" newline bitfld.long 0x00 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process" "8x8,16x16" bitfld.long 0x00 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP primary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 15. " VFLIP1 ,Input buffer flipped vertically" "No,Yes" newline bitfld.long 0x00 14. " HFLIP1 ,Input buffer flipped horizontally" "No,Yes" bitfld.long 0x00 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 11. " VFLIP0 ,Output buffer flipped vertically" "No,Yes" newline bitfld.long 0x00 10. " HFLIP0 ,Output buffer flipped horizontally" "No,Yes" bitfld.long 0x00 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "Disabled,Enabled" newline bitfld.long 0x00 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "Disabled,Enabled" bitfld.long 0x00 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " IRQ_ENABLE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enables PXP operation with specified parameters" "Disabled,Enabled" line.long 0x04 "CTRL_SET,Control Register 0" bitfld.long 0x04 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Set" newline bitfld.long 0x04 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Set" bitfld.long 0x04 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Set" newline bitfld.long 0x04 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Set" bitfld.long 0x04 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Set" newline bitfld.long 0x04 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Set" bitfld.long 0x04 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "No effect,Set" newline bitfld.long 0x04 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "No effect,Set" bitfld.long 0x04 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "No effect,Set" bitfld.long 0x04 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Set" newline bitfld.long 0x04 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Set" bitfld.long 0x04 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Set" line.long 0x08 "CTRL_CLR,Control Register 0" bitfld.long 0x08 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Clear" newline bitfld.long 0x08 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Clear" bitfld.long 0x08 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Clear" newline bitfld.long 0x08 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Clear" bitfld.long 0x08 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Clear" newline bitfld.long 0x08 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Clear" bitfld.long 0x08 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "No effect,Clear" newline bitfld.long 0x08 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "No effect,Clear" bitfld.long 0x08 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "No effect,Clear" bitfld.long 0x08 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Clear" newline bitfld.long 0x08 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Clear" line.long 0x0C "CTRL_TOG,Control Register 0" bitfld.long 0x0C 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "Not toggled,Toggled" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled" bitfld.long 0x0C 28. " EN_REPEAT ,Enable the PXP to run continuously" "Not toggled,Toggled" newline bitfld.long 0x0C 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process" "Not toggled,Toggled" bitfld.long 0x0C 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 15. " VFLIP1 ,Input buffer flipped vertically" "Not toggled,Toggled" newline bitfld.long 0x0C 14. " HFLIP1 ,Input buffer flipped horizontally" "Not toggled,Toggled" bitfld.long 0x0C 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 11. " VFLIP0 ,Output buffer flipped vertically" "Not toggled,Toggled" newline bitfld.long 0x0C 10. " HFLIP0 ,Output buffer flipped horizontally" "Not toggled,Toggled" bitfld.long 0x0C 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "Not toggled,Toggled" bitfld.long 0x0C 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " IRQ_ENABLE ,Interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 0. " ENABLE ,Enables PXP operation with specified parameters" "Not toggled,Toggled" line.long 0x10 "STAT,Status Register" hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" bitfld.long 0x10 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No error,Error" bitfld.long 0x10 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No error,Error" bitfld.long 0x10 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "Not completed,Completed" newline bitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 3. " NEXT_IRQ ,Next command issue" "Not issued,Issued" bitfld.long 0x10 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No error,Error" newline bitfld.long 0x10 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No error,Error" bitfld.long 0x10 0. " IRQ0 ,Indicates current PXP interrupt status" "No interrupt,Interrupt" line.long 0x14 "STAT_SET,Status Register" hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" bitfld.long 0x14 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Set" bitfld.long 0x14 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Set" bitfld.long 0x14 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "No effect,Set" newline bitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 3. " NEXT_IRQ ,Next command issue" "No effect,Set" bitfld.long 0x14 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Set" newline bitfld.long 0x14 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Set" bitfld.long 0x14 0. " IRQ0 ,Indicates current PXP interrupt status" "No effect,Set" line.long 0x18 "STAT_CLR,Status Register" hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" bitfld.long 0x18 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "No effect,Clear" newline bitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 3. " NEXT_IRQ ,Next command issue" "No effect,Clear" bitfld.long 0x18 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" newline bitfld.long 0x18 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 0. " IRQ0 ,Indicates current PXP interrupt status" "No effect,Clear" line.long 0x1C "STAT_TOG,Status Register" hexmask.long.byte 0x1C 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x1C 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" bitfld.long 0x1C 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "Not toggled,Toggled" newline bitfld.long 0x1C 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 3. " NEXT_IRQ ,Next command issue" "Not toggled,Toggled" bitfld.long 0x1C 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 0. " IRQ0 ,Indicates current PXP interrupt status" "Not toggled,Toggled" line.long 0x20 "OUT_CTRL,Output Buffer Control Register" hexmask.long.byte 0x20 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x20 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwrited" newline bitfld.long 0x20 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x20 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x24 "OUT_CTRL_SET,Output Buffer Control Set Register" hexmask.long.byte 0x24 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x24 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "No effect,Set" newline bitfld.long 0x24 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x24 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x28 "OUT_CTRL_CLR,Output Buffer Control Clear Register" hexmask.long.byte 0x28 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x28 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "No effect,Clear" newline bitfld.long 0x28 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x28 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x2C "OUT_CTRL_TOG,Output Buffer Control Toggle Register" hexmask.long.byte 0x2C 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x2C 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Not toggled,Toggled" newline bitfld.long 0x2C 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x2C 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x30 "OUT_BUF,Output Frame Buffer Pointer" group.long 0x40++0x03 line.long 0x00 "OUT_BUF2,Output Frame Buffer Pointer 2" newline group.long 0x50++0x03 line.long 0x00 "OUT_PITCH,Output Buffer Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x60++0x03 line.long 0x00 "OUT_LRC,Output Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Number of horizontal PIXELS in the output surface (Non-rotated)" hexmask.long.word 0x00 0.--13. 1. " Y ,Number of vertical PIXELS in the output surface (Non-rotated)" group.long 0x70++0x03 line.long 0x00 "OUT_PS_ULC,Processed Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (In pixels) of PS in the output buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (In pixels) of PS in the output buffer" group.long 0x80++0x03 line.long 0x00 "OUT_PS_LRC,Processed Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (In pixels) of PS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (In pixels) of PS in the output frame buffer" group.long 0x90++0x03 line.long 0x00 "OUT_AS_ULC,Alpha Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (In pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (In pixels) of AS in the output frame buffer" group.long 0xA0++0x03 line.long 0x00 "OUT_AS_LRC,Alpha Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (In pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (In pixels) of AS in the output frame buffer" group.long 0xB0++0x13 line.long 0x00 "PS_CTRL,Processed Surface (Ps) Control Register" bitfld.long 0x00 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x00 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x00 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x00 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x04 "PS_CTRL_SET,Processed Surface (Ps) Control Set Register" bitfld.long 0x04 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x04 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x04 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x04 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x08 "PS_CTRL_CLR,Processed Surface (Ps) Control Clear Register" bitfld.long 0x08 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x08 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x08 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x08 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x0C "PS_CTRL_TOG,Processed Surface (Ps) Control Toggle Register" bitfld.long 0x0C 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x0C 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x0C 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x0C 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x10 "PS_BUF,PS Input Buffer Address" group.long 0xD0++0x03 line.long 0x00 "PS_UBUF,PS U/cb Or 2 Plane UV Input Buffer Address" group.long 0xE0++0x03 line.long 0x00 "PS_VBUF,PS V/cr Input Buffer Address" group.long 0xF0++0x03 line.long 0x00 "PS_PITCH,Processed Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x100++0x03 line.long 0x00 "PS_BACKGROUND_0,PS Background Color" hexmask.long.tbyte 0x00 0.--23. 1. " COLOR ,Background color (In 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC" group.long 0x110++0x03 line.long 0x00 "PS_SCALE,PS Scale Factor Register" hexmask.long.word 0x00 16.--30. 1. " YSCALE ,Two bit integer and 12 bit fractional representation of the Y scaling factor for the PS source buffer" hexmask.long.word 0x00 0.--14. 1. " XSCALE ,Two bit integer and 12 bit fractional representation of the X scaling factor for the PS source buffer" group.long 0x120++0x03 line.long 0x00 "PS_OFFSET,PS Scale Offset Register" hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,12 bit fractional representation of the Y scaling offset" hexmask.long.word 0x00 0.--11. 1. " XOFFSET ,12 bit fractional representation of the X scaling offset" group.long 0x130++0x03 line.long 0x00 "PS_CLRKEYLOW_0,PS Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of color key applied to PS buffer" group.long 0x140++0x03 line.long 0x00 "PS_CLRKEYHIGH_0,PS Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of color key applied to PS buffer" group.long 0x150++0x03 line.long 0x00 "AS_CTRL,Alpha Surface Control" bitfld.long 0x00 21. " ALPHA1_INVERT ,Invert the alpha value and apply (1- alpha) for image composition" "Not inverted,Inverted" bitfld.long 0x00 20. " ALPHA0_INVERT ,Invert the alpha value and apply (1- alpha) for image composition" "Not inverted,Inverted" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" newline bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for AS" "ARGB8888,RGBA8888,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Methods of construction of alpha value" "Embedded,Override,Multiply,Rops" group.long 0x160++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer" group.long 0x170++0x03 line.long 0x00 "AS_PITCH,Alpha Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x180++0x03 line.long 0x00 "AS_CLRKEYLOW_0,Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x190++0x03 line.long 0x00 "AS_CLRKEYHIGH_0,Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x1A0++0x03 line.long 0x00 "CSC1_COEF0,Color Space Conversion Coefficient Register 0" bitfld.long 0x00 31. " YCBCR_MODE ,Conversion data type" "YUV to RGB,Ycbcr to RGB" bitfld.long 0x00 30. " BYPASS ,Bypass the CSC unit in the scaling engine" "Not bypassed,Bypassed" hexmask.long.word 0x00 18.--28. 1. " C0 ,Two's compliment Y multiplier coefficient" hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Two's compliment phase offset implicit for cbcr data" newline hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's compliment amplitude offset implicit in the Y data" group.long 0x1B0++0x03 line.long 0x00 "CSC1_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " C1 ,Two's compliment red v/cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C4 ,Two's compliment blue u/cb multiplier coefficient" group.long 0x1C0++0x03 line.long 0x00 "CSC1_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement green v/cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement green u/cb multiplier coefficient" group.long 0x1D0++0x03 line.long 0x00 "CSC2_CTRL,Color Space Conversion Control Register" bitfld.long 0x00 1.--2. " CSC_MODE ,Methods of CSC unit operates on pixels when the CSC is not bypassed (Converted from)" "YUV to RGB,Ycbcr to RGB,RGB to YUV,RGB to ycbcr" bitfld.long 0x00 0. " BYPASS ,Bypass CSC2 unit" "Not bypassed,Bypassed" group.long 0x1E0++0x03 line.long 0x00 "CSC2_COEF0,Color Space Conversion Coefficient Register 0" hexmask.long.word 0x00 16.--26. 1. " A2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A1 ,Two's complement coefficient offset" group.long 0x1F0++0x03 line.long 0x00 "CSC2_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " B1 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A3 ,Two's complement coefficient offset" group.long 0x200++0x03 line.long 0x00 "CSC2_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " B3 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " B2 ,Two's complement coefficient offset" group.long 0x210++0x03 line.long 0x00 "CSC2_COEF3,Color Space Conversion Coefficient Register 3" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " C1 ,Two's complement coefficient offset" group.long 0x220++0x03 line.long 0x00 "CSC2_COEF4,Color Space Conversion Coefficient Register 4" hexmask.long.word 0x00 16.--26. 1. " D1 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement coefficient offset" group.long 0x230++0x03 line.long 0x00 "CSC2_COEF5,Color Space Conversion Coefficient Register 5" hexmask.long.word 0x00 16.--24. 1. " D3 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--8. 1. " D2 ,Two's complement D1 coefficient integer offset to be added" group.long 0x240++0x03 line.long 0x00 "LUT_CTRL,Lookup Table Control Register" bitfld.long 0x00 31. " BYPASS ,Bypass the LUT memory resource completely" "Not bypassed,Bypassed" bitfld.long 0x00 24.--25. " LOOKUP_MODE ,Configure the input address for the 16KB" "CACHE_RGB565,DIRECT_Y8,DIRECT_RGB444,DIRECT_RGB454" bitfld.long 0x00 16.--17. " OUT_MODE ,Select the output mode of operation for the LUT resource" ",Y8,RGBW4444CFA,RGB888" bitfld.long 0x00 10. " SEL_8KB ,Selects which 8KB bank of memory to use for direct 12bpp lookup modes" "First,Second" newline bitfld.long 0x00 9. " LRU_UPD ,Least recently used policy update control" "All hits,Hit after miss" bitfld.long 0x00 8. " INVALID ,Invalidate the cache LRU and valid bits" "Invalid,Valid" bitfld.long 0x00 0. " DMA_START ,Load the PXP LUT memory based on PXP_LUT_ADDR_NUM_BYTES, PXP_LUT_ADDR_ADDR, and PXP_LUT_MEM_ADDR" "Not loaded,Loaded" group.long 0x250++0x03 line.long 0x00 "LUT_ADDR,Lookup Table Control Register" hexmask.long.word 0x00 16.--30. 1. " NUM_BYTES ,Number of bytes to load via a DMA operation" hexmask.long.word 0x00 0.--13. 1. " ADDR ,LUT indexed address pointer" group.long 0x260++0x03 line.long 0x00 "LUT_DATA,Lookup Table Data Register" group.long 0x270++0x03 line.long 0x00 "LUT_EXTMEM,Lookup Table External Memory Address Register" group.long 0x280++0x03 line.long 0x00 "CFA,Color Filter Array Register" group.long 0x290++0x03 line.long 0x00 "ALPHA_A_CTRL,PXP Alpha Engine A Control Register" hexmask.long.byte 0x00 24.--31. 1. " S1_GLOBAL_ALPHA ,S1 global alpha" hexmask.long.byte 0x00 16.--23. 1. " S0_GLOBAL_ALPHA ,S0 global alpha" bitfld.long 0x00 13. " S1_COLOR_MODE ,S1 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 12. " S1_ALPHA_MODE ,S1 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 10.--11. " S1_GLOBAL_ALPHA_MODE ,S1 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 8.--9. " S1_S0_FACTOR_MODE ,S1 to s0 factor mode" "1,0,Straight,Inversed" bitfld.long 0x00 6. " S0_COLOR_MODE ,S0 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 5. " S0_ALPHA_MODE ,S0 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 3.--4. " S0_GLOBAL_ALPHA_MODE ,S0 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 1.--2. " S0_S1_FACTOR_MODE ,S0 to s1 factor mode" "1,0,Straight,Inversed" bitfld.long 0x00 0. " POTER_DUFF_ENABLE ,Porter duff enable" "Disabled,Enabled" group.long 0x2A0++0x03 line.long 0x00 "ALPHA_B_CTRL,PXP Alpha Engine B Control Register" hexmask.long.byte 0x00 24.--31. 1. " S1_GLOBAL_ALPHA ,S1 global alpha" hexmask.long.byte 0x00 16.--23. 1. " S0_GLOBAL_ALPHA ,S0 global alpha" bitfld.long 0x00 13. " S1_COLOR_MODE ,S1 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 12. " S1_ALPHA_MODE ,S1 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 10.--11. " S1_GLOBAL_ALPHA_MODE ,S1 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 8.--9. " S1_S0_FACTOR_MODE ,S1 to s0 factor mode" "1,0,Straight,Inversed" bitfld.long 0x00 6. " S0_COLOR_MODE ,S0 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 5. " S0_ALPHA_MODE ,S0 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 3.--4. " S0_GLOBAL_ALPHA_MODE ,S0 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 1.--2. " S0_S1_FACTOR_MODE ,S0 to s1 factor mode" "1,0,Straight,Inversed" bitfld.long 0x00 0. " POTER_DUFF_ENABLE ,Porter duff enable" "Disabled,Enabled" group.long 0x2B0++0x03 line.long 0x00 "ALPHA_B_CTRL_1,ALPHA_B_CTRL_1" bitfld.long 0x00 4.--7. " ROP ,Indicates a raster operation to perform when enabled" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." bitfld.long 0x00 1. " OL_CLRKEY_ENABLE ,Indicates that colorkey functionality is enabled for this alpha surface" "Disabled,Enabled" bitfld.long 0x00 0. " ROP_ENABLE ,ROP ENABLE" "Disabled,Enabled" group.long 0x2C0++0x03 line.long 0x00 "PS_BACKGROUND_1,PS Background Color 1" hexmask.long.tbyte 0x00 0.--23. 1. " COLOR ,Background color (In 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC" group.long 0x2D0++0x03 line.long 0x00 "PS_CLRKEYLOW_1,PS Color Key Low 1" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of color key applied to PS buffer" group.long 0x2E0++0x03 line.long 0x00 "PS_CLRKEYHIGH_1,PS Color Key High 1" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of color key applied to PS buffer" group.long 0x2F0++0x03 line.long 0x00 "AS_CLRKEYLOW_1,Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x300++0x03 line.long 0x00 "AS_CLRKEYHIGH_1,Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" newline group.long 0x310++0x13 line.long 0x00 "CTRL2,Control Register 2" bitfld.long 0x00 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "8x8,16x16" bitfld.long 0x00 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP secondary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 15. " VFLIP1 ,Input buffer flipped vertically" "No,Yes" bitfld.long 0x00 14. " HFLIP1 ,Input buffer flipped horizontally" "No,Yes" newline bitfld.long 0x00 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 11. " VFLIP0 ,Output buffer flipped vertically" "No,Yes" bitfld.long 0x00 10. " HFLIP0 ,Output buffer flipped horizontally" "No,Yes" newline bitfld.long 0x00 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "Disabled,Enabled" line.long 0x04 "CTRL2_SET,Control Register 2" bitfld.long 0x04 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "No effect,Set" bitfld.long 0x04 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Set" bitfld.long 0x04 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Set" newline bitfld.long 0x04 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Set" bitfld.long 0x04 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Set" newline bitfld.long 0x04 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "No effect,Set" line.long 0x08 "CTRL2_CLR,Control Register 2" bitfld.long 0x08 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "No effect,Clear" bitfld.long 0x08 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Clear" bitfld.long 0x08 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Clear" newline bitfld.long 0x08 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Clear" bitfld.long 0x08 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Clear" newline bitfld.long 0x08 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "No effect,Clear" line.long 0x0C "CTRL2_TOG,Control Register 2" bitfld.long 0x0C 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "Not toggled,Toggled" bitfld.long 0x0C 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 20. " ENABLE_INPUT_FETCH_STORE ,Enable the input fetch and store engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 15. " VFLIP1 ,Input buffer flipped vertically" "Not toggled,Toggled" bitfld.long 0x0C 14. " HFLIP1 ,Input buffer flipped horizontally" "Not toggled,Toggled" newline bitfld.long 0x0C 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 11. " VFLIP0 ,Output buffer flipped vertically" "Not toggled,Toggled" bitfld.long 0x0C 10. " HFLIP0 ,Output buffer flipped horizontally" "Not toggled,Toggled" newline bitfld.long 0x0C 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "Not toggled,Toggled" line.long 0x10 "POWER_REG0,PXP Power Control Register" hexmask.long.tbyte 0x10 12.--31. 1. " CTRL ,This register contains power control for the PXP" bitfld.long 0x10 9.--11. " ROT0_MEM_LP_STATE ,Selects the low power state of the ROT 0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x10 6.--8. " LUT_LP_STATE_WAY1_BANKN ,Selects the low power state of the lut's WAY1-BANK0,1,2,3 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x10 3.--5. " LUT_LP_STATE_WAY0_BANKN ,Selects the low power state of the lut's WAY0-BANK1,2,3 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x10 0.--2. " LUT_LP_STATE_WAY0_BANK0 ,Selects the low power state of the lut's WAY0-BANK0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." group.long 0x330++0x03 line.long 0x00 "POWER_REG1,PXP Power Control Register 1" bitfld.long 0x00 21.--23. " ALU_B_MEM_LP_STATE ,Selects the low power state of the ALU B memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 18.--20. " ALU_A_MEM_LP_STATE ,Selects the low power state of the ALU A memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 15.--17. " DITH2_LUT_MEM_LP_STATE ,Selects the low power state of the dither2 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x00 12.--14. " DITH1_LUT_MEM_LP_STATE ,Selects the low power state of the dither1 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 9.--11. " DITH0_ERR1_MEM_LP_STATE ,Selects the low power state of the dither0 ERR1 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 6.--8. " DITH0_ERR0_MEM_LP_STATE ,Selects the low power state of the dither0 ERR0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x00 3.--5. " DITH0_LUT_MEM_LP_STATE ,Selects the low power state of the dither0 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 0.--2. " ROT1_MEM_LP_STATE ,Selects the low power state of the ROT 1 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline group.long 0x350++0x23 line.long 0x00 "DATA_PATH_CTRL1,DATA_PATH_CTRL1" bitfld.long 0x00 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x00 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x04 "DATA_PATH_CTRL1_SET,DATA_PATH_CTRL1_SET" bitfld.long 0x04 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x04 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x08 "DATA_PATH_CTRL1_CLR,DATA_PATH_CTRL1_CLR" bitfld.long 0x08 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x08 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x0C "DATA_PATH_CTRL1_TOG,DATA_PATH_CTRL1_TOG" bitfld.long 0x0C 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" newline line.long 0x10 "INIT_MEM_CTRL,Initialize Memory Buffer Control Register" bitfld.long 0x10 31. " START ,Enables writing to the memory" "Disabled,Enabled" bitfld.long 0x10 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x10 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x14 "INIT_MEM_CTRL_SET,Initialize Memory Buffer Control Register" bitfld.long 0x14 31. " START ,Enables writing to the memory" "No effect,Set" bitfld.long 0x14 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x14 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x18 "INIT_MEM_CTRL_CLR,Initialize Memory Buffer Control Register" bitfld.long 0x18 31. " START ,Enables writing to the memory" "No effect,Clear" bitfld.long 0x18 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x18 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x1C "INIT_MEM_CTRL_TOG,Initialize Memory Buffer Control Register" bitfld.long 0x1C 31. " START ,Enables writing to the memory" "Not toggled,Toggled" bitfld.long 0x1C 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x1C 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x20 "INIT_MEM_DATA,Write Data Register" group.long 0x380++0x03 line.long 0x00 "INIT_MEM_DATA_HIGH,Write Data Register" group.long 0x390++0x1F line.long 0x00 "PXP_IRQ_MAS,PXP IRQ Mask Register" bitfld.long 0x00 31. " COMPRESS_DONE_IRQ_EN ,Enables compression done interrupt detection" "Disabled,Enabled" bitfld.long 0x00 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 14. " WFE_A_STORE_IRQ_EN ,Enables WFE A store engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 13. " DITHER_STORE_IRQ_EN ,Enables dither store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 12. " FIRST_STORE_IRQ_EN ,Enables first store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 9. " WFE_A_CH1_STORE_IRQ_EN ,Enables WFE A ch1 store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 8. " WFE_A_CH0_STORE_IRQ_EN ,Enables WFE A ch0 store engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 7. " DITHER_CH1_STORE_IRQ_EN ,Enables dither ch1 store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 6. " DITHER_CH0_STORE_IRQ_EN ,Enables dither ch0 store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 5. " DITHER_CH1_PREFETCH_IRQ_EN ,Enables dither ch1 prefetch engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 4. " DITHER_CH0_PREFETCH_IRQ_EN ,Enables dither ch0 prefetch engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 3. " FIRST_CH1_STORE_IRQ_EN ,Enables first ch1 store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 2. " FIRST_CH0_STORE_IRQ_EN ,Enables first ch0 store engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 1. " FIRST_CH1_PREFETCH_IRQ_EN ,Enables first ch1 prefetch engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 0. " FIRST_CH0_PREFETCH_IRQ_EN ,Enables first ch0 prefetch engine interrupt detection" "Disabled,Enabled" line.long 0x04 "PXP_IRQ_MAS_SET,PXP IRQ Mask Register" bitfld.long 0x04 31. " COMPRESS_DONE_IRQ_EN ,Enables compression done interrupt detection" "No effect,Set" bitfld.long 0x04 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "No effect,Set" bitfld.long 0x04 14. " WFE_A_STORE_IRQ_EN ,Enables WFE A store engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 13. " DITHER_STORE_IRQ_EN ,Enables dither store engine interrupt detection" "No effect,Set" bitfld.long 0x04 12. " FIRST_STORE_IRQ_EN ,Enables first store engine interrupt detection" "No effect,Set" bitfld.long 0x04 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "No effect,Set" bitfld.long 0x04 9. " WFE_A_CH1_STORE_IRQ_EN ,Enables WFE A ch1 store engine interrupt detection" "No effect,Set" bitfld.long 0x04 8. " WFE_A_CH0_STORE_IRQ_EN ,Enables WFE A ch0 store engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 7. " DITHER_CH1_STORE_IRQ_EN ,Enables dither ch1 store engine interrupt detection" "No effect,Set" bitfld.long 0x04 6. " DITHER_CH0_STORE_IRQ_EN ,Enables dither ch0 store engine interrupt detection" "No effect,Set" bitfld.long 0x04 5. " DITHER_CH1_PREFETCH_IRQ_EN ,Enables dither ch1 prefetch engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 4. " DITHER_CH0_PREFETCH_IRQ_EN ,Enables dither ch0 prefetch engine interrupt detection" "No effect,Set" bitfld.long 0x04 3. " FIRST_CH1_STORE_IRQ_EN ,Enables first ch1 store engine interrupt detection" "No effect,Set" bitfld.long 0x04 2. " FIRST_CH0_STORE_IRQ_EN ,Enables first ch0 store engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 1. " FIRST_CH1_PREFETCH_IRQ_EN ,Enables first ch1 prefetch engine interrupt detection" "No effect,Set" bitfld.long 0x04 0. " FIRST_CH0_PREFETCH_IRQ_EN ,Enables first ch0 prefetch engine interrupt detection" "No effect,Set" line.long 0x08 "PXP_IRQ_MAS_CLR,PXP IRQ Mask Register" bitfld.long 0x08 31. " COMPRESS_DONE_IRQ_EN ,Enables compression done interrupt detection" "No effect,Clear" bitfld.long 0x08 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 14. " WFE_A_STORE_IRQ_EN ,Enables WFE A store engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 13. " DITHER_STORE_IRQ_EN ,Enables dither store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 12. " FIRST_STORE_IRQ_EN ,Enables first store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 9. " WFE_A_CH1_STORE_IRQ_EN ,Enables WFE A ch1 store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 8. " WFE_A_CH0_STORE_IRQ_EN ,Enables WFE A ch0 store engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 7. " DITHER_CH1_STORE_IRQ_EN ,Enables dither ch1 store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 6. " DITHER_CH0_STORE_IRQ_EN ,Enables dither ch0 store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 5. " DITHER_CH1_PREFETCH_IRQ_EN ,Enables dither ch1 prefetch engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 4. " DITHER_CH0_PREFETCH_IRQ_EN ,Enables dither ch0 prefetch engine interrupt detection" "No effect,Clear" bitfld.long 0x08 3. " FIRST_CH1_STORE_IRQ_EN ,Enables first ch1 store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 2. " FIRST_CH0_STORE_IRQ_EN ,Enables first ch0 store engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 1. " FIRST_CH1_PREFETCH_IRQ_EN ,Enables first ch1 prefetch engine interrupt detection" "No effect,Clear" bitfld.long 0x08 0. " FIRST_CH0_PREFETCH_IRQ_EN ,Enables first ch0 prefetch engine interrupt detection" "No effect,Clear" line.long 0x0C "PXP_IRQ_MAS_TOG,PXP IRQ Mask Register" bitfld.long 0x0C 31. " COMPRESS_DONE_IRQ_EN ,Enables compression done interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 14. " WFE_A_STORE_IRQ_EN ,Enables WFE A store engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 13. " DITHER_STORE_IRQ_EN ,Enables dither store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 12. " FIRST_STORE_IRQ_EN ,Enables first store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 9. " WFE_A_CH1_STORE_IRQ_EN ,Enables WFE A ch1 store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 8. " WFE_A_CH0_STORE_IRQ_EN ,Enables WFE A ch0 store engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " DITHER_CH1_STORE_IRQ_EN ,Enables dither ch1 store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 6. " DITHER_CH0_STORE_IRQ_EN ,Enables dither ch0 store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 5. " DITHER_CH1_PREFETCH_IRQ_EN ,Enables dither ch1 prefetch engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " DITHER_CH0_PREFETCH_IRQ_EN ,Enables dither ch0 prefetch engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 3. " FIRST_CH1_STORE_IRQ_EN ,Enables first ch1 store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 2. " FIRST_CH0_STORE_IRQ_EN ,Enables first ch0 store engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " FIRST_CH1_PREFETCH_IRQ_EN ,Enables first ch1 prefetch engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 0. " FIRST_CH0_PREFETCH_IRQ_EN ,Enables first ch0 prefetch engine interrupt detection" "Not toggled,Toggled" line.long 0x10 "HW_PXP_IRQ,HW_PXP_IRQ" bitfld.long 0x10 31. " COMPRESS_DONE_IRQ ,Compression done interrupt" "No interrupt,Interrupt" bitfld.long 0x10 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 14. " WFE_A_STORE_IRQ ,WFE A store engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 13. " DITHER_STORE_IRQ ,Dither store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 12. " FIRST_STORE_IRQ ,Initial store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 9. " WFE_A_CH1_STORE_IRQ ,WFE A ch1 store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 8. " WFE_A_CH0_STORE_IRQ ,WFE A ch0 store engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 7. " DITHER_CH1_STORE_IRQ ,Dither ch1 store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 6. " DITHER_CH0_STORE_IRQ ,Dither ch0 store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 5. " DITHER_CH1_PREFETCH_IRQ ,Dither ch1 prefetch engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 4. " DITHER_CH0_PREFETCH_IRQ ,Dither ch0 prefetch engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 3. " FIRST_CH1_STORE_IRQ ,Initial ch1 store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 2. " FIRST_CH0_STORE_IRQ ,Initial ch0 store engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 1. " FIRST_CH1_PREFETCH_IRQ ,Initial ch1 prefetch engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 0. " FIRST_CH0_PREFETCH_IRQ ,Initial ch0 prefetch engine interrupt" "No interrupt,Interrupt" line.long 0x14 "HW_PXP_IRQ_SET,HW_PXP_IRQ_SET" bitfld.long 0x14 31. " COMPRESS_DONE_IRQ ,Compression done interrupt" "No effect,Set" bitfld.long 0x14 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No effect,Set" bitfld.long 0x14 14. " WFE_A_STORE_IRQ ,WFE A store engine interrupt" "No effect,Set" newline bitfld.long 0x14 13. " DITHER_STORE_IRQ ,Dither store engine interrupt" "No effect,Set" bitfld.long 0x14 12. " FIRST_STORE_IRQ ,Initial store engine interrupt" "No effect,Set" bitfld.long 0x14 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No effect,Set" newline bitfld.long 0x14 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No effect,Set" bitfld.long 0x14 9. " WFE_A_CH1_STORE_IRQ ,WFE A ch1 store engine interrupt" "No effect,Set" bitfld.long 0x14 8. " WFE_A_CH0_STORE_IRQ ,WFE A ch0 store engine interrupt" "No effect,Set" newline bitfld.long 0x14 7. " DITHER_CH1_STORE_IRQ ,Dither ch1 store engine interrupt" "No effect,Set" bitfld.long 0x14 6. " DITHER_CH0_STORE_IRQ ,Dither ch0 store engine interrupt" "No effect,Set" bitfld.long 0x14 5. " DITHER_CH1_PREFETCH_IRQ ,Dither ch1 prefetch engine interrupt" "No effect,Set" newline bitfld.long 0x14 4. " DITHER_CH0_PREFETCH_IRQ ,Dither ch0 prefetch engine interrupt" "No effect,Set" bitfld.long 0x14 3. " FIRST_CH1_STORE_IRQ ,Initial ch1 store engine interrupt" "No effect,Set" bitfld.long 0x14 2. " FIRST_CH0_STORE_IRQ ,Initial ch0 store engine interrupt" "No effect,Set" newline bitfld.long 0x14 1. " FIRST_CH1_PREFETCH_IRQ ,Initial ch1 prefetch engine interrupt" "No effect,Set" bitfld.long 0x14 0. " FIRST_CH0_PREFETCH_IRQ ,Initial ch0 prefetch engine interrupt" "No effect,Set" line.long 0x18 "HW_PXP_IRQ_CLR,HW_PXP_IRQ_CLR" bitfld.long 0x18 31. " COMPRESS_DONE_IRQ ,Compression done interrupt" "No effect,Clear" bitfld.long 0x18 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No effect,Clear" bitfld.long 0x18 14. " WFE_A_STORE_IRQ ,WFE A store engine interrupt" "No effect,Clear" newline bitfld.long 0x18 13. " DITHER_STORE_IRQ ,Dither store engine interrupt" "No effect,Clear" bitfld.long 0x18 12. " FIRST_STORE_IRQ ,Initial store engine interrupt" "No effect,Clear" bitfld.long 0x18 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No effect,Clear" newline bitfld.long 0x18 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No effect,Clear" bitfld.long 0x18 9. " WFE_A_CH1_STORE_IRQ ,WFE A ch1 store engine interrupt" "No effect,Clear" bitfld.long 0x18 8. " WFE_A_CH0_STORE_IRQ ,WFE A ch0 store engine interrupt" "No effect,Clear" newline bitfld.long 0x18 7. " DITHER_CH1_STORE_IRQ ,Dither ch1 store engine interrupt" "No effect,Clear" bitfld.long 0x18 6. " DITHER_CH0_STORE_IRQ ,Dither ch0 store engine interrupt" "No effect,Clear" bitfld.long 0x18 5. " DITHER_CH1_PREFETCH_IRQ ,Dither ch1 prefetch engine interrupt" "No effect,Clear" newline bitfld.long 0x18 4. " DITHER_CH0_PREFETCH_IRQ ,Dither ch0 prefetch engine interrupt" "No effect,Clear" bitfld.long 0x18 3. " FIRST_CH1_STORE_IRQ ,Initial ch1 store engine interrupt" "No effect,Clear" bitfld.long 0x18 2. " FIRST_CH0_STORE_IRQ ,Initial ch0 store engine interrupt" "No effect,Clear" newline bitfld.long 0x18 1. " FIRST_CH1_PREFETCH_IRQ ,Initial ch1 prefetch engine interrupt" "No effect,Clear" bitfld.long 0x18 0. " FIRST_CH0_PREFETCH_IRQ ,Initial ch0 prefetch engine interrupt" "No effect,Clear" line.long 0x1C "HW_PXP_IRQ_TOG,HW_PXP_IRQ_TOG" bitfld.long 0x1C 31. " COMPRESS_DONE_IRQ ,Compression done interrupt" "Not toggled,Toggled" bitfld.long 0x1C 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 14. " WFE_A_STORE_IRQ ,WFE A store engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 13. " DITHER_STORE_IRQ ,Dither store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 12. " FIRST_STORE_IRQ ,Initial store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 9. " WFE_A_CH1_STORE_IRQ ,WFE A ch1 store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 8. " WFE_A_CH0_STORE_IRQ ,WFE A ch0 store engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 7. " DITHER_CH1_STORE_IRQ ,Dither ch1 store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 6. " DITHER_CH0_STORE_IRQ ,Dither ch0 store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 5. " DITHER_CH1_PREFETCH_IRQ ,Dither ch1 prefetch engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 4. " DITHER_CH0_PREFETCH_IRQ ,Dither ch0 prefetch engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 3. " FIRST_CH1_STORE_IRQ ,Initial ch1 store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 2. " FIRST_CH0_STORE_IRQ ,Initial ch0 store engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " FIRST_CH1_PREFETCH_IRQ ,Initial ch1 prefetch engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 0. " FIRST_CH0_PREFETCH_IRQ ,Initial ch0 prefetch engine interrupt" "Not toggled,Toggled" group.long 0x400++0x03 line.long 0x00 "NEXT,Next Frame Pointer" hexmask.long 0x00 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" rbitfld.long 0x00 0. " ENABLED ,Indicates that the 'next frame' functionality has been enabled" "Disabled,Enabled" width 35. tree "Input Registers" group.long 0x450++0x1F line.long 0x00 "INPUT_FETCH_CTRL_CH0,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x00 31. " ARBIT_EN ,Enables arbitration" "Disabled,Enabled" bitfld.long 0x00 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x00 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x00 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x00 10. " VFLIP ,Enables VFLIP" "Disabled,Enabled" bitfld.long 0x00 9. " HFLIP ,Enables HFLIP" "Disabled,Enabled" newline bitfld.long 0x00 5. " HIGH_BYTE ,Channel 0 high byte selection" "No,Yes" bitfld.long 0x00 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Memory,Previous process engine" bitfld.long 0x00 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Disabled,Enabled" newline bitfld.long 0x00 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x00 1. " BLOCK_EN ,Chooses the prefetch mode" "Scan mode,Block mode" bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "INPUT_FETCH_CTRL_CH0_SET,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x04 31. " ARBIT_EN ,Enables arbitration" "No effect,Set" bitfld.long 0x04 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x04 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x04 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x04 10. " VFLIP ,Enables VFLIP" "No effect,Set" bitfld.long 0x04 9. " HFLIP ,Enables HFLIP" "No effect,Set" newline bitfld.long 0x04 5. " HIGH_BYTE ,Channel 0 high byte selection" "No effect,Set" bitfld.long 0x04 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Set" bitfld.long 0x04 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Set" newline bitfld.long 0x04 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x04 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Set" bitfld.long 0x04 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x08 "INPUT_FETCH_CTRL_CH0_CLR,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x08 31. " ARBIT_EN ,Enables arbitration" "No effect,Clear" bitfld.long 0x08 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x08 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x08 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x08 10. " VFLIP ,Enables VFLIP" "No effect,Clear" bitfld.long 0x08 9. " HFLIP ,Enables HFLIP" "No effect,Clear" newline bitfld.long 0x08 5. " HIGH_BYTE ,Channel 0 high byte selection" "No effect,Clear" bitfld.long 0x08 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Clear" bitfld.long 0x08 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Clear" newline bitfld.long 0x08 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x08 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Clear" bitfld.long 0x08 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x0C "INPUT_FETCH_CTRL_CH0_TOG,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x0C 31. " ARBIT_EN ,Enables arbitration" "Not toggled,Toggled" bitfld.long 0x0C 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x0C 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x0C 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x0C 10. " VFLIP ,Enables VFLIP" "Not toggled,Toggled" bitfld.long 0x0C 9. " HFLIP ,Enables HFLIP" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " HIGH_BYTE ,Channel 0 high byte selection" "Not toggled,Toggled" bitfld.long 0x0C 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Not toggled,Toggled" bitfld.long 0x0C 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x0C 1. " BLOCK_EN ,Chooses the prefetch mode" "Not toggled,Toggled" bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" line.long 0x10 "INPUT_FETCH_CTRL_CH1,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x10 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x10 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x10 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x10 10. " VFLIP ,Enables VFLIP" "Disabled,Enabled" bitfld.long 0x10 9. " HFLIP ,Enables HFLIP" "Disabled,Enabled" bitfld.long 0x10 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Memory,Previous process engine" newline bitfld.long 0x10 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x10 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x10 1. " BLOCK_EN ,Chooses the prefetch mode" "Scan mode,Block mode" newline bitfld.long 0x10 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x14 "INPUT_FETCH_CTRL_CH1_SET,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x14 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x14 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x14 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x14 10. " VFLIP ,Enables VFLIP" "No effect,Set" bitfld.long 0x14 9. " HFLIP ,Enables HFLIP" "No effect,Set" bitfld.long 0x14 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Set" newline bitfld.long 0x14 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Set" bitfld.long 0x14 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x14 1. " BLOCK_EN ,Chooses the prefetch mode" "Not effect,Set" newline bitfld.long 0x14 0. " CH_EN ,Channel enable" "Not effect,Set" line.long 0x18 "INPUT_FETCH_CTRL_CH1_CLR,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x18 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x18 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x18 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x18 10. " VFLIP ,Enables VFLIP" "No effect,Clear" bitfld.long 0x18 9. " HFLIP ,Enables HFLIP" "Not effect,Clear" bitfld.long 0x18 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Clear" newline bitfld.long 0x18 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x18 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x18 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Clear" newline bitfld.long 0x18 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x1C "INPUT_FETCH_CTRL_CH1_TOG,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x1C 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x1C 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x1C 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x1C 10. " VFLIP ,Enables VFLIP" "Not toggled,Toggled" bitfld.long 0x1C 9. " HFLIP ,Enables HFLIP" "Not toggled,Toggled" bitfld.long 0x1C 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x1C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x1C 1. " BLOCK_EN ,Chooses the prefetch mode" "Not toggled,Toggled" newline bitfld.long 0x1C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" rgroup.long 0x470++0x03 line.long 0x00 "INPUT_FETCH_STATUS_CH0,Pre-fetch Engine Status Channel 0 Register" hexmask.long.word 0x00 16.--31. 1. " PREFETCH_BLOCK_Y ,Scan mode: indicates the current Y coordinate of the frame;block mode indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " PREFETCH_BLOCK_X ,Scan mode: always 0;block mode indicates the X coordinate of the block currently being rendered" rgroup.long 0x480++0x03 line.long 0x00 "INPUT_FETCH_STATUS_CH1,Store Engine Status Channel 1 Register" hexmask.long.word 0x00 16.--31. 1. " PREFETCH_BLOCK_Y ,Scan mode: indicates the current Y coordinate of the frame;block mode indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " PREFETCH_BLOCK_X ,Scan mode: always 0;block mode indicates the X coordinate of the block currently being rendered" group.long 0x490++0x03 line.long 0x00 "INPUT_FETCH_ACTIVE_SIZE_ULC_CH0,INPUT_FETCH_ACTIVE_SIZE_ULC_CH0" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_ULC_Y ,Indicates the upper left Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_ULC_X ,Indicates the upper left X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x4A0++0x03 line.long 0x00 "INPUT_FETCH_ACTIVE_SIZE_LRC_CH0,INPUT_FETCH_ACTIVE_SIZE_LRC_CH0" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_LRC_Y ,Indicates the lower right Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_LRC_X ,Indicates the lower right X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x4B0++0x03 line.long 0x00 "INPUT_FETCH_ACTIVE_SIZE_ULC_CH1,INPUT_FETCH_ACTIVE_SIZE_ULC_CH1" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_ULC_Y ,Indicates the upper left Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_ULC_X ,Indicates the upper left X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x4C0++0x03 line.long 0x00 "INPUT_FETCH_ACTIVE_SIZE_LRC_CH1,INPUT_FETCH_ACTIVE_SIZE_LRC_CH1" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_LRC_Y ,Indicates the lower right Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_LRC_X ,Indicates the lower right X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x4D0++0x03 line.long 0x00 "INPUT_FETCH_SIZE_CH0,INPUT_FETCH_SIZE_CH0" hexmask.long.word 0x00 16.--31. 1. " INPUT_TOTAL_HEIGHT ,Actual total height - 1" hexmask.long.word 0x00 0.--15. 1. " INPUT_TOTAL_WIDTH ,Actual total width - 1" group.long 0x4E0++0x03 line.long 0x00 "INPUT_FETCH_SIZE_CH1,INPUT_FETCH_SIZE_CH1" hexmask.long.word 0x00 16.--31. 1. " INPUT_TOTAL_HEIGHT ,Actual total height - 1" hexmask.long.word 0x00 0.--15. 1. " INPUT_TOTAL_WIDTH ,Actual total width - 1" group.long 0x4F0++0x03 line.long 0x00 "INPUT_FETCH_BACKGROUND_COLOR_CH0,INPUT_FETCH_BACKGROUND_COLOR_CH0" group.long 0x500++0x03 line.long 0x00 "INPUT_FETCH_BACKGROUND_COLOR_CH1,INPUT_FETCH_BACKGROUND_COLOR_CH1" group.long 0x510++0x03 line.long 0x00 "INPUT_FETCH_PITCH,INPUT_FETCH_PITCH" hexmask.long.word 0x00 16.--31. 1. " CH1_INPUT_PITCH ,Indicates the channel 1 input pitch" hexmask.long.word 0x00 0.--15. 1. " CH0_INPUT_PITCH ,Indicates the channel 0 input pitch" group.long 0x520++0x63 line.long 0x00 "INPUT_FETCH_SHIFT_CTRL_CH0,INPUT_FETCH_SHIFT_CTRL_CH0" bitfld.long 0x00 12. " SHIFT_BYPASS ,CH0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x00 11. " EXPAND_EN ,Expand enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x00 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x04 "INPUT_FETCH_SHIFT_CTRL_CH0_SET,INPUT_FETCH_SHIFT_CTRL_CH0_SET" bitfld.long 0x04 12. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Set" bitfld.long 0x04 11. " EXPAND_EN ,Expand enable" "No effect,Set" bitfld.long 0x04 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x04 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x08 "INPUT_FETCH_SHIFT_CTRL_CH0_CLR,INPUT_FETCH_SHIFT_CTRL_CH0_CLR" bitfld.long 0x08 12. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Clear" bitfld.long 0x08 11. " EXPAND_EN ,Expand enable" "No effect,Clear" bitfld.long 0x08 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x08 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x0C "INPUT_FETCH_SHIFT_CTRL_CH0_TOG,INPUT_FETCH_SHIFT_CTRL_CH0_TOG" bitfld.long 0x0C 12. " SHIFT_BYPASS ,CH0 shift bypass" "Not toggled,Toggled" bitfld.long 0x0C 11. " EXPAND_EN ,Expand enable" "Not toggled,Toggled" bitfld.long 0x0C 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x0C 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x10 "INPUT_FETCH_SHIFT_CTRL_CH1,INPUT_FETCH_SHIFT_CTRL_CH1" bitfld.long 0x10 12. " SHIFT_BYPASS ,CH1 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x10 11. " EXPAND_EN ,Expand enable" "Disabled,Enabled" bitfld.long 0x10 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x10 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x14 "INPUT_FETCH_SHIFT_CTRL_CH1_SET,INPUT_FETCH_SHIFT_CTRL_CH1_SET" bitfld.long 0x14 12. " SHIFT_BYPASS ,CH1 shift bypass" "No effect,Set" bitfld.long 0x14 11. " EXPAND_EN ,Expand enable" "No effect,Set" bitfld.long 0x14 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x14 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x18 "INPUT_FETCH_SHIFT_CTRL_CH1_CLR,INPUT_FETCH_SHIFT_CTRL_CH1_CLR" bitfld.long 0x18 12. " SHIFT_BYPASS ,CH1 shift bypass" "No effect,Clear" bitfld.long 0x18 11. " EXPAND_EN ,Expand enable" "No effect,Clear" bitfld.long 0x18 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x18 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x1C "INPUT_FETCH_SHIFT_CTRL_CH1_TOG,INPUT_FETCH_SHIFT_CTRL_CH1_TOG" bitfld.long 0x1C 12. " SHIFT_BYPASS ,CH1 shift bypass" "Not toggled,Toggled" bitfld.long 0x1C 11. " EXPAND_EN ,Expand enable" "Not toggled,Toggled" bitfld.long 0x1C 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x1C 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x20 "INPUT_FETCH_SHIFT_OFFSET_CH0,INPUT_FETCH_SHIFT_OFFSET_CH0" bitfld.long 0x20 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "INPUT_FETCH_SHIFT_OFFSET_CH0_SET,INPUT_FETCH_SHIFT_OFFSET_CH0_SET" bitfld.long 0x24 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "INPUT_FETCH_SHIFT_OFFSET_CH0_CLR,INPUT_FETCH_SHIFT_OFFSET_CH0_CLR" bitfld.long 0x28 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "INPUT_FETCH_SHIFT_OFFSET_CH0_TOG,INPUT_FETCH_SHIFT_OFFSET_CH0_TOG" bitfld.long 0x2C 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "INPUT_FETCH_SHIFT_OFFSET_CH1,INPUT_FETCH_SHIFT_OFFSET_CH1" bitfld.long 0x30 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "INPUT_FETCH_SHIFT_OFFSET_CH1_SET,INPUT_FETCH_SHIFT_OFFSET_CH1_SET" bitfld.long 0x34 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "INPUT_FETCH_SHIFT_OFFSET_CH1_CLR,INPUT_FETCH_SHIFT_OFFSET_CH1_CLR" bitfld.long 0x38 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "INPUT_FETCH_SHIFT_OFFSET_CH1_TOG,INPUT_FETCH_SHIFT_OFFSET_CH1_TOG" bitfld.long 0x3C 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "INPUT_FETCH_SHIFT_WIDTH_CH0,INPUT_FETCH_SHIFT_WIDTH_CH0" bitfld.long 0x40 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "INPUT_FETCH_SHIFT_WIDTH_CH0_SET,INPUT_FETCH_SHIFT_WIDTH_CH0_SET" bitfld.long 0x44 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "INPUT_FETCH_SHIFT_WIDTH_CH0_CLR,INPUT_FETCH_SHIFT_WIDTH_CH0_CLR" bitfld.long 0x48 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "INPUT_FETCH_SHIFT_WIDTH_CH0_TOG,INPUT_FETCH_SHIFT_WIDTH_CH0_TOG" bitfld.long 0x4C 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x50 "INPUT_FETCH_SHIFT_WIDTH_CH1,INPUT_FETCH_SHIFT_WIDTH_CH1" bitfld.long 0x50 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x54 "INPUT_FETCH_SHIFT_WIDTH_CH1_SET,INPUT_FETCH_SHIFT_WIDTH_CH1_SET" bitfld.long 0x54 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x58 "INPUT_FETCH_SHIFT_WIDTH_CH1_CLR,INPUT_FETCH_SHIFT_WIDTH_CH1_CLR" bitfld.long 0x58 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x5C "INPUT_FETCH_SHIFT_WIDTH_CH1_TOG,INPUT_FETCH_SHIFT_WIDTH_CH1_TOG" bitfld.long 0x5C 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x60 "INPUT_FETCH_ADDR_0_CH0,INPUT_FETCH_ADDR_0_CH0" group.long 0x590++0x03 line.long 0x00 "INPUT_FETCH_ADDR_1_CH0,INPUT_FETCH_ADDR_1_CH0" group.long 0x5A0++0x03 line.long 0x00 "INPUT_FETCH_ADDR_0_CH1,INPUT_FETCH_ADDR_0_CH1" group.long 0x5B0++0x03 line.long 0x00 "INPUT_FETCH_ADDR_1_CH1,INPUT_FETCH_ADDR_1_CH1" group.long 0x5C0++0x1F line.long 0x00 "INPUT_STORE_CTRL_CH0,Store Engine Control Channel 0 Register" bitfld.long 0x00 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x00 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 11. " FILL_DATA_EN ,Fill data enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x00 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x00 8. " STORE_BYPASS_EN ,Store bypass enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" newline bitfld.long 0x00 4. " ARRAY_EN ,Array handshake enable" "Disabled,Enabled" bitfld.long 0x00 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x00 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x00 1. " BLOCK_EN ,Chooses the store mode" "Scan mode,Block mode" newline bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "INPUT_STORE_CTRL_CH0_SET,Store Engine Control Channel 0 Register" bitfld.long 0x04 31. " ARBIT_EN ,Arbitration enable" "No effect,Set" bitfld.long 0x04 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "No effect,Set" bitfld.long 0x04 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x04 11. " FILL_DATA_EN ,Fill data enable" "No effect,Set" newline bitfld.long 0x04 10. " PACK_IN_SEL ,Selects out data to pack" "No effect,Set" bitfld.long 0x04 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Set" bitfld.long 0x04 8. " STORE_BYPASS_EN ,Store bypass enable" "No effect,Set" bitfld.long 0x04 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" newline bitfld.long 0x04 4. " ARRAY_EN ,Array handshake enable" "No effect,Set" bitfld.long 0x04 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Set" bitfld.long 0x04 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x04 1. " BLOCK_EN ,Chooses the store mode" "No effect,Set" newline bitfld.long 0x04 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x08 "INPUT_STORE_CTRL_CH0_CLR,Store Engine Control Channel 0 Register" bitfld.long 0x08 31. " ARBIT_EN ,Arbitration enable" "No effect,Clear" bitfld.long 0x08 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "No effect,Clear" bitfld.long 0x08 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x08 11. " FILL_DATA_EN ,Fill data enable" "No effect,Clear" newline bitfld.long 0x08 10. " PACK_IN_SEL ,Selects out data to pack" "No effect,Clear" bitfld.long 0x08 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Clear" bitfld.long 0x08 8. " STORE_BYPASS_EN ,Store bypass enable" "No effect,Clear" bitfld.long 0x08 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" newline bitfld.long 0x08 4. " ARRAY_EN ,Array handshake enable" "No effect,Clear" bitfld.long 0x08 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x08 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x08 1. " BLOCK_EN ,Chooses the store mode" "No effect,Clear" newline bitfld.long 0x08 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x0C "INPUT_STORE_CTRL_CH0_TOG,Store Engine Control Channel 0 Register" bitfld.long 0x0C 31. " ARBIT_EN ,Arbitration enable" "Not toggled,Toggled" bitfld.long 0x0C 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Not toggled,Toggled" bitfld.long 0x0C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x0C 11. " FILL_DATA_EN ,Fill data enable" "Not toggled,Toggled" newline bitfld.long 0x0C 10. " PACK_IN_SEL ,Selects out data to pack" "Not toggled,Toggled" bitfld.long 0x0C 9. " STORE_MEMORY_EN ,Store memory enable" "Not toggled,Toggled" bitfld.long 0x0C 8. " STORE_BYPASS_EN ,Store bypass enable" "Not toggled,Toggled" bitfld.long 0x0C 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" newline bitfld.long 0x0C 4. " ARRAY_EN ,Array handshake enable" "Not toggled,Toggled" bitfld.long 0x0C 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x0C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x0C 1. " BLOCK_EN ,Chooses the store mode" "Not toggled,Toggled" newline bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" line.long 0x10 "INPUT_STORE_CTRL_CH1,Store Engine Control Channel 1 Register" bitfld.long 0x10 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x10 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x10 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x10 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Disabled,Enabled" newline bitfld.long 0x10 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x10 4. " ARRAY_EN ,Array handshake enable" "Disabled,Enabled" bitfld.long 0x10 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x10 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" newline bitfld.long 0x10 1. " BLOCK_EN ,Chooses the store mode" "Scan mode,Block mode" bitfld.long 0x10 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x14 "INPUT_STORE_CTRL_CH1_SET,Store Engine Control Channel 1 Register" bitfld.long 0x14 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x14 10. " PACK_IN_SEL ,Selects out data to pack" "64 shift,Low 32 bit shift" bitfld.long 0x14 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Set" bitfld.long 0x14 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Set" newline bitfld.long 0x14 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x14 4. " ARRAY_EN ,Array handshake enable" "No effect,Set" bitfld.long 0x14 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Set" bitfld.long 0x14 2. " BLOCK_16 ,Determines the block size" "No effect,Set" newline bitfld.long 0x14 1. " BLOCK_EN ,Chooses the store mode" "No effect,Set" bitfld.long 0x14 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x18 "INPUT_STORE_CTRL_CH1_CLR,Store Engine Control Channel 1 Register" bitfld.long 0x18 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x18 10. " PACK_IN_SEL ,Selects out data to pack" "64 shift,Low 32 bit shift" bitfld.long 0x18 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Clear" bitfld.long 0x18 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Clear" newline bitfld.long 0x18 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x18 4. " ARRAY_EN ,Array handshake enable" "No effect,Clear" bitfld.long 0x18 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x18 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" newline bitfld.long 0x18 1. " BLOCK_EN ,Chooses the store mode" "No effect,Clear" bitfld.long 0x18 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x1C "INPUT_STORE_CTRL_CH1_TOG,Store Engine Control Channel 1 Register" bitfld.long 0x1C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x1C 10. " PACK_IN_SEL ,Selects out data to pack" "64 shift,Low 32 bit shift" bitfld.long 0x1C 9. " STORE_MEMORY_EN ,Store memory enable" "Not toggled,Toggled" bitfld.long 0x1C 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Not toggled,Toggled" newline bitfld.long 0x1C 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x1C 4. " ARRAY_EN ,Array handshake enable" "Not toggled,Toggled" bitfld.long 0x1C 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x1C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " BLOCK_EN ,Chooses the store mode" "Not toggled,Toggled" bitfld.long 0x1C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" rgroup.long 0x5E0++0x03 line.long 0x00 "INPUT_STORE_STATUS_CH0,Store Engine Status Channel 0 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,In scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" rgroup.long 0x5F0++0x03 line.long 0x00 "INPUT_STORE_STATUS_CH1,Store Engine Status Channel 1 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,In scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" group.long 0x600++0x03 line.long 0x00 "INPUT_STORE_SIZE_CH0,INPUT_STORE_SIZE_CH0" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGHT ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0x610++0x03 line.long 0x00 "INPUT_STORE_SIZE_CH1,INPUT_STORE_SIZE_CH1" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGHT ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0x620++0x03 line.long 0x00 "INPUT_STORE_PITCH,INPUT_STORE_PITCH" hexmask.long.word 0x00 16.--31. 1. " CH1_OUT_PITCH ,Indicates the channel 1 output pitch" hexmask.long.word 0x00 0.--15. 1. " CH0_OUT_PITCH ,Indicates the channel 0 output pitch" group.long 0x630++0x1F line.long 0x00 "INPUT_STORE_SHIFT_CTRL_CH0,INPUT_STORE_SHIFT_CTRL_CH0" bitfld.long 0x00 7. " SHIFT_BYPASS ,CH0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x00 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x00 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x00 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x04 "INPUT_STORE_SHIFT_CTRL_CH0_SET,INPUT_STORE_SHIFT_CTRL_CH0_SET" bitfld.long 0x04 7. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Set" bitfld.long 0x04 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Set" bitfld.long 0x04 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Set" bitfld.long 0x04 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x08 "INPUT_STORE_SHIFT_CTRL_CH0_CLR,INPUT_STORE_SHIFT_CTRL_CH0_CLR" bitfld.long 0x08 7. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Clear" bitfld.long 0x08 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Clear" bitfld.long 0x08 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Clear" bitfld.long 0x08 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x0C "INPUT_STORE_SHIFT_CTRL_CH0_TOG,INPUT_STORE_SHIFT_CTRL_CH0_TOG" bitfld.long 0x0C 7. " SHIFT_BYPASS ,CH0 shift bypass" "Not toggled,Toggled" bitfld.long 0x0C 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Not toggled,Toggled" bitfld.long 0x0C 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Not toggled,Toggled" bitfld.long 0x0C 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x10 "INPUT_STORE_SHIFT_CTRL_CH1,INPUT_STORE_SHIFT_CTRL_CH1" bitfld.long 0x10 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x10 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x10 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x14 "INPUT_STORE_SHIFT_CTRL_CH1_SET,INPUT_STORE_SHIFT_CTRL_CH1_SET" bitfld.long 0x14 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Set" bitfld.long 0x14 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Set" bitfld.long 0x14 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x18 "INPUT_STORE_SHIFT_CTRL_CH1_CLR,INPUT_STORE_SHIFT_CTRL_CH1_CLR" bitfld.long 0x18 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Clear" bitfld.long 0x18 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Clear" bitfld.long 0x18 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x1C "INPUT_STORE_SHIFT_CTRL_CH1_TOG,INPUT_STORE_SHIFT_CTRL_CH1_TOG" bitfld.long 0x1C 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Not toggled,Toggled" bitfld.long 0x1C 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Not toggled,Toggled" bitfld.long 0x1C 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" group.long 0x690++0x03 line.long 0x00 "INPUT_STORE_ADDR_0_CH0,INPUT_STORE_ADDR_0_CH0" group.long 0x6A0++0x03 line.long 0x00 "INPUT_STORE_ADDR_1_CH0,INPUT_STORE_ADDR_1_CH0" group.long 0x6B0++0x03 line.long 0x00 "INPUT_STORE_FILL_DATA_CH0,INPUT_STORE_FILL_DATA_CH0" group.long 0x6C0++0x03 line.long 0x00 "INPUT_STORE_ADDR_0_CH1,INPUT_STORE_ADDR_0_CH1" group.long 0x6D0++0x03 line.long 0x00 "INPUT_STORE_ADDR_1_CH1,INPUT_STORE_ADDR_1_CH1" group.long 0x6E0++0x03 line.long 0x00 "INPUT_STORE_D_MASK0_H_CH0,INPUT_STORE_D_MASK0_H_CH0" group.long 0x6F0++0x03 line.long 0x00 "INPUT_STORE_D_MASK0_L_CH0,INPUT_STORE_D_MASK0_L_CH0" group.long 0x700++0x03 line.long 0x00 "INPUT_STORE_D_MASK1_H_CH0,INPUT_STORE_D_MASK1_H_CH0" group.long 0x710++0x03 line.long 0x00 "INPUT_STORE_D_MASK1_L_CH0,INPUT_STORE_D_MASK1_L_CH0" group.long 0x720++0x03 line.long 0x00 "INPUT_STORE_D_MASK2_H_CH0,INPUT_STORE_D_MASK2_H_CH0" group.long 0x730++0x03 line.long 0x00 "INPUT_STORE_D_MASK2_L_CH0,INPUT_STORE_D_MASK2_L_CH0" group.long 0x740++0x03 line.long 0x00 "INPUT_STORE_D_MASK3_H_CH0,INPUT_STORE_D_MASK3_H_CH0" group.long 0x750++0x03 line.long 0x00 "INPUT_STORE_D_MASK3_L_CH0,INPUT_STORE_D_MASK3_L_CH0" group.long 0x760++0x03 line.long 0x00 "INPUT_STORE_D_MASK4_H_CH0,INPUT_STORE_D_MASK4_H_CH0" group.long 0x770++0x03 line.long 0x00 "INPUT_STORE_D_MASK4_L_CH0,INPUT_STORE_D_MASK4_L_CH0" group.long 0x780++0x03 line.long 0x00 "INPUT_STORE_D_MASK5_H_CH0,INPUT_STORE_D_MASK5_H_CH0" group.long 0x790++0x03 line.long 0x00 "INPUT_STORE_D_MASK5_L_CH0,INPUT_STORE_D_MASK5_L_CH0" group.long 0x7A0++0x03 line.long 0x00 "INPUT_STORE_D_MASK6_H_CH0,INPUT_STORE_D_MASK6_H_CH0" group.long 0x7B0++0x03 line.long 0x00 "INPUT_STORE_D_MASK6_L_CH0,INPUT_STORE_D_MASK6_L_CH0" group.long 0x7C0++0x03 line.long 0x00 "INPUT_STORE_D_MASK7_H_CH0,INPUT_STORE_D_MASK7_H_CH0" group.long 0x7E0++0x03 line.long 0x00 "INPUT_STORE_D_MASK7_L_CH0,INPUT_STORE_D_MASK7_L_CH0" group.long 0x7F0++0x03 line.long 0x00 "INPUT_STORE_D_SHIFT_L_CH0,INPUT_STORE_D_SHIFT_L_CH0" bitfld.long 0x00 31. " D_SHIFT_FLAG3 ,Data shift flag 3" "Low,High" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH3 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " D_SHIFT_FLAG2 ,Data shift flag 2" "Low,High" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH2 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG1 ,Data shift flag 1" "Low,High" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH1 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " D_SHIFT_FLAG0 ,Data shift flag 0" "Low,High" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH0 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x800++0x03 line.long 0x00 "INPUT_STORE_D_SHIFT_H_CH0,INPUT_STORE_D_SHIFT_H_CH0" bitfld.long 0x00 31. " D_SHIFT_FLAG7 ,Data shift flag 7" "Low,High" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH7 ,Data shift width 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " D_SHIFT_FLAG6 ,Data shift flag 6" "Low,High" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH6 ,Data shift width 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG5 ,Data shift flag 5" "Low,High" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH5 ,Data shift width 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " D_SHIFT_FLAG4 ,Data shift flag 4" "Low,High" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH4 ,Data shift width 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x810++0x03 line.long 0x00 "INPUT_STORE_F_SHIFT_L_CH0,INPUT_STORE_F_SHIFT_L_CH0" bitfld.long 0x00 30. " F_SHIFT_FLAG3 ,Flag shift flag3" "Low,High" bitfld.long 0x00 24.--29. " F_SHIFT_WIDTH3 ,Flag shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " F_SHIFT_FLAG2 ,Flag shift flag2" "Low,High" bitfld.long 0x00 16.--21. " F_SHIFT_WIDTH2 ,Flag shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 14. " F_SHIFT_FLAG1 ,Flag shift flag1" "Low,High" bitfld.long 0x00 8.--13. " F_SHIFT_WIDTH1 ,Flag shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " F_SHIFT_FLAG0 ,Flag shift flag0" "Low,High" bitfld.long 0x00 0.--5. " F_SHIFT_WIDTH0 ,Flag shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x820++0x03 line.long 0x00 "INPUT_STORE_F_SHIFT_H_CH0,INPUT_STORE_F_SHIFT_H_CH0" bitfld.long 0x00 30. " F_SHIFT_FLAG7 ,Flag shift flag7" "Low,High" bitfld.long 0x00 24.--29. " F_SHIFT_WIDTH7 ,Flag shift width 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " F_SHIFT_FLAG6 ,Flag shift flag6" "Low,High" bitfld.long 0x00 16.--21. " F_SHIFT_WIDTH6 ,Flag shift width 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 14. " F_SHIFT_FLAG5 ,Flag shift flag5" "Low,High" bitfld.long 0x00 8.--13. " F_SHIFT_WIDTH5 ,Flag shift width 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " F_SHIFT_FLAG4 ,Flag shift flag4" "Low,High" bitfld.long 0x00 0.--5. " F_SHIFT_WIDTH4 ,Flag shift width 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x830++0x03 line.long 0x00 "INPUT_STORE_F_MASK_L_CH0,INPUT_STORE_F_MASK_L_CH0" hexmask.long.byte 0x00 24.--31. 1. " F_MASK3 ,Flag mask3" hexmask.long.byte 0x00 16.--23. 1. " F_MASK2 ,Flag mask2" hexmask.long.byte 0x00 8.--15. 1. " F_MASK1 ,Flag mask1" hexmask.long.byte 0x00 0.--7. 1. " F_MASK0 ,Flag mask0" group.long 0x840++0x03 line.long 0x00 "INPUT_STORE_F_MASK_H_CH0,INPUT_STORE_F_MASK_H_CH0" hexmask.long.byte 0x00 24.--31. 1. " F_MASK7 ,Flag mask7" hexmask.long.byte 0x00 16.--23. 1. " F_MASK6 ,Flag mask6" hexmask.long.byte 0x00 8.--15. 1. " F_MASK5 ,Flag mask5" hexmask.long.byte 0x00 0.--7. 1. " F_MASK4 ,Flag mask4" tree.end width 35. tree "Dither Registers" group.long 0x850++0x1F line.long 0x00 "DITHER_FETCH_CTRL_CH0,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x00 31. " ARBIT_EN ,Enables arbitration" "Disabled,Enabled" bitfld.long 0x00 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x00 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x00 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x00 10. " VFLIP ,Enables VFLIP" "Disabled,Enabled" bitfld.long 0x00 9. " HFLIP ,Enables HFLIP" "Disabled,Enabled" newline bitfld.long 0x00 5. " HIGH_BYTE ,Channel 0 high byte selection" "No,Yes" bitfld.long 0x00 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Memory,Previous process engine" bitfld.long 0x00 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Disabled,Enabled" newline bitfld.long 0x00 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x00 1. " BLOCK_EN ,Chooses the prefetch mode" "Scan mode,Block mode" bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "DITHER_FETCH_CTRL_CH0_SET,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x04 31. " ARBIT_EN ,Enables arbitration" "No effect,Set" bitfld.long 0x04 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x04 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x04 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x04 10. " VFLIP ,Enables VFLIP" "No effect,Set" bitfld.long 0x04 9. " HFLIP ,Enables HFLIP" "No effect,Set" newline bitfld.long 0x04 5. " HIGH_BYTE ,Channel 0 high byte selection" "No effect,Set" bitfld.long 0x04 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Set" bitfld.long 0x04 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Set" newline bitfld.long 0x04 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x04 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Set" bitfld.long 0x04 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x08 "DITHER_FETCH_CTRL_CH0_CLR,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x08 31. " ARBIT_EN ,Enables arbitration" "No effect,Clear" bitfld.long 0x08 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x08 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x08 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x08 10. " VFLIP ,Enables VFLIP" "No effect,Clear" bitfld.long 0x08 9. " HFLIP ,Enables HFLIP" "No effect,Clear" newline bitfld.long 0x08 5. " HIGH_BYTE ,Channel 0 high byte selection" "No effect,Clear" bitfld.long 0x08 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "No effect,Clear" bitfld.long 0x08 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Clear" newline bitfld.long 0x08 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x08 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Clear" bitfld.long 0x08 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x0C "DITHER_FETCH_CTRL_CH0_TOG,Pre-fetch Engine Control Channel 0 Register" bitfld.long 0x0C 31. " ARBIT_EN ,Enables arbitration" "Not toggled,Toggled" bitfld.long 0x0C 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x0C 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x0C 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.long 0x0C 10. " VFLIP ,Enables VFLIP" "Not toggled,Toggled" bitfld.long 0x0C 9. " HFLIP ,Enables HFLIP" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " HIGH_BYTE ,Channel 0 high byte selection" "Not toggled,Toggled" bitfld.long 0x0C 4. " BYPASS_PIXEL_EN ,Selects channel 0 pixel source" "Not toggled,Toggled" bitfld.long 0x0C 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x0C 1. " BLOCK_EN ,Chooses the prefetch mode" "Not toggled,Toggled" bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" line.long 0x10 "DITHER_FETCH_CTRL_CH1,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x10 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x10 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x10 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x10 10. " VFLIP ,Enables VFLIP" "Disabled,Enabled" bitfld.long 0x10 9. " HFLIP ,Enables HFLIP" "Disabled,Enabled" bitfld.long 0x10 4. " BYPASS_PIXEL_EN ,Selects channel 1 pixel source" "Memory,Previous process engine" newline bitfld.long 0x10 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x10 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x10 1. " BLOCK_EN ,Chooses the prefetch mode" "Scan mode,Block mode" newline bitfld.long 0x10 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x14 "DITHER_FETCH_CTRL_CH1_SET,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x14 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x14 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x14 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x14 10. " VFLIP ,Enables VFLIP" "No effect,Set" bitfld.long 0x14 9. " HFLIP ,Enables HFLIP" "No effect,Set" bitfld.long 0x14 4. " BYPASS_PIXEL_EN ,Selects channel 1 pixel source" "No effect,Set" newline bitfld.long 0x14 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Set" bitfld.long 0x14 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x14 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Set" newline bitfld.long 0x14 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x18 "DITHER_FETCH_CTRL_CH1_CLR,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x18 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x18 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x18 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x18 10. " VFLIP ,Enables VFLIP" "No effect,Clear" bitfld.long 0x18 9. " HFLIP ,Enables HFLIP" "No effect,Clear" bitfld.long 0x18 4. " BYPASS_PIXEL_EN ,Selects channel 1 pixel source" "No effect,Clear" newline bitfld.long 0x18 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x18 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x18 1. " BLOCK_EN ,Chooses the prefetch mode" "No effect,Clear" newline bitfld.long 0x18 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x1C "DITHER_FETCH_CTRL_CH1_TOG,Pre-fetch Engine Control Channel 1 Register" bitfld.long 0x1C 24.--25. " HANDSHAKE_SCAN_LINE_NUM ,Scans handshake line number" "1 line,8 line,16 line,16 line" bitfld.long 0x1C 16.--17. " RD_NUM_BYTES ,Bytes in a read burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x1C 12.--13. " ROTATION_ANGLE ,Degrees by which the image should be rotated" "0 degrees,90 degrees,180 degrees,270 degrees" newline bitfld.long 0x1C 10. " VFLIP ,Enables VFLIP" "Not toggled,Toggled" bitfld.long 0x1C 9. " HFLIP ,Enables HFLIP" "Not toggled,Toggled" bitfld.long 0x1C 4. " BYPASS_PIXEL_EN ,Selects channel 1 pixel source" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " HANDSHAKE_EN ,Enables bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x1C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x1C 1. " BLOCK_EN ,Chooses the prefetch mode" "Not toggled,Toggled" newline bitfld.long 0x1C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" rgroup.long 0x870++0x03 line.long 0x00 "DITHER_FETCH_STATUS_CH0,Pre-fetch Engine Status Channel 0 Register" hexmask.long.word 0x00 16.--31. 1. " PREFETCH_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " PREFETCH_BLOCK_X ,Scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" rgroup.long 0x880++0x03 line.long 0x00 "DITHER_FETCH_STATUS_CH1,Store Engine Status Channel 1 Register" hexmask.long.word 0x00 16.--31. 1. " PREFETCH_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " PREFETCH_BLOCK_X ,Scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" group.long 0x890++0x03 line.long 0x00 "DITHER_FETCH_ACTIVE_SIZE_ULC_CH0,DITHER_FETCH_ACTIVE_SIZE_ULC_CH0" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_ULC_Y ,Indicates the upper left Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_ULC_X ,Indicates the upper left X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x8A0++0x03 line.long 0x00 "DITHER_FETCH_ACTIVE_SIZE_LRC_CH0,DITHER_FETCH_ACTIVE_SIZE_LRC_CH0" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_LRC_Y ,Indicates the lower right Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_LRC_X ,Indicates the lower right X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x8B0++0x03 line.long 0x00 "DITHER_FETCH_ACTIVE_SIZE_ULC_CH1,DITHER_FETCH_ACTIVE_SIZE_ULC_CH1" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_ULC_Y ,Indicates the upper left Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_ULC_X ,Indicates the upper left X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x8C0++0x03 line.long 0x00 "DITHER_FETCH_ACTIVE_SIZE_LRC_CH1,DITHER_FETCH_ACTIVE_SIZE_LRC_CH1" hexmask.long.word 0x00 16.--31. 1. " ACTIVE_SIZE_LRC_Y ,Indicates the lower right Y-coordinate(In pixels) of the active surface of the total input memory" hexmask.long.word 0x00 0.--15. 1. " ACTIVE_SIZE_LRC_X ,Indicates the lower right X-coordinate(In pixels) of the active surface of the total input memory" group.long 0x8D0++0x03 line.long 0x00 "DITHER_FETCH_SIZE_CH0,DITHER_FETCH_SIZE_CH0" hexmask.long.word 0x00 16.--31. 1. " INPUT_TOTAL_HEIGHT ,Actual total height -1" hexmask.long.word 0x00 0.--15. 1. " INPUT_TOTAL_WIDTH ,Actual total width -1" group.long 0x8E0++0x03 line.long 0x00 "DITHER_FETCH_SIZE_CH1,DITHER_FETCH_SIZE_CH1" hexmask.long.word 0x00 16.--31. 1. " INPUT_TOTAL_HEIGHT ,Actual total height -1" hexmask.long.word 0x00 0.--15. 1. " INPUT_TOTAL_WIDTH ,Actual total width -1" group.long 0x8F0++0x03 line.long 0x00 "DITHER_FETCH_BACKGROUND_COLOR_CH0,DITHER_FETCH_BACKGROUND_COLOR_CH0" group.long 0x900++0x03 line.long 0x00 "DITHER_FETCH_BACKGROUND_COLOR_CH1,DITHER_FETCH_BACKGROUND_COLOR_CH1" newline group.long 0x910++0x03 line.long 0x00 "DITHER_FETCH_PITCH,DITHER_FETCH_PITCH" hexmask.long.word 0x00 16.--31. 1. " CH1_INPUT_PITCH ,Indicates the channel 1 input pitch" hexmask.long.word 0x00 0.--15. 1. " CH0_INPUT_PITCH ,Indicates the channel 0 input pitch" group.long 0x920++0x63 line.long 0x00 "DITHER_FETCH_SHIFT_CTRL_CH0,DITHER_FETCH_SHIFT_CTRL_CH0" bitfld.long 0x00 12. " SHIFT_BYPASS ,CH0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x00 11. " EXPAND_EN ,Expand enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x00 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x04 "DITHER_FETCH_SHIFT_CTRL_CH0_SET,DITHER_FETCH_SHIFT_CTRL_CH0_SET" bitfld.long 0x04 12. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Set" bitfld.long 0x04 11. " EXPAND_EN ,Expand enable" "No effect,Set" bitfld.long 0x04 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x04 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x08 "DITHER_FETCH_SHIFT_CTRL_CH0_CLR,DITHER_FETCH_SHIFT_CTRL_CH0_CLR" bitfld.long 0x08 12. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Clear" bitfld.long 0x08 11. " EXPAND_EN ,Expand enable" "No effect,Clear" bitfld.long 0x08 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x08 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x0C "DITHER_FETCH_SHIFT_CTRL_CH0_TOG,DITHER_FETCH_SHIFT_CTRL_CH0_TOG" bitfld.long 0x0C 12. " SHIFT_BYPASS ,CH0 shift bypass" "Not toggled,Toggled" bitfld.long 0x0C 11. " EXPAND_EN ,Expand enable" "Not toggled,Toggled" bitfld.long 0x0C 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x0C 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x10 "DITHER_FETCH_SHIFT_CTRL_CH1,DITHER_FETCH_SHIFT_CTRL_CH1" bitfld.long 0x10 12. " SHIFT_BYPASS ,CH1 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x10 11. " EXPAND_EN ,Expand enable" "Disabled,Enabled" bitfld.long 0x10 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x10 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x14 "DITHER_FETCH_SHIFT_CTRL_CH1_SET,DITHER_FETCH_SHIFT_CTRL_CH1_SET" bitfld.long 0x14 12. " SHIFT_BYPASS ,CH1 shift bypass" "No effect,Set" bitfld.long 0x14 11. " EXPAND_EN ,Expand enable" "No effect,Set" bitfld.long 0x14 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x14 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x18 "DITHER_FETCH_SHIFT_CTRL_CH1_CLR,DITHER_FETCH_SHIFT_CTRL_CH1_CLR" bitfld.long 0x18 12. " SHIFT_BYPASS ,CH1 shift bypass" "No effect,Clear" bitfld.long 0x18 11. " EXPAND_EN ,Expand enable" "No effect,Clear" bitfld.long 0x18 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x18 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x1C "DITHER_FETCH_SHIFT_CTRL_CH1_TOG,DITHER_FETCH_SHIFT_CTRL_CH1_TOG" bitfld.long 0x1C 12. " SHIFT_BYPASS ,CH1 shift bypass" "Not toggled,Toggled" bitfld.long 0x1C 11. " EXPAND_EN ,Expand enable" "Not toggled,Toggled" bitfld.long 0x1C 8.--10. " EXPAND_FORMAT ,Selects pixel format" "RGB 565,RGB 555,ARGB 1555,RGB 444,ARGB 4444,YUYV/YVYU,UYVY/VYUY,YUV422_2P" bitfld.long 0x1C 0.--1. " INPUT_ACTIVE_BPP ,INPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x20 "DITHER_FETCH_SHIFT_OFFSET_CH0,DITHER_FETCH_SHIFT_OFFSET_CH0" bitfld.long 0x20 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "DITHER_FETCH_SHIFT_OFFSET_CH0_SET,DITHER_FETCH_SHIFT_OFFSET_CH0_SET" bitfld.long 0x24 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "DITHER_FETCH_SHIFT_OFFSET_CH0_CLR,DITHER_FETCH_SHIFT_OFFSET_CH0_CLR" bitfld.long 0x28 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "DITHER_FETCH_SHIFT_OFFSET_CH0_TOG,DITHER_FETCH_SHIFT_OFFSET_CH0_TOG" bitfld.long 0x2C 24.--28. " OFFSET3 ,Shift offset for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 16.--20. " OFFSET2 ,Shift offset for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 8.--12. " OFFSET1 ,Shift offset for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 0.--4. " OFFSET0 ,Shift offset for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "DITHER_FETCH_SHIFT_OFFSET_CH1,DITHER_FETCH_SHIFT_OFFSET_CH1" bitfld.long 0x30 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "DITHER_FETCH_SHIFT_OFFSET_CH1_SET,DITHER_FETCH_SHIFT_OFFSET_CH1_SET" bitfld.long 0x34 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "DITHER_FETCH_SHIFT_OFFSET_CH1_CLR,DITHER_FETCH_SHIFT_OFFSET_CH1_CLR" bitfld.long 0x38 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "DITHER_FETCH_SHIFT_OFFSET_CH1_TOG,DITHER_FETCH_SHIFT_OFFSET_CH1_TOG" bitfld.long 0x3C 24.--28. " OFFSET3 ,Shift offset for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 16.--20. " OFFSET2 ,Shift offset for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 8.--12. " OFFSET1 ,Shift offset for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 0.--4. " OFFSET0 ,Shift offset for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "DITHER_FETCH_SHIFT_WIDTH_CH0,DITHER_FETCH_SHIFT_WIDTH_CH0" bitfld.long 0x40 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "DITHER_FETCH_SHIFT_WIDTH_CH0_SET,DITHER_FETCH_SHIFT_WIDTH_CH0_SET" bitfld.long 0x44 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "DITHER_FETCH_SHIFT_WIDTH_CH0_CLR,DITHER_FETCH_SHIFT_WIDTH_CH0_CLR" bitfld.long 0x48 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "DITHER_FETCH_SHIFT_WIDTH_CH0_TOG,DITHER_FETCH_SHIFT_WIDTH_CH0_TOG" bitfld.long 0x4C 12.--15. " WIDTH3 ,Shift width for channel 0 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 8.--11. " WIDTH2 ,Shift width for channel 0 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 4.--7. " WIDTH1 ,Shift width for channel 0 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 0.--3. " WIDTH0 ,Shift width for channel 0 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x50 "DITHER_FETCH_SHIFT_WIDTH_CH1,DITHER_FETCH_SHIFT_WIDTH_CH1" bitfld.long 0x50 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x54 "DITHER_FETCH_SHIFT_WIDTH_CH1_SET,DITHER_FETCH_SHIFT_WIDTH_CH1_SET" bitfld.long 0x54 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x54 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x58 "DITHER_FETCH_SHIFT_WIDTH_CH1_CLR,DITHER_FETCH_SHIFT_WIDTH_CH1_CLR" bitfld.long 0x58 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x5C "DITHER_FETCH_SHIFT_WIDTH_CH1_TOG,DITHER_FETCH_SHIFT_WIDTH_CH1_TOG" bitfld.long 0x5C 12.--15. " WIDTH3 ,Shift width for channel 1 componnent 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 8.--11. " WIDTH2 ,Shift width for channel 1 componnent 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 4.--7. " WIDTH1 ,Shift width for channel 1 componnent 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x5C 0.--3. " WIDTH0 ,Shift width for channel 1 componnent 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x60 "DITHER_FETCH_ADDR_0_CH0,DITHER_FETCH_ADDR_0_CH0" group.long 0x990++0x03 line.long 0x00 "DITHER_FETCH_ADDR_1_CH0,DITHER_FETCH_ADDR_1_CH0" group.long 0x9A0++0x03 line.long 0x00 "DITHER_FETCH_ADDR_0_CH1,DITHER_FETCH_ADDR_0_CH1" group.long 0x9B0++0x03 line.long 0x00 "DITHER_FETCH_ADDR_1_CH1,DITHER_FETCH_ADDR_1_CH1" group.long 0x9C0++0x1F line.long 0x00 "DITHER_STORE_CTRL_CH0,DITHER_STORE_CTRL_CH0" bitfld.long 0x00 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x00 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x00 11. " FILL_DATA_EN ,Enable bit for fill data" "Disabled,Enabled" bitfld.long 0x00 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x00 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Disabled,Enabled" bitfld.long 0x00 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x00 4. " ARRAY_EN ,Array handshake enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x00 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x00 1. " BLOCK_EN ,Chooses the store mode" "Scan mode,Block mode" newline bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "DITHER_STORE_CTRL_CH0_SET,DITHER_STORE_CTRL_CH0_SET" bitfld.long 0x04 31. " ARBIT_EN ,Arbitration enable" "No effect,Set" bitfld.long 0x04 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "No effect,Set" bitfld.long 0x04 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x04 11. " FILL_DATA_EN ,Enable bit for fill data" "No effect,Set" bitfld.long 0x04 10. " PACK_IN_SEL ,Selects out data to pack" "No effect,Set" bitfld.long 0x04 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Set" newline bitfld.long 0x04 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Set" bitfld.long 0x04 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x04 4. " ARRAY_EN ,Array handshake enable" "No effect,Set" newline bitfld.long 0x04 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Set" bitfld.long 0x04 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x04 1. " BLOCK_EN ,Chooses the store mode" "No effect,Set" newline bitfld.long 0x04 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x08 "DITHER_STORE_CTRL_CH0_CLR,DITHER_STORE_CTRL_CH0_CLR" bitfld.long 0x08 31. " ARBIT_EN ,Arbitration enable" "No effect,Clear" bitfld.long 0x08 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "No effect,Clear" bitfld.long 0x08 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x08 11. " FILL_DATA_EN ,Enable bit for fill data" "No effect,Clear" bitfld.long 0x08 10. " PACK_IN_SEL ,Selects out data to pack" "No effect,Clear" bitfld.long 0x08 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Clear" newline bitfld.long 0x08 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Clear" bitfld.long 0x08 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x08 4. " ARRAY_EN ,Array handshake enable" "No effect,Clear" newline bitfld.long 0x08 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x08 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x08 1. " BLOCK_EN ,Chooses the store mode" "No effect,Clear" newline bitfld.long 0x08 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x0C "DITHER_STORE_CTRL_CH0_TOG,DITHER_STORE_CTRL_CH0_TOG" bitfld.long 0x0C 31. " ARBIT_EN ,Arbitration enable" "Not toggled,Toggled" bitfld.long 0x0C 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Not toggled,Toggled" bitfld.long 0x0C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" newline bitfld.long 0x0C 11. " FILL_DATA_EN ,Enable bit for fill data" "Not toggled,Toggled" bitfld.long 0x0C 10. " PACK_IN_SEL ,Selects out data to pack" "Not toggled,Toggled" bitfld.long 0x0C 9. " STORE_MEMORY_EN ,Store memory enable" "Not toggled,Toggled" newline bitfld.long 0x0C 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Not toggled,Toggled" bitfld.long 0x0C 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x0C 4. " ARRAY_EN ,Array handshake enable" "Not toggled,Toggled" newline bitfld.long 0x0C 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x0C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x0C 1. " BLOCK_EN ,Chooses the store mode" "Not toggled,Toggled" newline bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" line.long 0x10 "DITHER_STORE_CTRL_CH1,Store Engine Control Channel 1 Register" bitfld.long 0x10 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x10 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x10 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x10 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Disabled,Enabled" bitfld.long 0x10 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x10 4. " ARRAY_EN ,Array handshake enable" "Disabled,Enabled" newline bitfld.long 0x10 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Disabled,Enabled" bitfld.long 0x10 2. " BLOCK_16 ,Determines the block size" "8x8,16x16" bitfld.long 0x10 1. " BLOCK_EN ,Chooses the store mode" "Scan mode,Block mode" newline bitfld.long 0x10 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x14 "DITHER_STORE_CTRL_CH1_SET,Store Engine Control Channel 1 Register" bitfld.long 0x14 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x14 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x14 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Set" newline bitfld.long 0x14 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Set" bitfld.long 0x14 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x14 4. " ARRAY_EN ,Array handshake enable" "No effect,Set" newline bitfld.long 0x14 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Set" bitfld.long 0x14 2. " BLOCK_16 ,Determines the block size" "No effect,Set" bitfld.long 0x14 1. " BLOCK_EN ,Chooses the store mode" "No effect,Set" newline bitfld.long 0x14 0. " CH_EN ,Channel enable" "No effect,Set" line.long 0x18 "DITHER_STORE_CTRL_CH1_CLR,Store Engine Control Channel 1 Register" bitfld.long 0x18 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x18 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x18 9. " STORE_MEMORY_EN ,Store memory enable" "No effect,Clear" newline bitfld.long 0x18 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "No effect,Clear" bitfld.long 0x18 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x18 4. " ARRAY_EN ,Array handshake enable" "No effect,Clear" newline bitfld.long 0x18 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "No effect,Clear" bitfld.long 0x18 2. " BLOCK_16 ,Determines the block size" "No effect,Clear" bitfld.long 0x18 1. " BLOCK_EN ,Chooses the store mode" "No effect,Clear" newline bitfld.long 0x18 0. " CH_EN ,Channel enable" "No effect,Clear" line.long 0x1C "DITHER_STORE_CTRL_CH1_TOG,Store Engine Control Channel 1 Register" bitfld.long 0x1C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x1C 10. " PACK_IN_SEL ,Selects out data to pack" "64 bit,Low 32 bit" bitfld.long 0x1C 9. " STORE_MEMORY_EN ,Store memory enable" "Not toggled,Toggled" newline bitfld.long 0x1C 8. " STORE_BYPASS_EN ,Enable bit for store bypass" "Not toggled,Toggled" bitfld.long 0x1C 5.--6. " ARRAY_LINE_NUM ,Selects array size" "1x1,3x3,5x5,5x5" bitfld.long 0x1C 4. " ARRAY_EN ,Array handshake enable" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " HANDSHAKE_EN ,Enable bit for handshake with the store engine" "Not toggled,Toggled" bitfld.long 0x1C 2. " BLOCK_16 ,Determines the block size" "Not toggled,Toggled" bitfld.long 0x1C 1. " BLOCK_EN ,Chooses the store mode" "Not toggled,Toggled" newline bitfld.long 0x1C 0. " CH_EN ,Channel enable" "Not toggled,Toggled" rgroup.long 0x9E0++0x03 line.long 0x00 "DITHER_STORE_STATUS_CH0,Store Engine Status Channel 0 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,In scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" rgroup.long 0x9F0++0x03 line.long 0x00 "DITHER_STORE_STATUS_CH1,Store Engine Status Channel 1 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Scan mode:indicates the current Y coordinate of the frame;block mode:indicates the Y coordinate of the block currently being rendered" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,In scan mode:always 0;block mode:indicates the X coordinate of the block currently being rendered" group.long 0xA00++0x03 line.long 0x00 "DITHER_STORE_SIZE_CH0,DITHER_STORE_SIZE_CH0" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGHT ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0xA10++0x03 line.long 0x00 "DITHER_STORE_SIZE_CH1,DITHER_STORE_SIZE_CH1" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGHT ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0xA20++0x03 line.long 0x00 "DITHER_STORE_PITCH,DITHER_STORE_PITCH" hexmask.long.word 0x00 16.--31. 1. " CH1_OUT_PITCH ,Indicates the channel 1 output pitch" hexmask.long.word 0x00 0.--15. 1. " CH0_OUT_PITCH ,Indicates the channel 0 output pitch" group.long 0xA30++0x1F line.long 0x00 "DITHER_STORE_SHIFT_CTRL_CH0,DITHER_STORE_SHIFT_CTRL_CH0" bitfld.long 0x00 7. " SHIFT_BYPASS ,CH0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x00 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Disabled,Enabled" newline bitfld.long 0x00 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x00 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x04 "DITHER_STORE_SHIFT_CTRL_CH0_SET,DITHER_STORE_SHIFT_CTRL_CH0_SET" bitfld.long 0x04 7. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Set" bitfld.long 0x04 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Set" newline bitfld.long 0x04 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Set" bitfld.long 0x04 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x08 "DITHER_STORE_SHIFT_CTRL_CH0_CLR,DITHER_STORE_SHIFT_CTRL_CH0_CLR" bitfld.long 0x08 7. " SHIFT_BYPASS ,CH0 shift bypass" "No effect,Clear" bitfld.long 0x08 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Clear" newline bitfld.long 0x08 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Clear" bitfld.long 0x08 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x0C "DITHER_STORE_SHIFT_CTRL_CH0_TOG,DITHER_STORE_SHIFT_CTRL_CH0_TOG" bitfld.long 0x0C 7. " SHIFT_BYPASS ,CH0 shift bypass" "Not toggled,Toggled" bitfld.long 0x0C 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Not toggled,Toggled" bitfld.long 0x0C 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x10 "DITHER_STORE_SHIFT_CTRL_CH1,DITHER_STORE_SHIFT_CTRL_CH1" bitfld.long 0x10 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x10 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x10 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x14 "DITHER_STORE_SHIFT_CTRL_CH1_SET,DITHER_STORE_SHIFT_CTRL_CH1_SET" bitfld.long 0x14 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Set" bitfld.long 0x14 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Set" bitfld.long 0x14 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x18 "DITHER_STORE_SHIFT_CTRL_CH1_CLR,DITHER_STORE_SHIFT_CTRL_CH1_CLR" bitfld.long 0x18 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "No effect,Clear" bitfld.long 0x18 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "No effect,Clear" bitfld.long 0x18 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" line.long 0x1C "DITHER_STORE_SHIFT_CTRL_CH1_TOG,DITHER_STORE_SHIFT_CTRL_CH1_TOG" bitfld.long 0x1C 5. " OUT_YUV422_2P_EN ,Enables for YUV422 2 plane" "Not toggled,Toggled" bitfld.long 0x1C 4. " OUT_YUV422_1P_EN ,Enables for YUV422 1 plane" "Not toggled,Toggled" bitfld.long 0x1C 2.--3. " OUTPUT_ACTIVE_BPP ,OUTPUT_ACTIVE_BPP" "8 bits,16 bits,32 bits,32 bits" group.long 0xA90++0x03 line.long 0x00 "DITHER_STORE_ADDR_0_CH0,DITHER_STORE_ADDR_0_CH0" group.long 0xAA0++0x03 line.long 0x00 "DITHER_STORE_ADDR_1_CH0,DITHER_STORE_ADDR_1_CH0" group.long 0xAB0++0x03 line.long 0x00 "DITHER_STORE_FILL_DATA_CH0,DITHER_STORE_FILL_DATA_CH0" group.long 0xAC0++0x03 line.long 0x00 "DITHER_STORE_ADDR_0_CH1,DITHER_STORE_ADDR_0_CH1" group.long 0xAD0++0x03 line.long 0x00 "DITHER_STORE_ADDR_1_CH1,DITHER_STORE_ADDR_1_CH1" group.long 0xAE0++0x03 line.long 0x00 "DITHER_STORE_D_MASK0_H_CH0,DITHER_STORE_D_MASK0_H_CH0" group.long 0xAF0++0x03 line.long 0x00 "DITHER_STORE_D_MASK0_L_CH0,DITHER_STORE_D_MASK0_L_CH0" group.long 0xB00++0x03 line.long 0x00 "DITHER_STORE_D_MASK1_H_CH0,DITHER_STORE_D_MASK1_H_CH0" group.long 0xB10++0x03 line.long 0x00 "DITHER_STORE_D_MASK1_L_CH0,DITHER_STORE_D_MASK1_L_CH0" group.long 0xB20++0x03 line.long 0x00 "DITHER_STORE_D_MASK2_H_CH0,DITHER_STORE_D_MASK2_H_CH0" group.long 0xB30++0x03 line.long 0x00 "DITHER_STORE_D_MASK2_L_CH0,DITHER_STORE_D_MASK2_L_CH0" group.long 0xB40++0x03 line.long 0x00 "DITHER_STORE_D_MASK3_H_CH0,DITHER_STORE_D_MASK3_H_CH0" group.long 0xB50++0x03 line.long 0x00 "DITHER_STORE_D_MASK3_L_CH0,DITHER_STORE_D_MASK3_L_CH0" group.long 0xB60++0x03 line.long 0x00 "DITHER_STORE_D_MASK4_H_CH0,DITHER_STORE_D_MASK4_H_CH0" group.long 0xB70++0x03 line.long 0x00 "DITHER_STORE_D_MASK4_L_CH0,DITHER_STORE_D_MASK4_L_CH0" group.long 0xB80++0x03 line.long 0x00 "DITHER_STORE_D_MASK5_H_CH0,DITHER_STORE_D_MASK5_H_CH0" group.long 0xB90++0x03 line.long 0x00 "DITHER_STORE_D_MASK5_L_CH0,DITHER_STORE_D_MASK5_L_CH0" group.long 0xBA0++0x03 line.long 0x00 "DITHER_STORE_D_MASK6_H_CH0,DITHER_STORE_D_MASK6_H_CH0" group.long 0xBB0++0x03 line.long 0x00 "DITHER_STORE_D_MASK6_L_CH0,DITHER_STORE_D_MASK6_L_CH0" group.long 0xBC0++0x03 line.long 0x00 "DITHER_STORE_D_MASK7_H_CH0,DITHER_STORE_D_MASK7_H_CH0" group.long 0xBD0++0x03 line.long 0x00 "DITHER_STORE_D_MASK7_L_CH0,DITHER_STORE_D_MASK7_L_CH0" group.long 0xBE0++0x03 line.long 0x00 "DITHER_STORE_D_SHIFT_L_CH0,DITHER_STORE_D_SHIFT_L_CH0" bitfld.long 0x00 31. " D_SHIFT_FLAG3 ,Data shift flag 3" "Low,High" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH3 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " D_SHIFT_FLAG2 ,Data shift flag 2" "Low,High" newline bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH2 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " D_SHIFT_FLAG1 ,Data shift flag 1" "Low,High" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH1 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG0 ,Data shift flag 0" "Low,High" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH0 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBF0++0x03 line.long 0x00 "DITHER_STORE_D_SHIFT_H_CH0,DITHER_STORE_D_SHIFT_H_CH0" bitfld.long 0x00 31. " D_SHIFT_FLAG7 ,Data shift flag 7" "Low,High" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH7 ,Data shift width 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " D_SHIFT_FLAG6 ,Data shift flag 6" "Low,High" newline bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH6 ,Data shift width 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " D_SHIFT_FLAG5 ,Data shift flag 5" "Low,High" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH5 ,Data shift width 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG4 ,Data shift flag 4" "Low,High" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH4 ,Data shift width 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC00++0x03 line.long 0x00 "DITHER_STORE_F_SHIFT_L_CH0,DITHER_STORE_F_SHIFT_L_CH0" bitfld.long 0x00 30. " F_SHIFT_FLAG3 ,Flag shift flag3" "Low,High" bitfld.long 0x00 24.--29. " F_SHIFT_WIDTH3 ,Flag shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " F_SHIFT_FLAG2 ,Flag shift flag2" "Low,High" newline bitfld.long 0x00 16.--21. " F_SHIFT_WIDTH2 ,Flag shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. " F_SHIFT_FLAG1 ,Flag shift flag1" "Low,High" bitfld.long 0x00 8.--13. " F_SHIFT_WIDTH1 ,Flag shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6. " F_SHIFT_FLAG0 ,Flag shift flag0" "Low,High" bitfld.long 0x00 0.--5. " F_SHIFT_WIDTH0 ,Flag shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC10++0x03 line.long 0x00 "DITHER_STORE_F_SHIFT_H_CH0,DITHER_STORE_F_SHIFT_H_CH0" bitfld.long 0x00 30. " F_SHIFT_FLAG7 ,Flag shift flag7" "Low,High" bitfld.long 0x00 24.--29. " F_SHIFT_WIDTH7 ,Flag shift width 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " F_SHIFT_FLAG6 ,Flag shift flag6" "Low,High" newline bitfld.long 0x00 16.--21. " F_SHIFT_WIDTH6 ,Flag shift width 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. " F_SHIFT_FLAG5 ,Flag shift flag5" "Low,High" bitfld.long 0x00 8.--13. " F_SHIFT_WIDTH5 ,Flag shift width 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6. " F_SHIFT_FLAG4 ,Flag shift flag4" "Low,High" bitfld.long 0x00 0.--5. " F_SHIFT_WIDTH4 ,Flag shift width 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC20++0x03 line.long 0x00 "DITHER_STORE_F_MASK_L_CH0,DITHER_STORE_F_MASK_L_CH0" hexmask.long.byte 0x00 24.--31. 1. " F_MASK3 ,Flag mask3" hexmask.long.byte 0x00 16.--23. 1. " F_MASK2 ,Flag mask2" newline hexmask.long.byte 0x00 8.--15. 1. " F_MASK1 ,Flag mask1" hexmask.long.byte 0x00 0.--7. 1. " F_MASK0 ,Flag mask0" group.long 0xC30++0x03 line.long 0x00 "DITHER_STORE_F_MASK_H_CH0,DITHER_STORE_F_MASK_H_CH0" hexmask.long.byte 0x00 24.--31. 1. " F_MASK7 ,Flag mask7" hexmask.long.byte 0x00 16.--23. 1. " F_MASK6 ,Flag mask6" newline hexmask.long.byte 0x00 8.--15. 1. " F_MASK5 ,Flag mask5" hexmask.long.byte 0x00 0.--7. 1. " F_MASK4 ,Flag mask4" if ((((per.l(ad:0x30700000+0x1670))&0xE00)==0x600)||(((per.l(ad:0x30700000+0x1670))&0x1C0)==0xC0)||(((per.l(ad:0x30700000+0x1670))&0x38)==0x18)) group.long 0x1670++0x0F line.long 0x00 "DITHER_CTRL,Dither Control Register 0" rbitfld.long 0x00 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "Not busy,Busy" rbitfld.long 0x00 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "Not busy,Busy" rbitfld.long 0x00 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "Not busy,Busy" newline bitfld.long 0x00 24. " ORDERED_ROUND_MODE ,Specifies to use rounding or truncation when calculating the ouptput pixel" "Truncation method,Rounding method" bitfld.long 0x00 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x00 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x00 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x00 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x00 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x00 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x00 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x00 2. " ENABLE2 ,Enables the dither engine 2" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE1 ,Enables the dither engine 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE0 ,Enables the dither engine 0" "Disabled,Enabled" line.long 0x04 "DITHER_CTRL_SET,Dither Control Register 0" bitfld.long 0x04 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "No effect,Set" bitfld.long 0x04 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "No effect,Set" bitfld.long 0x04 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "No effect,Set" newline bitfld.long 0x04 24. " ORDERED_ROUND_MODE ,Specifies to use rounding or truncation when calculating the ouptput pixel" "No effect,Set" bitfld.long 0x04 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "No effect,Set" newline bitfld.long 0x04 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x04 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x04 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x04 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x04 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x04 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x04 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x04 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x04 2. " ENABLE2 ,Enables the dither engine 2" "No effect,Set" bitfld.long 0x04 1. " ENABLE1 ,Enables the dither engine 1" "No effect,Set" bitfld.long 0x04 0. " ENABLE0 ,Enables the dither engine 0" "No effect,Set" line.long 0x08 "DITHER_CTRL_CLR,Dither Control Register 0" bitfld.long 0x08 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "No effect,Clear" bitfld.long 0x08 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "No effect,Clear" bitfld.long 0x08 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "No effect,Clear" newline bitfld.long 0x08 24. " ORDERED_ROUND_MODE ,Specifies to use rounding or truncation when calculating the ouptput pixel" "No effect,Clear" bitfld.long 0x08 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "No effect,Clear" newline bitfld.long 0x08 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x08 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x08 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x08 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x08 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x08 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x08 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x08 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x08 2. " ENABLE2 ,Enables the dither engine 2" "No effect,Clear" bitfld.long 0x08 1. " ENABLE1 ,Enables the dither engine 1" "No effect,Clear" bitfld.long 0x08 0. " ENABLE0 ,Enables the dither engine 0" "No effect,Clear" line.long 0x0C "DITHER_CTRL_TOG,Dither Control Register 0" bitfld.long 0x0C 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "Not toggled,Toggled" bitfld.long 0x0C 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "Not toggled,Toggled" bitfld.long 0x0C 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "Not toggled,Toggled" newline bitfld.long 0x0C 24. " ORDERED_ROUND_MODE ,Specifies to use rounding or truncation when calculating the ouptput pixel" "Not toggled,Toggled" bitfld.long 0x0C 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "Not toggled,Toggled" newline bitfld.long 0x0C 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x0C 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x0C 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x0C 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x0C 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x0C 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x0C 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x0C 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x0C 2. " ENABLE2 ,Enables the dither engine 2" "Not toggled,Toggled" bitfld.long 0x0C 1. " ENABLE1 ,Enables the dither engine 1" "Not toggled,Toggled" bitfld.long 0x0C 0. " ENABLE0 ,Enables the dither engine 0" "Not toggled,Toggled" else group.long 0x1670++0x0F line.long 0x00 "DITHER_CTRL,Dither Control Register 0" rbitfld.long 0x00 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "Not busy,Busy" rbitfld.long 0x00 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "Not busy,Busy" rbitfld.long 0x00 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "Not busy,Busy" newline bitfld.long 0x00 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x00 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x00 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x00 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x00 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x00 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x00 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x00 2. " ENABLE2 ,Enables the dither engine 2" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE1 ,Enables the dither engine 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE0 ,Enables the dither engine 0" "Disabled,Enabled" line.long 0x04 "DITHER_CTRL_SET,Dither Control Register 0" bitfld.long 0x04 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "No effect,Set" bitfld.long 0x04 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "No effect,Set" bitfld.long 0x04 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "No effect,Set" newline bitfld.long 0x04 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "No effect,Set" newline bitfld.long 0x04 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x04 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x04 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x04 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x04 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x04 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x04 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x04 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x04 2. " ENABLE2 ,Enables the dither engine 2" "No effect,Set" bitfld.long 0x04 1. " ENABLE1 ,Enables the dither engine 1" "No effect,Set" bitfld.long 0x04 0. " ENABLE0 ,Enables the dither engine 0" "No effect,Set" line.long 0x08 "DITHER_CTRL_CLR,Dither Control Register 0" bitfld.long 0x08 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "No effect,Clear" bitfld.long 0x08 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "No effect,Clear" bitfld.long 0x08 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "No effect,Clear" newline bitfld.long 0x08 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "No effect,Clear" newline bitfld.long 0x08 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x08 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x08 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x08 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x08 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x08 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x08 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x08 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x08 2. " ENABLE2 ,Enables the dither engine 2" "No effect,Clear" bitfld.long 0x08 1. " ENABLE1 ,Enables the dither engine 1" "No effect,Clear" bitfld.long 0x08 0. " ENABLE0 ,Enables the dither engine 0" "No effect,Clear" line.long 0x0C "DITHER_CTRL_TOG,Dither Control Register 0" bitfld.long 0x0C 31. " BUSY0 ,Indicates if the dither engine 0 is busy" "Not toggled,Toggled" bitfld.long 0x0C 30. " BUSY1 ,Indicates if the dither engine 1 is busy" "Not toggled,Toggled" bitfld.long 0x0C 29. " BUSY2 ,Indicates if the dither engine 2 is busy" "Not toggled,Toggled" newline bitfld.long 0x0C 23. " FINAL_LUT_ENABLE ,Enables a final stage register based LUT at the last stage before output" "Not toggled,Toggled" newline bitfld.long 0x0C 21.--22. " IDX_MATRIX2_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 2" "4x4,8x8,16x16,Input value of index" bitfld.long 0x0C 19.--20. " IDX_MATRIX1_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 1" "4x4,8x8,16x16,Input value of index" bitfld.long 0x0C 17.--18. " IDX_MATRIX0_SIZE ,Specifies the dimension of the index matrix in the LUT memory so proper indexing can occur for dither engine 0" "4x4,8x8,16x16,Input value of index" newline bitfld.long 0x0C 15.--16. " LUT_MODE ,Specifies to use memory LUT to transform pixel" "Off,Pre-diter stage,Post-diter stage,?..." bitfld.long 0x0C 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" ",1,2,3,4,5,6,7" newline bitfld.long 0x0C 9.--11. " DITHER_MODE2 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x0C 6.--8. " DITHER_MODE1 ,Dither mode" "Pass through,,,Ordered,No dithering,?..." bitfld.long 0x0C 3.--5. " DITHER_MODE0 ,Dither mode" "Pass through,Floyd-steinberg,Atkinson,Ordered,No dithering,?..." newline bitfld.long 0x0C 2. " ENABLE2 ,Enables the dither engine 2" "Not toggled,Toggled" bitfld.long 0x0C 1. " ENABLE1 ,Enables the dither engine 1" "Not toggled,Toggled" bitfld.long 0x0C 0. " ENABLE0 ,Enables the dither engine 0" "Not toggled,Toggled" endif newline group.long 0x1680++0x3F line.long 0x00 "DITHER_FINAL_LUT_DATA0,Final Stage Lookup Value Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Final stage LUT data value" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Final stage LUT data value" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Final stage LUT data value" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Final stage LUT data value" line.long 0x04 "DITHER_FINAL_LUT_DATA0_SET,Final Stage Lookup Value Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Final stage LUT data value" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Final stage LUT data value" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Final stage LUT data value" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Final stage LUT data value" line.long 0x08 "DITHER_FINAL_LUT_DATA0_CLR,Final Stage Lookup Value Register" hexmask.long.byte 0x08 24.--31. 1. " DATA3 ,Final stage LUT data value" hexmask.long.byte 0x08 16.--23. 1. " DATA2 ,Final stage LUT data value" hexmask.long.byte 0x08 8.--15. 1. " DATA1 ,Final stage LUT data value" hexmask.long.byte 0x08 0.--7. 1. " DATA0 ,Final stage LUT data value" line.long 0x0C "DITHER_FINAL_LUT_DATA0_TOG,Final Stage Lookup Value Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA3 ,Final stage LUT data value" hexmask.long.byte 0x0C 16.--23. 1. " DATA2 ,Final stage LUT data value" hexmask.long.byte 0x0C 8.--15. 1. " DATA1 ,Final stage LUT data value" hexmask.long.byte 0x0C 0.--7. 1. " DATA0 ,Final stage LUT data value" line.long 0x10 "DITHER_FINAL_LUT_DATA1,Final Stage Lookup Value Register" hexmask.long.byte 0x10 24.--31. 1. " DATA7 ,Final stage LUT data value" hexmask.long.byte 0x10 16.--23. 1. " DATA6 ,Final stage LUT data value" hexmask.long.byte 0x10 8.--15. 1. " DATA5 ,Final stage LUT data value" hexmask.long.byte 0x10 0.--7. 1. " DATA4 ,Final stage LUT data value" line.long 0x14 "DITHER_FINAL_LUT_DATA1_SET,Final Stage Lookup Value Register" hexmask.long.byte 0x14 24.--31. 1. " DATA7 ,Final stage LUT data value" hexmask.long.byte 0x14 16.--23. 1. " DATA6 ,Final stage LUT data value" hexmask.long.byte 0x14 8.--15. 1. " DATA5 ,Final stage LUT data value" hexmask.long.byte 0x14 0.--7. 1. " DATA4 ,Final stage LUT data value" line.long 0x18 "DITHER_FINAL_LUT_DATA1_CLR,Final Stage Lookup Value Register" hexmask.long.byte 0x18 24.--31. 1. " DATA7 ,Final stage LUT data value" hexmask.long.byte 0x18 16.--23. 1. " DATA6 ,Final stage LUT data value" hexmask.long.byte 0x18 8.--15. 1. " DATA5 ,Final stage LUT data value" hexmask.long.byte 0x18 0.--7. 1. " DATA4 ,Final stage LUT data value" line.long 0x1C "DITHER_FINAL_LUT_DATA1_TOG,Final Stage Lookup Value Register" hexmask.long.byte 0x1C 24.--31. 1. " DATA7 ,Final stage LUT data value" hexmask.long.byte 0x1C 16.--23. 1. " DATA6 ,Final stage LUT data value" hexmask.long.byte 0x1C 8.--15. 1. " DATA5 ,Final stage LUT data value" hexmask.long.byte 0x1C 0.--7. 1. " DATA4 ,Final stage LUT data value" line.long 0x20 "DITHER_FINAL_LUT_DATA2,Final Stage Lookup Value Register" hexmask.long.byte 0x20 24.--31. 1. " DATA11 ,Final stage LUT data value" hexmask.long.byte 0x20 16.--23. 1. " DATA10 ,Final stage LUT data value" hexmask.long.byte 0x20 8.--15. 1. " DATA9 ,Final stage LUT data value" hexmask.long.byte 0x20 0.--7. 1. " DATA8 ,Final stage LUT data value" line.long 0x24 "DITHER_FINAL_LUT_DATA2_SET,Final Stage Lookup Value Register" hexmask.long.byte 0x24 24.--31. 1. " DATA11 ,Final stage LUT data value" hexmask.long.byte 0x24 16.--23. 1. " DATA10 ,Final stage LUT data value" hexmask.long.byte 0x24 8.--15. 1. " DATA9 ,Final stage LUT data value" hexmask.long.byte 0x24 0.--7. 1. " DATA8 ,Final stage LUT data value" line.long 0x28 "DITHER_FINAL_LUT_DATA2_CLR,Final Stage Lookup Value Register" hexmask.long.byte 0x28 24.--31. 1. " DATA11 ,Final stage LUT data value" hexmask.long.byte 0x28 16.--23. 1. " DATA10 ,Final stage LUT data value" hexmask.long.byte 0x28 8.--15. 1. " DATA9 ,Final stage LUT data value" hexmask.long.byte 0x28 0.--7. 1. " DATA8 ,Final stage LUT data value" line.long 0x2C "DITHER_FINAL_LUT_DATA2_TOG,Final Stage Lookup Value Register" hexmask.long.byte 0x2C 24.--31. 1. " DATA11 ,Final stage LUT data value" hexmask.long.byte 0x2C 16.--23. 1. " DATA10 ,Final stage LUT data value" hexmask.long.byte 0x2C 8.--15. 1. " DATA9 ,Final stage LUT data value" hexmask.long.byte 0x2C 0.--7. 1. " DATA8 ,Final stage LUT data value" line.long 0x30 "DITHER_FINAL_LUT_DATA3,Final Stage Lookup Value Register" hexmask.long.byte 0x30 24.--31. 1. " DATA15 ,Final stage LUT data value" hexmask.long.byte 0x30 16.--23. 1. " DATA14 ,Final stage LUT data value" hexmask.long.byte 0x30 8.--15. 1. " DATA13 ,Final stage LUT data value" hexmask.long.byte 0x30 0.--7. 1. " DATA12 ,Final stage LUT data value" line.long 0x34 "DITHER_FINAL_LUT_DATA3_SET,Final Stage Lookup Value Register" hexmask.long.byte 0x34 24.--31. 1. " DATA15 ,Final stage LUT data value" hexmask.long.byte 0x34 16.--23. 1. " DATA14 ,Final stage LUT data value" hexmask.long.byte 0x34 8.--15. 1. " DATA13 ,Final stage LUT data value" hexmask.long.byte 0x34 0.--7. 1. " DATA12 ,Final stage LUT data value" line.long 0x38 "DITHER_FINAL_LUT_DATA3_CLR,Final Stage Lookup Value Register" hexmask.long.byte 0x38 24.--31. 1. " DATA15 ,Final stage LUT data value" hexmask.long.byte 0x38 16.--23. 1. " DATA14 ,Final stage LUT data value" hexmask.long.byte 0x38 8.--15. 1. " DATA13 ,Final stage LUT data value" hexmask.long.byte 0x38 0.--7. 1. " DATA12 ,Final stage LUT data value" line.long 0x3C "DITHER_FINAL_LUT_DATA3_TOG,Final Stage Lookup Value Register" hexmask.long.byte 0x3C 24.--31. 1. " DATA15 ,Final stage LUT data value" hexmask.long.byte 0x3C 16.--23. 1. " DATA14 ,Final stage LUT data value" hexmask.long.byte 0x3C 8.--15. 1. " DATA13 ,Final stage LUT data value" hexmask.long.byte 0x3C 0.--7. 1. " DATA12 ,Final stage LUT data value" tree.end width 25. newline group.long 0x2A00++0x03 line.long 0x00 "HIST_A_CTRL,Histogram Control Register" bitfld.long 0x00 24.--26. " PIXEL_WIDTH ,The width of the pixel to be used for histogram calculation" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--22. 1. " PIXEL_OFFSET ,The offset of the pixel to be used for histogram calculation" rbitfld.long 0x00 12. " STATUS[12] ,Indicates that the bitmap pixels were fully contained within the HIST32 (5-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 11. " STATUS[11] ,Indicates that the bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 10. " STATUS[10] ,Indicates that the bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 9. " STATUS[9] ,Indicates that the bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not full,Full" bitfld.long 0x00 8. " STATUS[8] ,Indicates that the bitmap pixels were fully contained within the HIST2 (Black / white) histogram" "Not full,Full" eventfld.long 0x00 4. " CLEAR ,Clears the histogram result" "No effect,Clear" newline bitfld.long 0x00 0. " ENABLE ,Enables the histogram engine" "Disabled,Enabled" group.long 0x2A10++0x03 line.long 0x00 "HIST_A_MASK,Histogram Pixel Mask Register" hexmask.long.byte 0x00 24.--31. 1. " MASK_VALUE1 ,The value1 for mask condition checking" hexmask.long.byte 0x00 16.--23. 1. " MASK_VALUE0 ,The value0 for mask condition checking" bitfld.long 0x00 13.--15. " MASK_WIDTH ,The width of the field to be checked against mask condition" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 6.--12. 1. " MASK_OFFSET ,The offset of the field to be checked against mask condition" newline bitfld.long 0x00 4.--5. " MASK_MODE ,Operation mode of pixel mask function" "EQUAL,NOT_EQUAL,INSIDE,OUTSIDE" bitfld.long 0x00 0. " MASK_EN ,Enables the pixel mask function in histogram" "Disabled,Enabled" group.long 0x2A20++0x03 line.long 0x00 "HIST_A_BUF_SIZE,Histogram Pixel Buffer Size Register" hexmask.long.word 0x00 16.--27. 1. " HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--11. 1. " WIDTH ,Indicates the buffer width in pixels" rgroup.long 0x2A30++0x03 line.long 0x00 "HIST_A_TOTAL_PIXEL,Total Number Of Pixels Used By Histogram Engine" hexmask.long.tbyte 0x00 0.--23. 1. " TOTAL_PIXEL ,Total number of pixels used by histogram engine, the pixels got masked will be skipped" rgroup.long 0x2A40++0x03 line.long 0x00 "HIST_A_ACTIVE_AREA_X,The X Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_X_OFFSET ,Maximum X coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_X_OFFSET ,Minimul X coordinate offset for the active area in histogram processing" rgroup.long 0x2A50++0x03 line.long 0x00 "HIST_A_ACTIVE_AREA_Y,The Y Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_Y_OFFSET ,Maximum Y coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_Y_OFFSET ,Minimul Y coordinate offset for the active area in histogram processing" rgroup.long 0x2A60++0x03 line.long 0x00 "HIST_A_RAW_STAT0,Histogram Result Based On RAW Pixel Value" rgroup.long 0x2A70++0x03 line.long 0x00 "HIST_A_RAW_STAT1,Histogram Result Based On RAW Pixel Value" group.long 0x2A80++0x03 line.long 0x00 "HIST_B_CTRL,Histogram Control Register" bitfld.long 0x00 24.--26. " PIXEL_WIDTH ,The width of the pixel to be used for histogram calculation" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--22. 1. " PIXEL_OFFSET ,The offset of the pixel to be used for histogram calculation" rbitfld.long 0x00 12. " STATUS[12] ,Indicates that the bitmap pixels were fully contained within the HIST32 (5-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 11. " STATUS[11] ,Indicates that the bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 10. " STATUS[10] ,Indicates that the bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 9. " STATUS[9] ,Indicates that the bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not full,Full" bitfld.long 0x00 8. " STATUS[8] ,Indicates that the bitmap pixels were fully contained within the HIST2 (Black / white) histogram" "Not full,Full" eventfld.long 0x00 4. " CLEAR ,Clears the histogram result" "No effect,Clear" newline bitfld.long 0x00 0. " ENABLE ,Enables the histogram engine" "Disabled,Enabled" group.long 0x2A90++0x03 line.long 0x00 "HIST_B_MASK,Histogram Pixel Mask Register" hexmask.long.byte 0x00 24.--31. 1. " MASK_VALUE1 ,The value1 for mask condition checking" hexmask.long.byte 0x00 16.--23. 1. " MASK_VALUE0 ,The value0 for mask condition checking" bitfld.long 0x00 13.--15. " MASK_WIDTH ,The width of the field to be checked against mask condition" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 6.--12. 1. " MASK_OFFSET ,The offset of the field to be checked against mask condition" newline bitfld.long 0x00 4.--5. " MASK_MODE ,Operation mode of pixel mask function" "EQUAL,NOT_EQUAL,INSIDE,OUTSIDE" bitfld.long 0x00 0. " MASK_EN ,Enables the pixel mask function in histogram" "Disabled,Enabled" group.long 0x2AA0++0x03 line.long 0x00 "HIST_B_BUF_SIZE,Histogram Pixel Buffer Size Register" hexmask.long.word 0x00 16.--27. 1. " HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--11. 1. " WIDTH ,Indicates the buffer width in pixels" rgroup.long 0x2AB0++0x03 line.long 0x00 "HIST_B_TOTAL_PIXEL,Total Number Of Pixels Used By Histogram Engine" hexmask.long.tbyte 0x00 0.--23. 1. " TOTAL_PIXEL ,Total number of pixels used by histogram engine, the pixels got masked will be skipped" rgroup.long 0x2AC0++0x03 line.long 0x00 "HIST_B_ACTIVE_AREA_X,The X Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_X_OFFSET ,Maximum X coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_X_OFFSET ,Minimul X coordinate offset for the active area in histogram processing" rgroup.long 0x2AD0++0x03 line.long 0x00 "HIST_B_ACTIVE_AREA_Y,The Y Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_Y_OFFSET ,Maximum Y coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_Y_OFFSET ,Minimul Y coordinate offset for the active area in histogram processing" rgroup.long 0x2AE0++0x03 line.long 0x00 "HIST_B_RAW_STAT0,Histogram Result Based On RAW Pixel Value" rgroup.long 0x2AF0++0x03 line.long 0x00 "HIST_B_RAW_STAT1,Histogram Result Based On RAW Pixel Value" newline group.long 0x2B00++0x03 line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register" bitfld.long 0x00 8.--13. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B10++0x03 line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B20++0x03 line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B30++0x03 line.long 0x00 "HIST8_PARAM1,8-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B40++0x03 line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B50++0x03 line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B60++0x03 line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B70++0x03 line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B80++0x03 line.long 0x00 "HIST32_PARAM0,32-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B90++0x03 line.long 0x00 "HIST32_PARAM1,32-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BA0++0x03 line.long 0x00 "HIST32_PARAM2,32-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE11 ,GRAY11 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE10 ,GRAY10 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE9 ,GRAY9 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE8 ,GRAY8 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BB0++0x03 line.long 0x00 "HIST32_PARAM3,32-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE15 ,GRAY15 (White) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE14 ,GRAY14 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE13 ,GRAY13 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE12 ,GRAY12 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BC0++0x03 line.long 0x00 "HIST32_PARAM4,32-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE19 ,GRAY19 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE18 ,GRAY18 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE17 ,GRAY17 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE16 ,GRAY16 (Black) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BD0++0x03 line.long 0x00 "HIST32_PARAM5,32-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE23 ,GRAY23 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE22 ,GRAY22 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE21 ,GRAY21 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE20 ,GRAY20 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BE0++0x03 line.long 0x00 "HIST32_PARAM6,32-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE27 ,GRAY27 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE26 ,GRAY26 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE25 ,GRAY25 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE24 ,GRAY24 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BF0++0x03 line.long 0x00 "HIST32_PARAM7,32-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE31 ,GRAY31 (White) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE30 ,GRAY30 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE29 ,GRAY29 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE28 ,GRAY28 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline group.long 0x2C00++0x23 line.long 0x00 "COMP_CTRL,COMP_CTRL" bitfld.long 0x00 8. " SW_RESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " START ,Start operation" "No start,Start" line.long 0x04 "COMP_CTRL_SET,COMP_CTRL_SET" bitfld.long 0x04 8. " SW_RESET ,Software reset" "No effect,Set" bitfld.long 0x04 0. " START ,Start operation" "No effect,Set" line.long 0x08 "COMP_CTRL_CLR,COMP_CTRL_CLR" bitfld.long 0x08 8. " SW_RESET ,Software reset" "No effect,Clear" bitfld.long 0x08 0. " START ,Start operation" "No effect,Clear" line.long 0x0C "COMP_CTRL_TOG,COMP_CTRL_TOG" bitfld.long 0x0C 8. " SW_RESET ,Software reset" "Not toggled,Toggled" bitfld.long 0x0C 0. " START ,Start operation" "Not toggled,Toggled" line.long 0x10 "COMP_FORMAT0,COMP_FORMAT0" rbitfld.long 0x10 27. " FIFOFULL ,Fifo full" "Not full,Full" rbitfld.long 0x10 26. " ERR_PRONE ,ERR_PRONE" "No error,Error" hexmask.long.word 0x10 16.--25. 1. " PIXEL_PITCH_64B ,Extends each line to be 64-bit aligned" bitfld.long 0x10 8.--9. " MASK_INDEX ,MASK_INDEX" "A,B,C,D" newline bitfld.long 0x10 4.--5. " FIELD_NUM ,FIELD_NUM" "Only A,AB,ABC,ABCD" bitfld.long 0x10 0. " FLAG_32B ,FLAG_32B" "16-bit,32-bit" line.long 0x14 "COMP_FORMAT0_SET,COMP_FORMAT0_SET" bitfld.long 0x14 27. " FIFOFULL ,Fifo full" "No effect,Set" bitfld.long 0x14 26. " ERR_PRONE ,ERR_PRONE" "No effect,Set" hexmask.long.word 0x14 16.--25. 1. " PIXEL_PITCH_64B ,Extends each line to be 64-bit aligned" bitfld.long 0x14 8.--9. " MASK_INDEX ,MASK_INDEX" "A,B,C,D" newline bitfld.long 0x14 4.--5. " FIELD_NUM ,FIELD_NUM" "Only A,AB,ABC,ABCD" bitfld.long 0x14 0. " FLAG_32B ,FLAG_32B" "No effect,Set" line.long 0x18 "COMP_FORMAT0_CLR,COMP_FORMAT0_CLR" bitfld.long 0x18 27. " FIFOFULL ,Fifo full" "No effect,Clear" bitfld.long 0x18 26. " ERR_PRONE ,ERR_PRONE" "No effect,Clear" hexmask.long.word 0x18 16.--25. 1. " PIXEL_PITCH_64B ,Extends each line to be 64-bit aligned" bitfld.long 0x18 8.--9. " MASK_INDEX ,MASK_INDEX" "A,B,C,D" newline bitfld.long 0x18 4.--5. " FIELD_NUM ,FIELD_NUM" "Only A,AB,ABC,ABCD" bitfld.long 0x18 0. " FLAG_32B ,FLAG_32B" "No effect,Clear" line.long 0x1C "COMP_FORMAT0_TOG,COMP_FORMAT0_TOG" bitfld.long 0x1C 27. " FIFOFULL ,Fifo full" "Not toggled,Toggled" bitfld.long 0x1C 26. " ERR_PRONE ,ERR_PRONE" "Not toggled,Toggled" hexmask.long.word 0x1C 16.--25. 1. " PIXEL_PITCH_64B ,Extends each line to be 64-bit aligned" bitfld.long 0x1C 8.--9. " MASK_INDEX ,MASK_INDEX" "A,B,C,D" newline bitfld.long 0x1C 4.--5. " FIELD_NUM ,FIELD_NUM" "Only A,AB,ABC,ABCD" bitfld.long 0x1C 0. " FLAG_32B ,FLAG_32B" "Not toggled,Toggled" line.long 0x20 "COMP_FORMAT1,COMP_FORMAT1" bitfld.long 0x20 29.--31. " D_LEN ,Length of field D" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" bitfld.long 0x20 24.--28. " D_OFFSET ,Offset for field D" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 21.--23. " C_LEN ,Length of field C" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" bitfld.long 0x20 16.--20. " C_OFFSET ,Offset for field C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 13.--15. " B_LEN ,Length of field B" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" bitfld.long 0x20 8.--12. " B_OFFSET ,Offset for field B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 5.--7. " A_LEN ,Length of field A" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" bitfld.long 0x20 0.--4. " A_OFFSET ,Offset for field A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C30++0x03 line.long 0x00 "COMP_FORMAT2,COMP_FORMAT2" bitfld.long 0x00 12.--15. " D_RUNLEN ,Length of the RLE for field D max 12 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 8.--11. " C_RUNLEN ,Length of the RLE for field C max 12 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 4.--7. " B_RUNLEN ,Length of the RLE for field B max 12 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 0.--3. " A_RUNLEN ,Length of the RLE for field A max 12 bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." group.long 0x2C40++0x03 line.long 0x00 "COMP_MASK0,COMP_MASK0" group.long 0x2C50++0x03 line.long 0x00 "COMP_MASK1,COMP_MASK1" group.long 0x2C60++0x03 line.long 0x00 "COMP_BUFFER_SIZE,COMP_BUFFER_SIZE" hexmask.long.word 0x00 16.--28. 1. " PIXEL_WIDTH ,Pixel width of the input frame (4096 max)" hexmask.long.word 0x00 0.--12. 1. " PIXEL_LENGTH ,Pixel length of the input frame (4096 max)" group.long 0x2C70++0x03 line.long 0x00 "COMP_SOURCE,COMP_SOURCE" group.long 0x2C80++0x03 line.long 0x00 "COMP_TARGET,COMP_TARGET" group.long 0x2C90++0x03 line.long 0x00 "COMP_BUFFER_A,COMP_BUFFER_A" group.long 0x2CA0++0x03 line.long 0x00 "COMP_BUFFER_B,COMP_BUFFER_B" group.long 0x2CB0++0x03 line.long 0x00 "COMP_BUFFER_C,COMP_BUFFER_C" group.long 0x2CC0++0x03 line.long 0x00 "COMP_BUFFER_D,COMP_BUFFER_D" newline group.long 0x2CD0++0x03 line.long 0x00 "COMP_DEBUG,COMP_DEBUG" hexmask.long.tbyte 0x00 8.--31. 1. " DEBUG_VALUE ,Value of selected debug signal" hexmask.long.byte 0x00 0.--7. 1. " DEBUG_SEL ,Debug selection" group.long 0x2CE0++0x03 line.long 0x00 "BUS_MUX,BUS_MUX" hexmask.long.byte 0x00 16.--23. 1. " WR_SEL ,Subblocks BUS to AXI MUX by setting 0 to axi0 and setting 1 to axi1" hexmask.long.byte 0x00 0.--7. 1. " RD_SEL ,Subblocks BUS to AXI MUX by setting 0 to axi0 and setting 1 to axi1" group.long 0x2CF0++0x03 line.long 0x00 "HANDSHAKE_READY_MUX0,HANDSHAKE_READY_MUX0" bitfld.long 0x00 28.--31. " HSK7 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 24.--27. " HSK6 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 20.--23. " HSK5 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 16.--19. " HSK4 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 12.--15. " HSK3 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 8.--11. " HSK2 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 4.--7. " HSK1 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 0.--3. " HSK0 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." group.long 0x2D00++0x03 line.long 0x00 "HANDSHAKE_READY_MUX1,HANDSHAKE_READY_MUX1" bitfld.long 0x00 28.--31. " HSK15 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 24.--27. " HSK14 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 20.--23. " HSK13 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 16.--19. " HSK12 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 12.--15. " HSK11 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 8.--11. " HSK10 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 4.--7. " HSK9 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 0.--3. " HSK8 ,Subblocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." group.long 0x2D10++0x03 line.long 0x00 "HANDSHAKE_DONE_MUX0,HANDSHAKE_DONE_MUX0" bitfld.long 0x00 28.--31. " HSK7 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 24.--27. " HSK6 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 20.--23. " HSK5 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 16.--19. " HSK4 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 12.--15. " HSK3 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 8.--11. " HSK2 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 4.--7. " HSK1 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 0.--3. " HSK0 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." group.long 0x2D20++0x03 line.long 0x00 "HANDSHAKE_DONE_MUX1,HANDSHAKE_DONE_MUX1" bitfld.long 0x00 28.--31. " HSK15 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 24.--27. " HSK14 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 20.--23. " HSK13 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 16.--19. " HSK12 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 12.--15. " HSK11 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 8.--11. " HSK10 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 4.--7. " HSK9 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 0.--3. " HSK8 ,Subblocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline group.long 0x2D30++0x1F line.long 0x00 "HANDSHAKE_CPU_FETCH,HANDSHAKE_CPU_FETCH" bitfld.long 0x00 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x00 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "Not done,Done" bitfld.long 0x00 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "Not done,Done" newline rbitfld.long 0x00 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "Not ready,Ready" rbitfld.long 0x00 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "Not ready,Ready" newline bitfld.long 0x00 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x00 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "Not done,Done" bitfld.long 0x00 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "Not done,Done" newline rbitfld.long 0x00 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "Not ready,Ready" rbitfld.long 0x00 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "Not ready,Ready" line.long 0x04 "HANDSHAKE_CPU_FETCH_SET,HANDSHAKE_CPU_FETCH_SET" bitfld.long 0x04 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "No effect,Set" bitfld.long 0x04 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x04 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Set" bitfld.long 0x04 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Set" newline bitfld.long 0x04 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Set" bitfld.long 0x04 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Set" newline bitfld.long 0x04 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "No effect,Set" bitfld.long 0x04 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x04 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Set" bitfld.long 0x04 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Set" newline bitfld.long 0x04 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Set" bitfld.long 0x04 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Set" line.long 0x08 "HANDSHAKE_CPU_FETCH_CLR,HANDSHAKE_CPU_FETCH_CLR" bitfld.long 0x08 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "No effect,Clear" bitfld.long 0x08 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x08 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Clear" bitfld.long 0x08 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Clear" newline bitfld.long 0x08 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Clear" bitfld.long 0x08 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Clear" newline bitfld.long 0x08 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "No effect,Clear" bitfld.long 0x08 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x08 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Clear" bitfld.long 0x08 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Clear" newline bitfld.long 0x08 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Clear" bitfld.long 0x08 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Clear" line.long 0x0C "HANDSHAKE_CPU_FETCH_TOG,HANDSHAKE_CPU_FETCH_TOG" bitfld.long 0x0C 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "Not toggled,Toggled" bitfld.long 0x0C 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x0C 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "Not toggled,Toggled" bitfld.long 0x0C 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "Not toggled,Toggled" bitfld.long 0x0C 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "Not toggled,Toggled" newline bitfld.long 0x0C 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "Not toggled,Toggled" bitfld.long 0x0C 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x0C 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "Not toggled,Toggled" bitfld.long 0x0C 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "Not toggled,Toggled" bitfld.long 0x0C 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "Not toggled,Toggled" line.long 0x10 "HANDSHAKE_CPU_STORE,HANDSHAKE_CPU_STORE" bitfld.long 0x10 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "Disabled,Enabled" rbitfld.long 0x10 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." rbitfld.long 0x10 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "Not done,Done" rbitfld.long 0x10 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "Not done,Done" newline bitfld.long 0x10 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "Not ready,Ready" bitfld.long 0x10 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "Not ready,Ready" newline bitfld.long 0x10 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "Disabled,Enabled" rbitfld.long 0x10 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." rbitfld.long 0x10 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "Not done,Done" rbitfld.long 0x10 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "Not done,Done" newline bitfld.long 0x10 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "Not ready,Ready" bitfld.long 0x10 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "Not ready,Ready" line.long 0x14 "HANDSHAKE_CPU_STORE_SET,HANDSHAKE_CPU_STORE_SET" bitfld.long 0x14 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "No effect,Set" bitfld.long 0x14 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x14 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Set" bitfld.long 0x14 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Set" newline bitfld.long 0x14 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Set" bitfld.long 0x14 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Set" newline bitfld.long 0x14 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "No effect,Set" bitfld.long 0x14 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x14 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Set" bitfld.long 0x14 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Set" newline bitfld.long 0x14 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Set" bitfld.long 0x14 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Set" line.long 0x18 "HANDSHAKE_CPU_STORE_CLR,HANDSHAKE_CPU_STORE_CLR" bitfld.long 0x18 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "No effect,Clear" bitfld.long 0x18 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x18 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Clear" bitfld.long 0x18 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Clear" newline bitfld.long 0x18 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Clear" bitfld.long 0x18 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Clear" newline bitfld.long 0x18 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "No effect,Clear" bitfld.long 0x18 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x18 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "No effect,Clear" bitfld.long 0x18 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "No effect,Clear" newline bitfld.long 0x18 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "No effect,Clear" bitfld.long 0x18 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "No effect,Clear" line.long 0x1C "HANDSHAKE_CPU_STORE_TOG,HANDSHAKE_CPU_STORE_TOG" bitfld.long 0x1C 31. " SW1_HSK_EN ,Enables software handshake 1 with CPU" "Not toggled,Toggled" bitfld.long 0x1C 20.--21. " SW1_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x1C 19. " SW1_B1_DONE ,CPU b1 buffer done to PXP" "Not toggled,Toggled" bitfld.long 0x1C 18. " SW1_B0_DONE ,CPU b0 buffer done to PXP" "Not toggled,Toggled" newline bitfld.long 0x1C 17. " SW1_B1_READY ,PXP b1 buffer ready to CPU" "Not toggled,Toggled" bitfld.long 0x1C 16. " SW1_B0_READY ,PXP b0 buffer ready to CPU" "Not toggled,Toggled" newline bitfld.long 0x1C 15. " SW0_HSK_EN ,Enables software handshake 0 with CPU" "Not toggled,Toggled" bitfld.long 0x1C 4.--5. " SW0_BUF_LINES ,Buffer lines for software handshake" "LINE_4,LINE_8,LINE_16,?..." bitfld.long 0x1C 3. " SW0_B1_DONE ,CPU b1 buffer done to PXP" "Not toggled,Toggled" bitfld.long 0x1C 2. " SW0_B0_DONE ,CPU b0 buffer done to PXP" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " SW0_B1_READY ,PXP b1 buffer ready to CPU" "Not toggled,Toggled" bitfld.long 0x1C 0. " SW0_B0_READY ,PXP b0 buffer ready to CPU" "Not toggled,Toggled" width 0x0B tree.end tree.open "SAI (Synchronous Audio Interface)" tree "I2S1" base ad:0x308A0000 width 6. sif cpuis("K32W0?2S1M*") rgroup.long (-0x08)++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x00++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled transmit FIFO has underrun" "No underrun,Underrun" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled transmit FIFO is empty" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled transmit channel FIFO is less than or equal to the transmit FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308A0000))&0x80000000)==0x80000000) rgroup.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register" sif cpuis("K32W0?2S1M*") wgroup.long 0x24++0x03 line.long 0x00 "TDR1,SAI Transmit Data Register 1" endif sif !cpuis("K32W0?2S1M*") rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register" hexmask.long.byte 0x00 16.--21. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 1. " RFP ,Read FIFO pointer" endif sif cpuis("K32W0?2S1M*") rgroup.long 0x40++0x07 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 1. " RFP ,Read FIFO pointer" line.long 0x04 "TFR1,SAI Transmit FIFO Register 1" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x04 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 1. " RFP ,Read FIFO pointer" endif group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word mask 0" "Not masked,Masked" group.long 0x80++0x03 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled receive FIFO has overflowed" "No overflow,Overflow" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled receive FIFO is full" "Not full,Full" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled receive channel FIFO is greater than the receive FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308A0000+0x80))&0x80000000)==0x80000000) rgroup.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register" in sif cpuis("K32W0?2S1M*") hgroup.long 0xA4++0x03 hide.long 0x00 "RDR1,SAI Receive Data Register 1" in endif sif !cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x07 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RFR1,SAI Receive FIFO Register 1" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Receive word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Receive word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Receive word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Receive word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Receive word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Receive word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Receive word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Receive word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Receive word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Receive word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Receive word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Receive word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Receive word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Receive word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Receive word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Receive word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Receive word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Receive word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Receive word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Receive word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Receive word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Receive word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Receive word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Receive word mask 0" "Not masked,Masked" width 0x0B tree.end tree "I2S2" base ad:0x308B0000 width 6. sif cpuis("K32W0?2S1M*") rgroup.long (-0x08)++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x00++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled transmit FIFO has underrun" "No underrun,Underrun" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled transmit FIFO is empty" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled transmit channel FIFO is less than or equal to the transmit FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308B0000))&0x80000000)==0x80000000) rgroup.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register" sif cpuis("K32W0?2S1M*") wgroup.long 0x24++0x03 line.long 0x00 "TDR1,SAI Transmit Data Register 1" endif sif !cpuis("K32W0?2S1M*") rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register" hexmask.long.byte 0x00 16.--21. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 1. " RFP ,Read FIFO pointer" endif sif cpuis("K32W0?2S1M*") rgroup.long 0x40++0x07 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 1. " RFP ,Read FIFO pointer" line.long 0x04 "TFR1,SAI Transmit FIFO Register 1" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x04 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 1. " RFP ,Read FIFO pointer" endif group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word mask 0" "Not masked,Masked" group.long 0x80++0x03 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled receive FIFO has overflowed" "No overflow,Overflow" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled receive FIFO is full" "Not full,Full" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled receive channel FIFO is greater than the receive FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308B0000+0x80))&0x80000000)==0x80000000) rgroup.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register" in sif cpuis("K32W0?2S1M*") hgroup.long 0xA4++0x03 hide.long 0x00 "RDR1,SAI Receive Data Register 1" in endif sif !cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x07 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RFR1,SAI Receive FIFO Register 1" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Receive word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Receive word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Receive word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Receive word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Receive word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Receive word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Receive word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Receive word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Receive word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Receive word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Receive word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Receive word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Receive word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Receive word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Receive word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Receive word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Receive word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Receive word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Receive word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Receive word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Receive word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Receive word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Receive word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Receive word mask 0" "Not masked,Masked" width 0x0B tree.end tree "I2S3" base ad:0x308C0000 width 6. sif cpuis("K32W0?2S1M*") rgroup.long (-0x08)++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16.--19. " FRAME ,Frame size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 8.--11. " FIFO ,FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " DATALINE ,Number of datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x00++0x03 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled transmit FIFO has underrun" "No underrun,Underrun" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled transmit FIFO is empty" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled transmit channel FIFO is less than or equal to the transmit FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x04++0x03 line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x00 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308C0000))&0x80000000)==0x80000000) rgroup.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With receiver,Syn. With SAI transm.,Syn. With SAI rec." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "MCLK 1,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " TCE[1] ,Transmit channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Transmit channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 5. " CHMOD ,Channel mode" "TDM mode,Output mode" textline " " endif bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On Demand Mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register" sif cpuis("K32W0?2S1M*") wgroup.long 0x24++0x03 line.long 0x00 "TDR1,SAI Transmit Data Register 1" endif sif !cpuis("K32W0?2S1M*") rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register" hexmask.long.byte 0x00 16.--21. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 1. " RFP ,Read FIFO pointer" endif sif cpuis("K32W0?2S1M*") rgroup.long 0x40++0x07 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x00 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 1. " RFP ,Read FIFO pointer" line.long 0x04 "TFR1,SAI Transmit FIFO Register 1" bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" hexmask.long.byte 0x04 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 1. " RFP ,Read FIFO pointer" endif group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Transmit word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Transmit word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Transmit word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Transmit word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Transmit word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Transmit word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Transmit word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word mask 0" "Not masked,Masked" group.long 0x80++0x03 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Indicates that the start of the configured word has been detected" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Indicates that an error in the externally-generated frame sync has been detected" "Not detected,Detected" textline " " eventfld.long 0x00 18. " FEF ,Indicates that an enabled receive FIFO has overflowed" "No overflow,Overflow" rbitfld.long 0x00 17. " FWF ,Indicates that an enabled receive FIFO is full" "Not full,Full" rbitfld.long 0x00 16. " FRF ,Indicates that the number of words in an enabled receive channel FIFO is greater than the receive FIFO watermark" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" sif cpuis("K32W0?2S1M*") group.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" else rgroup.long 0x84++0x03 line.long 0x00 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x00 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x308C0000+0x80))&0x80000000)==0x80000000) rgroup.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Syn. With trans..,Syn. With SAI rec.,Syn. With SAI trans." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Clocked like external" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" textline " " bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External-slave,Internal-master" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x04 25. " CFR[1] ,Channel FIFO reset 1" "No effected,Effected" bitfld.long 0x04 24. " [0] ,Channel FIFO reset 0" "No effected,Effected" bitfld.long 0x04 17. " RCE[1] ,Receive channel enable bit 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Receive channel enable bit 0" "Disabled,Enabled" textline " " else bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "Not occurred,Occurred" bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO writes,FIFO reads,FIFO reads/writes" bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,MSB first" "LSB first,MSB first" textline " " bitfld.long 0x08 3. " FSE ,Frame sync early" "Disabled,Enabled" textline " " sif cpuis("K32W0?2S1M*") bitfld.long 0x08 2. " ONDEM ,On demand mode" "Continuously,FIFO clear" textline " " endif bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External-slave,Internal-master" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,SAI Receive Data Register" in sif cpuis("K32W0?2S1M*") hgroup.long 0xA4++0x03 hide.long 0x00 "RDR1,SAI Receive Data Register 1" in endif sif !cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO Register" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif cpuis("K32W0?2S1M*") rgroup.long 0xC0++0x07 line.long 0x00 "RFR0,SAI Receive FIFO Register 0" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RFR1,SAI Receive FIFO Register 1" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Receive word mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Receive word mask 29" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Receive word mask 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " [27] ,Receive word mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Receive word mask 26" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Receive word mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Receive word mask 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " [23] ,Receive word mask 23" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Receive word mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Receive word mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Receive word mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Receive word mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Receive word mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Receive word mask 17" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Receive word mask 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " [15] ,Receive word mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Receive word mask 14" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Receive word mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Receive word mask 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " [11] ,Receive word mask 11" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Receive word mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Receive word mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Receive word mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Receive word mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Receive word mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Receive word mask 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Receive word mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Receive word mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Receive word mask 2" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Receive word mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Receive word mask 0" "Not masked,Masked" width 0x0B tree.end tree.end tree.open "ADC (Analog-to-Digital Converter)" tree "ADC1" base ad:0x30610000 width 16. group.long 0x0++0x03 line.long 0x00 "CH_A_CFG1,Channel A Configuration 1" bitfld.long 0x00 31. " CHA_EN ,Channel A enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHA_SINGLE ,Channel A signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHA_AVG_EN ,Channel A average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHA_SEL ,Channel A select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHA_TIMER ,Channel A timer" if (((per.l(ad:0x30610000+0x0))&0x20000000)==0x20000000) group.long (0x0+0x10)++0x03 line.long 0x00 "CH_A_CFG2,Channel A Configuration 2" bitfld.long 0x00 29.--31. " CHA_CMP_MODE ,Channel A compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHA_HIGH_THRES ,Channel A high threshold value" bitfld.long 0x00 15. " CHA_AUTO_DIS ,Channel A auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHA_AVG_NUMBER ,Channel A average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHA_LOW_THRES ,Channel A low threshold value" else group.long (0x0+0x10)++0x03 line.long 0x00 "CH_A_CFG2,Channel A Configuration 2" bitfld.long 0x00 29.--31. " CHA_CMP_MODE ,Channel A compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHA_HIGH_THRES ,Channel A high threshold value" bitfld.long 0x00 15. " CHA_AUTO_DIS ,Channel A auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHA_LOW_THRES ,Channel A low threshold value" endif group.long 0x20++0x03 line.long 0x00 "CH_B_CFG1,Channel B Configuration 1" bitfld.long 0x00 31. " CHB_EN ,Channel B enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHB_SINGLE ,Channel B signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHB_AVG_EN ,Channel B average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHB_SEL ,Channel B select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHB_TIMER ,Channel B timer" if (((per.l(ad:0x30610000+0x20))&0x20000000)==0x20000000) group.long (0x20+0x10)++0x03 line.long 0x00 "CH_B_CFG2,Channel B Configuration 2" bitfld.long 0x00 29.--31. " CHB_CMP_MODE ,Channel B compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHB_HIGH_THRES ,Channel B high threshold value" bitfld.long 0x00 15. " CHB_AUTO_DIS ,Channel B auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHB_AVG_NUMBER ,Channel B average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHB_LOW_THRES ,Channel B low threshold value" else group.long (0x20+0x10)++0x03 line.long 0x00 "CH_B_CFG2,Channel B Configuration 2" bitfld.long 0x00 29.--31. " CHB_CMP_MODE ,Channel B compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHB_HIGH_THRES ,Channel B high threshold value" bitfld.long 0x00 15. " CHB_AUTO_DIS ,Channel B auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHB_LOW_THRES ,Channel B low threshold value" endif group.long 0x40++0x03 line.long 0x00 "CH_C_CFG1,Channel C Configuration 1" bitfld.long 0x00 31. " CHC_EN ,Channel C enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHC_SINGLE ,Channel C signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHC_AVG_EN ,Channel C average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHC_SEL ,Channel C select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHC_TIMER ,Channel C timer" if (((per.l(ad:0x30610000+0x40))&0x20000000)==0x20000000) group.long (0x40+0x10)++0x03 line.long 0x00 "CH_C_CFG2,Channel C Configuration 2" bitfld.long 0x00 29.--31. " CHC_CMP_MODE ,Channel C compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHC_HIGH_THRES ,Channel C high threshold value" bitfld.long 0x00 15. " CHC_AUTO_DIS ,Channel C auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHC_AVG_NUMBER ,Channel C average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHC_LOW_THRES ,Channel C low threshold value" else group.long (0x40+0x10)++0x03 line.long 0x00 "CH_C_CFG2,Channel C Configuration 2" bitfld.long 0x00 29.--31. " CHC_CMP_MODE ,Channel C compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHC_HIGH_THRES ,Channel C high threshold value" bitfld.long 0x00 15. " CHC_AUTO_DIS ,Channel C auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHC_LOW_THRES ,Channel C low threshold value" endif group.long 0x60++0x03 line.long 0x00 "CH_D_CFG1,Channel D Configuration 1" bitfld.long 0x00 31. " CHD_EN ,Channel D enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHD_SINGLE ,Channel D signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHD_AVG_EN ,Channel D average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHD_SEL ,Channel D select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHD_TIMER ,Channel D timer" if (((per.l(ad:0x30610000+0x60))&0x20000000)==0x20000000) group.long (0x60+0x10)++0x03 line.long 0x00 "CH_D_CFG2,Channel D Configuration 2" bitfld.long 0x00 29.--31. " CHD_CMP_MODE ,Channel D compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHD_HIGH_THRES ,Channel D high threshold value" bitfld.long 0x00 15. " CHD_AUTO_DIS ,Channel D auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHD_AVG_NUMBER ,Channel D average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHD_LOW_THRES ,Channel D low threshold value" else group.long (0x60+0x10)++0x03 line.long 0x00 "CH_D_CFG2,Channel D Configuration 2" bitfld.long 0x00 29.--31. " CHD_CMP_MODE ,Channel D compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHD_HIGH_THRES ,Channel D high threshold value" bitfld.long 0x00 15. " CHD_AUTO_DIS ,Channel D auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHD_LOW_THRES ,Channel D low threshold value" endif newline if (((per.l(ad:0x30610000+0x80))&0x800000)==0x800000) group.long 0x80++0x03 line.long 0x00 "CH_SW_CFG,Channel Software Configuration" bitfld.long 0x00 31. " START_CONV ,Start software trigger conversion" "Not started,Started" bitfld.long 0x00 24.--27. " CH_SW_SEL ,Software trigger channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" newline bitfld.long 0x00 23. " CH_SW_AVG_EN ,Channel software average enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " CH_SW_AVG_NUMBER ,Channel software average number" "4,8,16,32" else group.long 0x80++0x03 line.long 0x00 "CH_SW_CFG,Channel Software Configuration" bitfld.long 0x00 31. " START_CONV ,Start software trigger conversion" "Not started,Started" bitfld.long 0x00 24.--27. " CH_SW_SEL ,Software trigger channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" newline bitfld.long 0x00 23. " CH_SW_AVG_EN ,Channel software average enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "TIMER_UNIT,Timer Unit" bitfld.long 0x00 29.--31. " PRE_DIV ,Pre-divide" "/1,/2,/4,/8,/16,/32,?..." bitfld.long 0x00 0.--4. " CORE_TIMER_UNIT ,Core_timer_unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA0++0x03 line.long 0x00 "DMA_FIFO,DMA FIFO" bitfld.long 0x00 9. " DMA_RST ,DMA reset" "No reset,Reset" bitfld.long 0x00 8. " DMA_FIFO_EN ,DMA FIFO enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMA_EN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--6. " DMA_CH_SEL ,DMA channel select" "Channel A,Channel B,Channel C,Channel D" bitfld.long 0x00 0.--4. " DMA_WM_LVL ,DMA water mark level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xB0++0x03 line.long 0x00 "FIFO_STATUS,FIFO Status" bitfld.long 0x00 9. " FIFO_FULL ,FIFO full" "Not full,Full" bitfld.long 0x00 8. " FIFO_EMPTY ,FIFO empty" "Not empty,Empty" bitfld.long 0x00 0.--5. " FIFO_ENTRIES ,FIFO entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x03 line.long 0x00 "INT_SIG_EN,INT_SIG_EN" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ_SIG_EN ,Last FIFO data read signal enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_CH_COV_TO_INT_SIG_EN ,Software channel conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 19. " CHD_COV_TO_INT_SIG_EN ,Channel D conversion time out interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CHC_COV_TO_INT_SIG_EN ,Channel C conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 17. " CHB_COV_TO_INT_SIG_EN ,Channel B conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 16. " CHA_COV_TO_INT_SIG_EN ,Channel A conversion time out interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SW_CH_COV_INT_SIG_EN ,Software channel conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV_INT_SIG_EN ,Channel D conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV_INT_SIG_EN ,Channel C conversion interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV_INT_SIG_EN ,Channel B conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV_INT_SIG_EN ,Channel A conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN_INT_SIG_EN ,FIFO overrun interrupt signal enable" "Enabled,Disabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN_INT_SIG_EN ,FIFO underrrun interrupt signal enable" "Enabled,Disabled" bitfld.long 0x00 5. " DMA_REACH_WM_INT_SIG_EN ,DMA reach watermark level interrupt signal (Flag) enable" "Enabled,Disabled" bitfld.long 0x00 3. " CHD_CMP_INT_SIG_EN ,Channel D compare interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP_INT_SIG_EN ,Channel C compare interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP_INT_SIG_EN ,Channel B compare interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP_INT_SIG_EN ,Channel A compare interrupt signal enable" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "INT_EN,Interrupt Enable" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ_EN ,Last FIFO data read enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_CH_COV_TO_INT_EN ,Software channel conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CHD_COV_TO_INT_EN ,Channel D conversion time out interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CHC_COV_TO_INT_EN ,Channel C conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CHB_COV_TO_INT_EN ,Channel B conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " CHA_COV_TO_INT_EN ,Channel A conversion time out interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SW_CH_COV_INT_EN ,Software channel conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV_INT_EN ,Channel D conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV_INT_EN ,Channel C conversion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV_INT_EN ,Channel B conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV_INT_EN ,Channel A conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN_INT_EN ,FIFO overrun interrupt enable" "Enabled,Disabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN_INT_EN ,FIFO underrrun interrupt enable" "Enabled,Disabled" bitfld.long 0x00 5. " DMA_REACH_WM_INT_EN ,DMA reach watermark level interrupt enable" "Enabled,Disabled" bitfld.long 0x00 3. " CHD_CMP_INT_EN ,Channel D compare interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP_INT_EN ,Channel C compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP_INT_EN ,Channel B compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP_INT_EN ,Channel A compare interrupt enable" "Disabled,Enabled" group.long 0xE0++0x03 line.long 0x00 "INT_STATUS,INT_STATUS" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ ,Last FIFO data read" "Not read out,Read out" bitfld.long 0x00 20. " SW_CH_COV_TO ,Software channel conversion time out" "No timeout,Timeout" bitfld.long 0x00 19. " CHD_COV_TO ,Channel D conversion time out" "No timeout,Timeout" newline bitfld.long 0x00 18. " CHC_COV_TO ,Channel C conversion time out" "No timeout,Timeout" bitfld.long 0x00 17. " CHB_COV_TO ,Channel B conversion time out" "No timeout,Timeout" bitfld.long 0x00 16. " CHA_COV_TO ,Channel A conversion time out" "No timeout,Timeout" newline bitfld.long 0x00 12. " SW_CH_COV ,Software channel conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV ,Channel D conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV ,Channel C conversion (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV ,Channel B conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV ,Channel A conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN ,FIFO overrun (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN ,FIFO underrrun (Flag)" "No underrun,Underrun" bitfld.long 0x00 5. " DMA_REACH_WM ,DMA reach watermark level (Flag)" "Not reached,Reached" bitfld.long 0x00 3. " CHD_CMP ,Channel D compare (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP ,Channel C compare (Flag)" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP ,Channel B compare (Flag)" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP ,Channel A compare (Flag)" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "CHA_B_CNV_RSLT,Channel A And B Conversion Result" hexmask.long.word 0x00 16.--27. 1. " CHB_CNV_RSLT ,Channel B conversion result" hexmask.long.word 0x00 0.--11. 1. " CHA_CNV_RSLT ,Channel A conversion result" group.long 0x100++0x03 line.long 0x00 "CHC_D_CNV_RSLT,Channel C And D Conversion Result" hexmask.long.word 0x00 16.--27. 1. " CHD_CNV_RSLT ,Channel D conversion result" hexmask.long.word 0x00 0.--11. 1. " CHC_CNV_RSLT ,Channel C conversion result" group.long 0x110++0x03 line.long 0x00 "CH_SW_CNV_RSLT,Channel Software Conversion Result" hexmask.long.word 0x00 0.--11. 1. " CH_SW_CNV_RSLT ,Channel software conversion result" rgroup.long 0x120++0x03 line.long 0x00 "DMA_FIFO_DAT,DMA FIFO Data" bitfld.long 0x00 30.--31. " DAT2_FLAG ,Data 2 flag" "Default,Valid data,Last data,Invalid data" hexmask.long.word 0x00 16.--27. 1. " DMA_FIFO_1 ,The even number of data is in this field" newline bitfld.long 0x00 14.--15. " DAT1_FLAG ,Data 1 flag" "Default,Valid data,Last data,Invalid data" hexmask.long.word 0x00 0.--11. 1. " DMA_FIFO_0 ,The even number of data is in this field" group.long 0x130++0x03 line.long 0x00 "ADC_CFG,ADC Configuration" bitfld.long 0x00 31. " ADC_CLK_DOWN ,ADC clock down" "Running,Down" bitfld.long 0x00 7. " ADC_PD_OK ,ADC power down OK" "Not powered up,Powered up" newline bitfld.long 0x00 1. " ADC_PD ,ADC power down" "Not powered down,Powered down" bitfld.long 0x00 0. " ADC_EN ,ADC level shifter enable" "Disabled,Enabled" width 0x0B tree.end tree "ADC2" base ad:0x30620000 width 16. group.long 0x0++0x03 line.long 0x00 "CH_A_CFG1,Channel A Configuration 1" bitfld.long 0x00 31. " CHA_EN ,Channel A enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHA_SINGLE ,Channel A signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHA_AVG_EN ,Channel A average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHA_SEL ,Channel A select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHA_TIMER ,Channel A timer" if (((per.l(ad:0x30620000+0x0))&0x20000000)==0x20000000) group.long (0x0+0x10)++0x03 line.long 0x00 "CH_A_CFG2,Channel A Configuration 2" bitfld.long 0x00 29.--31. " CHA_CMP_MODE ,Channel A compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHA_HIGH_THRES ,Channel A high threshold value" bitfld.long 0x00 15. " CHA_AUTO_DIS ,Channel A auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHA_AVG_NUMBER ,Channel A average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHA_LOW_THRES ,Channel A low threshold value" else group.long (0x0+0x10)++0x03 line.long 0x00 "CH_A_CFG2,Channel A Configuration 2" bitfld.long 0x00 29.--31. " CHA_CMP_MODE ,Channel A compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHA_HIGH_THRES ,Channel A high threshold value" bitfld.long 0x00 15. " CHA_AUTO_DIS ,Channel A auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHA_LOW_THRES ,Channel A low threshold value" endif group.long 0x20++0x03 line.long 0x00 "CH_B_CFG1,Channel B Configuration 1" bitfld.long 0x00 31. " CHB_EN ,Channel B enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHB_SINGLE ,Channel B signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHB_AVG_EN ,Channel B average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHB_SEL ,Channel B select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHB_TIMER ,Channel B timer" if (((per.l(ad:0x30620000+0x20))&0x20000000)==0x20000000) group.long (0x20+0x10)++0x03 line.long 0x00 "CH_B_CFG2,Channel B Configuration 2" bitfld.long 0x00 29.--31. " CHB_CMP_MODE ,Channel B compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHB_HIGH_THRES ,Channel B high threshold value" bitfld.long 0x00 15. " CHB_AUTO_DIS ,Channel B auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHB_AVG_NUMBER ,Channel B average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHB_LOW_THRES ,Channel B low threshold value" else group.long (0x20+0x10)++0x03 line.long 0x00 "CH_B_CFG2,Channel B Configuration 2" bitfld.long 0x00 29.--31. " CHB_CMP_MODE ,Channel B compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHB_HIGH_THRES ,Channel B high threshold value" bitfld.long 0x00 15. " CHB_AUTO_DIS ,Channel B auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHB_LOW_THRES ,Channel B low threshold value" endif group.long 0x40++0x03 line.long 0x00 "CH_C_CFG1,Channel C Configuration 1" bitfld.long 0x00 31. " CHC_EN ,Channel C enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHC_SINGLE ,Channel C signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHC_AVG_EN ,Channel C average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHC_SEL ,Channel C select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHC_TIMER ,Channel C timer" if (((per.l(ad:0x30620000+0x40))&0x20000000)==0x20000000) group.long (0x40+0x10)++0x03 line.long 0x00 "CH_C_CFG2,Channel C Configuration 2" bitfld.long 0x00 29.--31. " CHC_CMP_MODE ,Channel C compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHC_HIGH_THRES ,Channel C high threshold value" bitfld.long 0x00 15. " CHC_AUTO_DIS ,Channel C auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHC_AVG_NUMBER ,Channel C average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHC_LOW_THRES ,Channel C low threshold value" else group.long (0x40+0x10)++0x03 line.long 0x00 "CH_C_CFG2,Channel C Configuration 2" bitfld.long 0x00 29.--31. " CHC_CMP_MODE ,Channel C compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHC_HIGH_THRES ,Channel C high threshold value" bitfld.long 0x00 15. " CHC_AUTO_DIS ,Channel C auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHC_LOW_THRES ,Channel C low threshold value" endif group.long 0x60++0x03 line.long 0x00 "CH_D_CFG1,Channel D Configuration 1" bitfld.long 0x00 31. " CHD_EN ,Channel D enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHD_SINGLE ,Channel D signal conversion" "No signal conversion,Signal conversion" bitfld.long 0x00 29. " CHD_AVG_EN ,Channel D average enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " CHD_SEL ,Channel D select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" hexmask.long.tbyte 0x00 0.--23. 1. " CHD_TIMER ,Channel D timer" if (((per.l(ad:0x30620000+0x60))&0x20000000)==0x20000000) group.long (0x60+0x10)++0x03 line.long 0x00 "CH_D_CFG2,Channel D Configuration 2" bitfld.long 0x00 29.--31. " CHD_CMP_MODE ,Channel D compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHD_HIGH_THRES ,Channel D high threshold value" bitfld.long 0x00 15. " CHD_AUTO_DIS ,Channel D auto disable" "No,Yes" newline bitfld.long 0x00 12.--13. " CHD_AVG_NUMBER ,Channel D average number" "4,8,16,32" hexmask.long.word 0x00 0.--11. 1. " CHD_LOW_THRES ,Channel D low threshold value" else group.long (0x60+0x10)++0x03 line.long 0x00 "CH_D_CFG2,Channel D Configuration 2" bitfld.long 0x00 29.--31. " CHD_CMP_MODE ,Channel D compare mode" "Disabled,>CHA_LOW_THRES,<=CHA_LOW_THRES,>CHA_LOW_THRES && =CHA_HIGH_THRES,=CHA_HIGH_THRES" hexmask.long.word 0x00 16.--27. 1. " CHD_HIGH_THRES ,Channel D high threshold value" bitfld.long 0x00 15. " CHD_AUTO_DIS ,Channel D auto disable" "No,Yes" newline hexmask.long.word 0x00 0.--11. 1. " CHD_LOW_THRES ,Channel D low threshold value" endif newline if (((per.l(ad:0x30620000+0x80))&0x800000)==0x800000) group.long 0x80++0x03 line.long 0x00 "CH_SW_CFG,Channel Software Configuration" bitfld.long 0x00 31. " START_CONV ,Start software trigger conversion" "Not started,Started" bitfld.long 0x00 24.--27. " CH_SW_SEL ,Software trigger channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" newline bitfld.long 0x00 23. " CH_SW_AVG_EN ,Channel software average enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " CH_SW_AVG_NUMBER ,Channel software average number" "4,8,16,32" else group.long 0x80++0x03 line.long 0x00 "CH_SW_CFG,Channel Software Configuration" bitfld.long 0x00 31. " START_CONV ,Start software trigger conversion" "Not started,Started" bitfld.long 0x00 24.--27. " CH_SW_SEL ,Software trigger channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" newline bitfld.long 0x00 23. " CH_SW_AVG_EN ,Channel software average enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "TIMER_UNIT,Timer Unit" bitfld.long 0x00 29.--31. " PRE_DIV ,Pre-divide" "/1,/2,/4,/8,/16,/32,?..." bitfld.long 0x00 0.--4. " CORE_TIMER_UNIT ,Core_timer_unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA0++0x03 line.long 0x00 "DMA_FIFO,DMA FIFO" bitfld.long 0x00 9. " DMA_RST ,DMA reset" "No reset,Reset" bitfld.long 0x00 8. " DMA_FIFO_EN ,DMA FIFO enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMA_EN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--6. " DMA_CH_SEL ,DMA channel select" "Channel A,Channel B,Channel C,Channel D" bitfld.long 0x00 0.--4. " DMA_WM_LVL ,DMA water mark level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xB0++0x03 line.long 0x00 "FIFO_STATUS,FIFO Status" bitfld.long 0x00 9. " FIFO_FULL ,FIFO full" "Not full,Full" bitfld.long 0x00 8. " FIFO_EMPTY ,FIFO empty" "Not empty,Empty" bitfld.long 0x00 0.--5. " FIFO_ENTRIES ,FIFO entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x03 line.long 0x00 "INT_SIG_EN,INT_SIG_EN" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ_SIG_EN ,Last FIFO data read signal enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_CH_COV_TO_INT_SIG_EN ,Software channel conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 19. " CHD_COV_TO_INT_SIG_EN ,Channel D conversion time out interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CHC_COV_TO_INT_SIG_EN ,Channel C conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 17. " CHB_COV_TO_INT_SIG_EN ,Channel B conversion time out interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 16. " CHA_COV_TO_INT_SIG_EN ,Channel A conversion time out interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SW_CH_COV_INT_SIG_EN ,Software channel conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV_INT_SIG_EN ,Channel D conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV_INT_SIG_EN ,Channel C conversion interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV_INT_SIG_EN ,Channel B conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV_INT_SIG_EN ,Channel A conversion interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN_INT_SIG_EN ,FIFO overrun interrupt signal enable" "Enabled,Disabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN_INT_SIG_EN ,FIFO underrrun interrupt signal enable" "Enabled,Disabled" bitfld.long 0x00 5. " DMA_REACH_WM_INT_SIG_EN ,DMA reach watermark level interrupt signal (Flag) enable" "Enabled,Disabled" bitfld.long 0x00 3. " CHD_CMP_INT_SIG_EN ,Channel D compare interrupt signal enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP_INT_SIG_EN ,Channel C compare interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP_INT_SIG_EN ,Channel B compare interrupt signal enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP_INT_SIG_EN ,Channel A compare interrupt signal enable" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "INT_EN,Interrupt Enable" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ_EN ,Last FIFO data read enable" "Disabled,Enabled" bitfld.long 0x00 20. " SW_CH_COV_TO_INT_EN ,Software channel conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CHD_COV_TO_INT_EN ,Channel D conversion time out interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CHC_COV_TO_INT_EN ,Channel C conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CHB_COV_TO_INT_EN ,Channel B conversion time out interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " CHA_COV_TO_INT_EN ,Channel A conversion time out interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SW_CH_COV_INT_EN ,Software channel conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV_INT_EN ,Channel D conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV_INT_EN ,Channel C conversion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV_INT_EN ,Channel B conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV_INT_EN ,Channel A conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN_INT_EN ,FIFO overrun interrupt enable" "Enabled,Disabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN_INT_EN ,FIFO underrrun interrupt enable" "Enabled,Disabled" bitfld.long 0x00 5. " DMA_REACH_WM_INT_EN ,DMA reach watermark level interrupt enable" "Enabled,Disabled" bitfld.long 0x00 3. " CHD_CMP_INT_EN ,Channel D compare interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP_INT_EN ,Channel C compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP_INT_EN ,Channel B compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP_INT_EN ,Channel A compare interrupt enable" "Disabled,Enabled" group.long 0xE0++0x03 line.long 0x00 "INT_STATUS,INT_STATUS" bitfld.long 0x00 21. " LAST_FIFO_DATA_READ ,Last FIFO data read" "Not read out,Read out" bitfld.long 0x00 20. " SW_CH_COV_TO ,Software channel conversion time out" "No timeout,Timeout" bitfld.long 0x00 19. " CHD_COV_TO ,Channel D conversion time out" "No timeout,Timeout" newline bitfld.long 0x00 18. " CHC_COV_TO ,Channel C conversion time out" "No timeout,Timeout" bitfld.long 0x00 17. " CHB_COV_TO ,Channel B conversion time out" "No timeout,Timeout" bitfld.long 0x00 16. " CHA_COV_TO ,Channel A conversion time out" "No timeout,Timeout" newline bitfld.long 0x00 12. " SW_CH_COV ,Software channel conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 11. " CHD_COV ,Channel D conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 10. " CHC_COV ,Channel C conversion (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 9. " CHB_COV ,Channel B conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 8. " CHA_COV ,Channel A conversion (Flag)" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO_OVRRUN ,FIFO overrun (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 6. " FIFO_UNDERRUN ,FIFO underrrun (Flag)" "No underrun,Underrun" bitfld.long 0x00 5. " DMA_REACH_WM ,DMA reach watermark level (Flag)" "Not reached,Reached" bitfld.long 0x00 3. " CHD_CMP ,Channel D compare (Flag)" "Disabled,Enabled" newline bitfld.long 0x00 2. " CHC_CMP ,Channel C compare (Flag)" "Disabled,Enabled" bitfld.long 0x00 1. " CHB_CMP ,Channel B compare (Flag)" "Disabled,Enabled" bitfld.long 0x00 0. " CHA_CMP ,Channel A compare (Flag)" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "CHA_B_CNV_RSLT,Channel A And B Conversion Result" hexmask.long.word 0x00 16.--27. 1. " CHB_CNV_RSLT ,Channel B conversion result" hexmask.long.word 0x00 0.--11. 1. " CHA_CNV_RSLT ,Channel A conversion result" group.long 0x100++0x03 line.long 0x00 "CHC_D_CNV_RSLT,Channel C And D Conversion Result" hexmask.long.word 0x00 16.--27. 1. " CHD_CNV_RSLT ,Channel D conversion result" hexmask.long.word 0x00 0.--11. 1. " CHC_CNV_RSLT ,Channel C conversion result" group.long 0x110++0x03 line.long 0x00 "CH_SW_CNV_RSLT,Channel Software Conversion Result" hexmask.long.word 0x00 0.--11. 1. " CH_SW_CNV_RSLT ,Channel software conversion result" rgroup.long 0x120++0x03 line.long 0x00 "DMA_FIFO_DAT,DMA FIFO Data" bitfld.long 0x00 30.--31. " DAT2_FLAG ,Data 2 flag" "Default,Valid data,Last data,Invalid data" hexmask.long.word 0x00 16.--27. 1. " DMA_FIFO_1 ,The even number of data is in this field" newline bitfld.long 0x00 14.--15. " DAT1_FLAG ,Data 1 flag" "Default,Valid data,Last data,Invalid data" hexmask.long.word 0x00 0.--11. 1. " DMA_FIFO_0 ,The even number of data is in this field" group.long 0x130++0x03 line.long 0x00 "ADC_CFG,ADC Configuration" bitfld.long 0x00 31. " ADC_CLK_DOWN ,ADC clock down" "Running,Down" bitfld.long 0x00 7. " ADC_PD_OK ,ADC power down OK" "Not powered up,Powered up" newline bitfld.long 0x00 1. " ADC_PD ,ADC power down" "Not powered down,Powered down" bitfld.long 0x00 0. " ADC_EN ,ADC level shifter enable" "Disabled,Enabled" width 0x0B tree.end tree.end tree "TEMPMON (Temperature Monitor)" base ad:0x30360000 width 20. group.long 0x600++0x1F line.long 0x00 "TEMPSENSE0,Anadig Tempsensor Control Register 0" hexmask.long.word 0x00 18.--26. 1. " PANIC_ALARM_VALUE ,Contains the temperature measurement that will cause a panic and reset the chip" hexmask.long.word 0x00 9.--17. 1. " HIGH_ALARM_VALUE ,Contains the temperature measurement that will issue a high temperature interrupt" hexmask.long.word 0x00 0.--8. 1. " LOW_ALARM_VALUE ,Contains the temperature measurement that will issue a low temperature interrupt" line.long 0x04 "TEMPSENSE0_SET,Anadig Tempsensor Control Register 0" hexmask.long.word 0x04 18.--26. 1. " PANIC_ALARM_VALUE ,Contains the temperature measurement that will cause a panic and reset the chip" hexmask.long.word 0x04 9.--17. 1. " HIGH_ALARM_VALUE ,Contains the temperature measurement that will issue a high temperature interrupt" hexmask.long.word 0x04 0.--8. 1. " LOW_ALARM_VALUE ,Contains the temperature measurement that will issue a low temperature interrupt" line.long 0x08 "TEMPSENSE0_CLR,Anadig Tempsensor Control Register 0" hexmask.long.word 0x08 18.--26. 1. " PANIC_ALARM_VALUE ,Contains the temperature measurement that will cause a panic and reset the chip" hexmask.long.word 0x08 9.--17. 1. " HIGH_ALARM_VALUE ,Contains the temperature measurement that will issue a high temperature interrupt" hexmask.long.word 0x08 0.--8. 1. " LOW_ALARM_VALUE ,Contains the temperature measurement that will issue a low temperature interrupt" line.long 0x0C "TEMPSENSE0_TOG,Anadig Tempsensor Control Register 0" hexmask.long.word 0x0C 18.--26. 1. " PANIC_ALARM_VALUE ,Contains the temperature measurement that will cause a panic and reset the chip" hexmask.long.word 0x0C 9.--17. 1. " HIGH_ALARM_VALUE ,Contains the temperature measurement that will issue a high temperature interrupt" hexmask.long.word 0x0C 0.--8. 1. " LOW_ALARM_VALUE ,Contains the temperature measurement that will issue a low temperature interrupt" line.long 0x10 "TEMPSENSE1,Anadig Tempsensor Control Register 1" hexmask.long.word 0x10 16.--31. 1. " MEASURE_FREQ ,Determines how many RTC clocks to wait before automatically repeating a temperature measurement" bitfld.long 0x10 11. " FINISHED ,Indicates that the latest temp is valid" "Not finished,Finished" bitfld.long 0x10 10. " MEASURE_TEMP ,Starts the measurement process" "Not started,Started" textline " " bitfld.long 0x10 9. " POWER_DOWN ,Powers down the temperature sensor" "Not powered down,Powered down" hexmask.long.word 0x10 0.--8. 1. " TEMP_VALUE ,Contains the temperature measurement" line.long 0x14 "TEMPSENSE1_SET,Anadig Tempsensor Control Register 1" hexmask.long.word 0x14 16.--31. 1. " MEASURE_FREQ ,Determines how many RTC clocks to wait before automatically repeating a temperature measurement" bitfld.long 0x14 11. " FINISHED ,Indicates that the latest temp is valid" "No effect,Set" bitfld.long 0x14 10. " MEASURE_TEMP ,Starts the measurement process" "No effect,Set" textline " " bitfld.long 0x14 9. " POWER_DOWN ,Powers down the temperature sensor" "No effect,Set" hexmask.long.word 0x14 0.--8. 1. " TEMP_VALUE ,Contains the temperature measurement" line.long 0x18 "TEMPSENSE1_CLR,Anadig Tempsensor Control Register 1" hexmask.long.word 0x18 16.--31. 1. " MEASURE_FREQ ,Determines how many RTC clocks to wait before automatically repeating a temperature measurement" bitfld.long 0x18 11. " FINISHED ,Indicates that the latest temp is valid" "No effect,Clear" bitfld.long 0x18 10. " MEASURE_TEMP ,Starts the measurement process" "No effect,Clear" textline " " bitfld.long 0x18 9. " POWER_DOWN ,Powers down the temperature sensor" "No effect,Clear" hexmask.long.word 0x18 0.--8. 1. " TEMP_VALUE ,Contains the temperature measurement" line.long 0x1C "TEMPSENSE1_TOG,Anadig Tempsensor Control Register 1" hexmask.long.word 0x1C 16.--31. 1. " MEASURE_FREQ ,Determines how many RTC clocks to wait before automatically repeating a temperature measurement" bitfld.long 0x1C 11. " FINISHED ,Indicates that the latest temp is valid" "Not toggled,Toggled" bitfld.long 0x1C 10. " MEASURE_TEMP ,Starts the measurement process" "Not toggled,Toggled" textline " " bitfld.long 0x1C 9. " POWER_DOWN ,Powers down the temperature sensor" "Not toggled,Toggled" hexmask.long.word 0x1C 0.--8. 1. " TEMP_VALUE ,Contains the temperature measurement" group.long 0x620++0x0F line.long 0x00 "TEMPSENSE_TRIM,Anadig Tempsensor Trim Control Register" bitfld.long 0x00 29.--31. " T_MUX_ADDR ,Test MUX address setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " T_BUF_SLOPE_SEL ,Amplifier gain setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 8.--16. 1. " T_VREF_VBE_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" textline " " bitfld.long 0x00 7. " T_EN_READ ,T_EN_READ" "Disabled,Enabled" bitfld.long 0x00 0.--4. " T_BUF_VREF_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "TEMPSENSE_TRIM_SET,Anadig Tempsensor Trim Control Register" bitfld.long 0x04 29.--31. " T_MUX_ADDR ,Test MUX address setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--23. " T_BUF_SLOPE_SEL ,Amplifier gain setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 8.--16. 1. " T_VREF_VBE_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" textline " " bitfld.long 0x04 7. " T_EN_READ ,T_EN_READ" "No effect,Set" bitfld.long 0x04 0.--4. " T_BUF_VREF_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TEMPSENSE_TRIM_CLR,Anadig Tempsensor Trim Control Register" bitfld.long 0x08 29.--31. " T_MUX_ADDR ,Test MUX address setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20.--23. " T_BUF_SLOPE_SEL ,Amplifier gain setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 8.--16. 1. " T_VREF_VBE_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" textline " " bitfld.long 0x08 7. " T_EN_READ ,T_EN_READ" "No effect,Clear" bitfld.long 0x08 0.--4. " T_BUF_VREF_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "TEMPSENSE_TRIM_TOG,Anadig Tempsensor Trim Control Register" bitfld.long 0x0C 29.--31. " T_MUX_ADDR ,Test MUX address setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 20.--23. " T_BUF_SLOPE_SEL ,Amplifier gain setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 8.--16. 1. " T_VREF_VBE_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" textline " " bitfld.long 0x0C 7. " T_EN_READ ,T_EN_READ" "Not toggled,Toggled" bitfld.long 0x0C 0.--4. " T_BUF_VREF_SEL ,Reference voltage setting bits for the am-plifier in the Positive-TC generator block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "FLEXCAN (Flexible Controller Area Network)" tree "FLEXCAN1" base ad:0x30A00000 width 10. tree "Common Registers" if (((per.l(ad:0x30A00000))&0x1100000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" rbitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" elif (((per.l(ad:0x30A00000))&0x1100000)==0x100000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" bitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" rbitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" rbitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" rbitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" rbitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" rbitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" endif if (((per.l(ad:0x30A00000))&0x1200000)==0x1200000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" bitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" bitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" bitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x30A00000))&0x1200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" rbitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" rbitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" rbitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x30A00000)&0x1200000)==0x1000000)) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" bitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" rbitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " rbitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" bitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" bitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" rbitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" rbitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " rbitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" rbitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" rbitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" endif hgroup.long 0x08++0x03 hide.long 0x00 "TIMER,Free-Running Timer Register" in textline " " if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long 0x10++0x0F line.long 0x00 "RXGMASK,Rx Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x04 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x04 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x04 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x04 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x04 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x04 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x04 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x04 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x04 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x04 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x08 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x08 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x08 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x08 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x08 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x08 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x08 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x08 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x08 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x08 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x08 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x08 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_COUNTER ,Rx error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_COUNTER ,Tx error counter" textline " " else rgroup.long 0x10++0x0F line.long 0x00 "RXGMASK,Rx Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x04 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x04 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x04 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x04 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x04 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x04 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x04 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x04 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x04 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x04 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x08 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x08 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x08 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x08 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x08 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x08 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x08 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x08 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x08 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x08 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x08 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x08 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " textline " " line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_COUNTER ,Rx error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_COUNTER ,Tx error counter" endif hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status Register 1" in group.long 0x24++0x0B line.long 0x00 "IMASK2,Interrupt Mask Register 2" bitfld.long 0x00 31. " BUF63M ,Buffer 63 MB mask" "Disabled,Enabled" bitfld.long 0x00 30. " BUF62M ,Buffer 62 MB mask" "Disabled,Enabled" bitfld.long 0x00 29. " BUF61M ,Buffer 61 MB mask" "Disabled,Enabled" bitfld.long 0x00 28. " BUF60M ,Buffer 60 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BUF59M ,Buffer 59 MB mask" "Disabled,Enabled" bitfld.long 0x00 26. " BUF58M ,Buffer 58 MB mask" "Disabled,Enabled" bitfld.long 0x00 25. " BUF57M ,Buffer 57 MB mask" "Disabled,Enabled" bitfld.long 0x00 24. " BUF56M ,Buffer 56 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BUF55M ,Buffer 55 MB mask" "Disabled,Enabled" bitfld.long 0x00 22. " BUF54M ,Buffer 54 MB mask" "Disabled,Enabled" bitfld.long 0x00 21. " BUF53M ,Buffer 53 MB mask" "Disabled,Enabled" bitfld.long 0x00 20. " BUF52M ,Buffer 52 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BUF51M ,Buffer 51 MB mask" "Disabled,Enabled" bitfld.long 0x00 18. " BUF50M ,Buffer 50 MB mask" "Disabled,Enabled" bitfld.long 0x00 17. " BUF49M ,Buffer 49 MB mask" "Disabled,Enabled" bitfld.long 0x00 16. " BUF48M ,Buffer 48 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " BUF47M ,Buffer 47 MB mask" "Disabled,Enabled" bitfld.long 0x00 14. " BUF46M ,Buffer 46 MB mask" "Disabled,Enabled" bitfld.long 0x00 13. " BUF45M ,Buffer 45 MB mask" "Disabled,Enabled" bitfld.long 0x00 12. " BUF44M ,Buffer 44 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BUF43M ,Buffer 43 MB mask" "Disabled,Enabled" bitfld.long 0x00 10. " BUF42M ,Buffer 42 MB mask" "Disabled,Enabled" bitfld.long 0x00 9. " BUF41M ,Buffer 41 MB mask" "Disabled,Enabled" bitfld.long 0x00 8. " BUF40M ,Buffer 40 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BUF39M ,Buffer 39 MB mask" "Disabled,Enabled" bitfld.long 0x00 6. " BUF38M ,Buffer 38 MB mask" "Disabled,Enabled" bitfld.long 0x00 5. " BUF37M ,Buffer 37 MB mask" "Disabled,Enabled" bitfld.long 0x00 4. " BUF36M ,Buffer 36 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF35M ,Buffer 35 MB mask" "Disabled,Enabled" bitfld.long 0x00 2. " BUF34M ,Buffer 34 MB mask" "Disabled,Enabled" bitfld.long 0x00 1. " BUF33M ,Buffer 33 MB mask" "Disabled,Enabled" bitfld.long 0x00 0. " BUF32M ,Buffer 32 MB mask" "Disabled,Enabled" line.long 0x04 "IMASK1,Interrupt Masks Register 1" bitfld.long 0x04 31. " BUF31M ,Buffer 31 MB mask" "Disabled,Enabled" bitfld.long 0x04 30. " BUF30M ,Buffer 30 MB mask" "Disabled,Enabled" bitfld.long 0x04 29. " BUF29M ,Buffer 29 MB mask" "Disabled,Enabled" bitfld.long 0x04 28. " BUF28M ,Buffer 28 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " BUF27M ,Buffer 27 MB mask" "Disabled,Enabled" bitfld.long 0x04 26. " BUF26M ,Buffer 26 MB mask" "Disabled,Enabled" bitfld.long 0x04 25. " BUF25M ,Buffer 25 MB mask" "Disabled,Enabled" bitfld.long 0x04 24. " BUF24M ,Buffer 24 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " BUF23M ,Buffer 23 MB mask" "Disabled,Enabled" bitfld.long 0x04 22. " BUF22M ,Buffer 22 MB mask" "Disabled,Enabled" bitfld.long 0x04 21. " BUF21M ,Buffer 21 MB mask" "Disabled,Enabled" bitfld.long 0x04 20. " BUF20M ,Buffer 20 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " BUF19M ,Buffer 19 MB mask" "Disabled,Enabled" bitfld.long 0x04 18. " BUF18M ,Buffer 18 MB mask" "Disabled,Enabled" bitfld.long 0x04 17. " BUF17M ,Buffer 17 MB mask" "Disabled,Enabled" bitfld.long 0x04 16. " BUF16M ,Buffer 16 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " BUF15M ,Buffer 15 MB mask" "Disabled,Enabled" bitfld.long 0x04 14. " BUF14M ,Buffer 14 MB mask" "Disabled,Enabled" bitfld.long 0x04 13. " BUF13M ,Buffer 13 MB mask" "Disabled,Enabled" bitfld.long 0x04 12. " BUF12M ,Buffer 12 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BUF11M ,Buffer 11 MB mask" "Disabled,Enabled" bitfld.long 0x04 10. " BUF10M ,Buffer 10 MB mask" "Disabled,Enabled" bitfld.long 0x04 9. " BUF9M ,Buffer 9 MB mask" "Disabled,Enabled" bitfld.long 0x04 8. " BUF8M ,Buffer 8 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BUF7M ,Buffer 7 MB mask" "Disabled,Enabled" bitfld.long 0x04 6. " BUF6M ,Buffer 6 MB mask" "Disabled,Enabled" bitfld.long 0x04 5. " BUF5M ,Buffer 5 MB mask" "Disabled,Enabled" bitfld.long 0x04 4. " BUF4M ,Buffer 4 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BUF3M ,Buffer 3 MB mask" "Disabled,Enabled" bitfld.long 0x04 2. " BUF2M ,Buffer 2 MB mask" "Disabled,Enabled" bitfld.long 0x04 1. " BUF1M ,Buffer 1 MB mask" "Disabled,Enabled" bitfld.long 0x04 0. " BUF0M ,Buffer 0 MB mask" "Disabled,Enabled" line.long 0x08 "IFLAG2,Interrupt Flags 2 Register" eventfld.long 0x08 31. " BUF63I ,Buffer 63 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 30. " BUF62I ,Buffer 62 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 29. " BUF61I ,Buffer 61 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 28. " BUF60I ,Buffer 60 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 27. " BUF59I ,Buffer 59 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 26. " BUF58I ,Buffer 58 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 25. " BUF57I ,Buffer 57 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 24. " BUF56I ,Buffer 56 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 23. " BUF55I ,Buffer 55 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 22. " BUF54I ,Buffer 54 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 21. " BUF53I ,Buffer 53 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 20. " BUF52I ,Buffer 52 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 19. " BUF51I ,Buffer 51 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 18. " BUF50I ,Buffer 50 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 17. " BUF49I ,Buffer 49 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 16. " BUF48I ,Buffer 48 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 15. " BUF47I ,Buffer 47 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 14. " BUF46I ,Buffer 46 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 13. " BUF45I ,Buffer 45 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 12. " BUF44I ,Buffer 44 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 11. " BUF43I ,Buffer 43 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 10. " BUF42I ,Buffer 42 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 9. " BUF41I ,Buffer 41 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 8. " BUF40I ,Buffer 40 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 7. " BUF39I ,Buffer 39 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 6. " BUF38I ,Buffer 38 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 5. " BUF37I ,Buffer 37 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 4. " BUF36I ,Buffer 36 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 3. " BUF35I ,Buffer 35 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 2. " BUF34I ,Buffer 34 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 1. " BUF33I ,Buffer 33 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 0. " BUF32I ,Buffer 32 MB interrupt" "Not occurred,Occurred" if (((per.l(ad:0x30A00000))&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer 31 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " BUF30I ,Buffer 30 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " BUF29I ,Buffer 29 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " BUF28I ,Buffer 28 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer 27 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " BUF26I ,Buffer 26 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BUF25I ,Buffer 25 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " BUF24I ,Buffer 24 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer 23 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " BUF22I ,Buffer 22 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " BUF21I ,Buffer 21 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " BUF20I ,Buffer 20 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer 19 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " BUF18I ,Buffer 18 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " BUF17I ,Buffer 17 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " BUF16I ,Buffer 16 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer 15 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " BUF14I ,Buffer 14 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " BUF13I ,Buffer 13 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " BUF12I ,Buffer 12 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer 11 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " BUF10I ,Buffer 10 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " BUF9I ,Buffer 9 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " BUF8I ,Buffer 8 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " BUF7I ,Buffer 7 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 6. " BUF6I ,Buffer 6 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 5. " BUF5I ,Buffer 5 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 4. " BUF4I ,Buffer 4 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " BUF3I ,Buffer 3 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 2. " BUF2I ,Buffer 2 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 1. " BUF1I ,Buffer 1 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 0. " BUF0I ,Buffer 0 MB interrupt" "Not occurred,Occurred" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer 31 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " BUF30I ,Buffer 30 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " BUF29I ,Buffer 29 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " BUF28I ,Buffer 28 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer 27 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " BUF26I ,Buffer 26 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BUF25I ,Buffer 25 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " BUF24I ,Buffer 24 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer 23 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " BUF22I ,Buffer 22 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " BUF21I ,Buffer 21 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " BUF20I ,Buffer 20 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer 19 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " BUF18I ,Buffer 18 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " BUF17I ,Buffer 17 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " BUF16I ,Buffer 16 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer 15 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " BUF14I ,Buffer 14 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " BUF13I ,Buffer 13 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " BUF12I ,Buffer 12 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer 11 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " BUF10I ,Buffer 10 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " BUF9I ,Buffer 9 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " BUF8I ,Buffer 8 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " BUF7I ,FIFO overflow condition" "No overflow,Overflow" eventfld.long 0x00 6. " BUF6I ,4 out of 6 buffers of the FIFO are already occupied" "Not occupied,Occupied" eventfld.long 0x00 5. " BUF5I ,Least one frame is available to be read from the FIFO" "Not available,Available" endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Unrestricted write access to flexcan memory enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx can bits delay value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Matching start process" "Rx FIFO->Mailboxes,Mailboxes->Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request frame generate/store" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,IDE and RTR comparison enable" "Disabled,Enabled" else rgroup.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Unrestricted write access to flexcan memory enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx can bits delay value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Matching start process" "Rx FIFO->Mailboxes,Mailboxes->Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request frame generate/store" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,IDE and RTR comparison enable" "Disabled,Enabled" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status Register 2" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number of inactive mailbox" bitfld.long 0x00 14. " VPS ,Contents of IMB and LPTM valid" "Not valid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox available" "Not available,Available" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Tx CRC mailbox number" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if (((per.l(ad:0x30A00000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 29. " FGM[29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" textline " " bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" textline " " bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " elif (((per.l(ad:0x30A00000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 29. " FGM[29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" textline " " bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" textline " " bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" textline " " bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier acceptance filter hit by the received message" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Register" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Glitch filter width" tree.end width 9. tree "Rx Individual Mask Registers 0-63" if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A00000))&0x1000000)==0x1000000) group.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif tree.end width 0x0B tree.end tree "FLEXCAN2" base ad:0x30A10000 width 10. tree "Common Registers" if (((per.l(ad:0x30A10000))&0x1100000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" rbitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" elif (((per.l(ad:0x30A10000))&0x1100000)==0x100000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" bitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" rbitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" rbitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO feature enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Flexcan freeze mode" "Not requested,Requested" textline " " rbitfld.long 0x00 27. " NOT_RDY ,Flexcan not ready" "Normal/listen-only/loopback,Disable/stop/freeze" bitfld.long 0x00 26. " WAK_MSK ,Wake-up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "Disabled,Enabled" rbitfld.long 0x00 22. " SLF_WAK ,Self wake-up" "Disabled,Enabled" rbitfld.long 0x00 21. " WRN_EN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low power mode acknowledge" "Not acknowledged,Acknowledged" textline " " rbitfld.long 0x00 19. " WAK_SRC ,Wake-up source" "Unfiltered rx,Filtered rx" rbitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual rx masking and queue feature enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local priority feature enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 12. " AEN ,Tx abort feature enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Maximum number of message buffers" endif if (((per.l(ad:0x30A10000))&0x1200000)==0x1200000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" bitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" bitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" bitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x30A10000))&0x1200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" rbitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" rbitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" rbitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" elif (((per.l(ad:0x30A10000)&0x1200000)==0x1000000)) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" bitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" rbitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " rbitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" bitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" bitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase buffer segment 1" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase buffer segment 2" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 15. " BOFF_MSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERR_MSK ,Error mask" "Disabled,Enabled" rbitfld.long 0x00 12. " LPB ,Loop back" "Disabled,Enabled" rbitfld.long 0x00 11. " TWRN_MSK ,Tx warning interrupt mask" "Disabled,Enabled" textline " " rbitfld.long 0x00 10. " RWRN_MSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,Sampling mode" "1 sample,3 samples" bitfld.long 0x00 6. " BOFF_REC ,Disable automatic recovering from bus off state" "No,Yes" rbitfld.long 0x00 5. " TSYN ,Timer sync mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "With highest priority,Lowest number" rbitfld.long 0x00 3. " LOM ,Listen-only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "1,2,3,4,5,6,7,8" endif hgroup.long 0x08++0x03 hide.long 0x00 "TIMER,Free-Running Timer Register" in textline " " if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long 0x10++0x0F line.long 0x00 "RXGMASK,Rx Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x04 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x04 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x04 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x04 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x04 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x04 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x04 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x04 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x04 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x04 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x08 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x08 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x08 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x08 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x08 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x08 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x08 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x08 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x08 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x08 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x08 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x08 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_COUNTER ,Rx error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_COUNTER ,Tx error counter" textline " " else rgroup.long 0x10++0x0F line.long 0x00 "RXGMASK,Rx Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x04 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x04 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x04 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x04 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x04 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x04 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x04 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x04 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x04 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x04 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x08 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x08 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x08 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x08 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x08 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x08 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x08 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x08 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x08 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x08 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x08 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x08 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " textline " " line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_COUNTER ,Rx error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_COUNTER ,Tx error counter" endif hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status Register 1" in group.long 0x24++0x0B line.long 0x00 "IMASK2,Interrupt Mask Register 2" bitfld.long 0x00 31. " BUF63M ,Buffer 63 MB mask" "Disabled,Enabled" bitfld.long 0x00 30. " BUF62M ,Buffer 62 MB mask" "Disabled,Enabled" bitfld.long 0x00 29. " BUF61M ,Buffer 61 MB mask" "Disabled,Enabled" bitfld.long 0x00 28. " BUF60M ,Buffer 60 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BUF59M ,Buffer 59 MB mask" "Disabled,Enabled" bitfld.long 0x00 26. " BUF58M ,Buffer 58 MB mask" "Disabled,Enabled" bitfld.long 0x00 25. " BUF57M ,Buffer 57 MB mask" "Disabled,Enabled" bitfld.long 0x00 24. " BUF56M ,Buffer 56 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BUF55M ,Buffer 55 MB mask" "Disabled,Enabled" bitfld.long 0x00 22. " BUF54M ,Buffer 54 MB mask" "Disabled,Enabled" bitfld.long 0x00 21. " BUF53M ,Buffer 53 MB mask" "Disabled,Enabled" bitfld.long 0x00 20. " BUF52M ,Buffer 52 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BUF51M ,Buffer 51 MB mask" "Disabled,Enabled" bitfld.long 0x00 18. " BUF50M ,Buffer 50 MB mask" "Disabled,Enabled" bitfld.long 0x00 17. " BUF49M ,Buffer 49 MB mask" "Disabled,Enabled" bitfld.long 0x00 16. " BUF48M ,Buffer 48 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " BUF47M ,Buffer 47 MB mask" "Disabled,Enabled" bitfld.long 0x00 14. " BUF46M ,Buffer 46 MB mask" "Disabled,Enabled" bitfld.long 0x00 13. " BUF45M ,Buffer 45 MB mask" "Disabled,Enabled" bitfld.long 0x00 12. " BUF44M ,Buffer 44 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BUF43M ,Buffer 43 MB mask" "Disabled,Enabled" bitfld.long 0x00 10. " BUF42M ,Buffer 42 MB mask" "Disabled,Enabled" bitfld.long 0x00 9. " BUF41M ,Buffer 41 MB mask" "Disabled,Enabled" bitfld.long 0x00 8. " BUF40M ,Buffer 40 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BUF39M ,Buffer 39 MB mask" "Disabled,Enabled" bitfld.long 0x00 6. " BUF38M ,Buffer 38 MB mask" "Disabled,Enabled" bitfld.long 0x00 5. " BUF37M ,Buffer 37 MB mask" "Disabled,Enabled" bitfld.long 0x00 4. " BUF36M ,Buffer 36 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF35M ,Buffer 35 MB mask" "Disabled,Enabled" bitfld.long 0x00 2. " BUF34M ,Buffer 34 MB mask" "Disabled,Enabled" bitfld.long 0x00 1. " BUF33M ,Buffer 33 MB mask" "Disabled,Enabled" bitfld.long 0x00 0. " BUF32M ,Buffer 32 MB mask" "Disabled,Enabled" line.long 0x04 "IMASK1,Interrupt Masks Register 1" bitfld.long 0x04 31. " BUF31M ,Buffer 31 MB mask" "Disabled,Enabled" bitfld.long 0x04 30. " BUF30M ,Buffer 30 MB mask" "Disabled,Enabled" bitfld.long 0x04 29. " BUF29M ,Buffer 29 MB mask" "Disabled,Enabled" bitfld.long 0x04 28. " BUF28M ,Buffer 28 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " BUF27M ,Buffer 27 MB mask" "Disabled,Enabled" bitfld.long 0x04 26. " BUF26M ,Buffer 26 MB mask" "Disabled,Enabled" bitfld.long 0x04 25. " BUF25M ,Buffer 25 MB mask" "Disabled,Enabled" bitfld.long 0x04 24. " BUF24M ,Buffer 24 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " BUF23M ,Buffer 23 MB mask" "Disabled,Enabled" bitfld.long 0x04 22. " BUF22M ,Buffer 22 MB mask" "Disabled,Enabled" bitfld.long 0x04 21. " BUF21M ,Buffer 21 MB mask" "Disabled,Enabled" bitfld.long 0x04 20. " BUF20M ,Buffer 20 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " BUF19M ,Buffer 19 MB mask" "Disabled,Enabled" bitfld.long 0x04 18. " BUF18M ,Buffer 18 MB mask" "Disabled,Enabled" bitfld.long 0x04 17. " BUF17M ,Buffer 17 MB mask" "Disabled,Enabled" bitfld.long 0x04 16. " BUF16M ,Buffer 16 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " BUF15M ,Buffer 15 MB mask" "Disabled,Enabled" bitfld.long 0x04 14. " BUF14M ,Buffer 14 MB mask" "Disabled,Enabled" bitfld.long 0x04 13. " BUF13M ,Buffer 13 MB mask" "Disabled,Enabled" bitfld.long 0x04 12. " BUF12M ,Buffer 12 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BUF11M ,Buffer 11 MB mask" "Disabled,Enabled" bitfld.long 0x04 10. " BUF10M ,Buffer 10 MB mask" "Disabled,Enabled" bitfld.long 0x04 9. " BUF9M ,Buffer 9 MB mask" "Disabled,Enabled" bitfld.long 0x04 8. " BUF8M ,Buffer 8 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BUF7M ,Buffer 7 MB mask" "Disabled,Enabled" bitfld.long 0x04 6. " BUF6M ,Buffer 6 MB mask" "Disabled,Enabled" bitfld.long 0x04 5. " BUF5M ,Buffer 5 MB mask" "Disabled,Enabled" bitfld.long 0x04 4. " BUF4M ,Buffer 4 MB mask" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BUF3M ,Buffer 3 MB mask" "Disabled,Enabled" bitfld.long 0x04 2. " BUF2M ,Buffer 2 MB mask" "Disabled,Enabled" bitfld.long 0x04 1. " BUF1M ,Buffer 1 MB mask" "Disabled,Enabled" bitfld.long 0x04 0. " BUF0M ,Buffer 0 MB mask" "Disabled,Enabled" line.long 0x08 "IFLAG2,Interrupt Flags 2 Register" eventfld.long 0x08 31. " BUF63I ,Buffer 63 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 30. " BUF62I ,Buffer 62 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 29. " BUF61I ,Buffer 61 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 28. " BUF60I ,Buffer 60 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 27. " BUF59I ,Buffer 59 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 26. " BUF58I ,Buffer 58 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 25. " BUF57I ,Buffer 57 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 24. " BUF56I ,Buffer 56 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 23. " BUF55I ,Buffer 55 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 22. " BUF54I ,Buffer 54 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 21. " BUF53I ,Buffer 53 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 20. " BUF52I ,Buffer 52 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 19. " BUF51I ,Buffer 51 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 18. " BUF50I ,Buffer 50 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 17. " BUF49I ,Buffer 49 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 16. " BUF48I ,Buffer 48 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 15. " BUF47I ,Buffer 47 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 14. " BUF46I ,Buffer 46 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 13. " BUF45I ,Buffer 45 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 12. " BUF44I ,Buffer 44 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 11. " BUF43I ,Buffer 43 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 10. " BUF42I ,Buffer 42 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 9. " BUF41I ,Buffer 41 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 8. " BUF40I ,Buffer 40 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 7. " BUF39I ,Buffer 39 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 6. " BUF38I ,Buffer 38 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 5. " BUF37I ,Buffer 37 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 4. " BUF36I ,Buffer 36 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x08 3. " BUF35I ,Buffer 35 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 2. " BUF34I ,Buffer 34 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 1. " BUF33I ,Buffer 33 MB interrupt" "Not occurred,Occurred" eventfld.long 0x08 0. " BUF32I ,Buffer 32 MB interrupt" "Not occurred,Occurred" if (((per.l(ad:0x30A10000))&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer 31 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " BUF30I ,Buffer 30 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " BUF29I ,Buffer 29 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " BUF28I ,Buffer 28 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer 27 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " BUF26I ,Buffer 26 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BUF25I ,Buffer 25 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " BUF24I ,Buffer 24 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer 23 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " BUF22I ,Buffer 22 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " BUF21I ,Buffer 21 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " BUF20I ,Buffer 20 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer 19 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " BUF18I ,Buffer 18 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " BUF17I ,Buffer 17 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " BUF16I ,Buffer 16 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer 15 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " BUF14I ,Buffer 14 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " BUF13I ,Buffer 13 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " BUF12I ,Buffer 12 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer 11 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " BUF10I ,Buffer 10 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " BUF9I ,Buffer 9 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " BUF8I ,Buffer 8 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " BUF7I ,Buffer 7 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 6. " BUF6I ,Buffer 6 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 5. " BUF5I ,Buffer 5 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 4. " BUF4I ,Buffer 4 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " BUF3I ,Buffer 3 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 2. " BUF2I ,Buffer 2 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 1. " BUF1I ,Buffer 1 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 0. " BUF0I ,Buffer 0 MB interrupt" "Not occurred,Occurred" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer 31 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " BUF30I ,Buffer 30 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " BUF29I ,Buffer 29 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " BUF28I ,Buffer 28 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer 27 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " BUF26I ,Buffer 26 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BUF25I ,Buffer 25 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " BUF24I ,Buffer 24 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer 23 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " BUF22I ,Buffer 22 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " BUF21I ,Buffer 21 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " BUF20I ,Buffer 20 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer 19 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " BUF18I ,Buffer 18 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " BUF17I ,Buffer 17 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " BUF16I ,Buffer 16 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer 15 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " BUF14I ,Buffer 14 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " BUF13I ,Buffer 13 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " BUF12I ,Buffer 12 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer 11 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " BUF10I ,Buffer 10 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " BUF9I ,Buffer 9 MB interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " BUF8I ,Buffer 8 MB interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " BUF7I ,FIFO overflow condition" "No overflow,Overflow" eventfld.long 0x00 6. " BUF6I ,4 out of 6 buffers of the FIFO are already occupied" "Not occupied,Occupied" eventfld.long 0x00 5. " BUF5I ,Least one frame is available to be read from the FIFO" "Not available,Available" endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Unrestricted write access to flexcan memory enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx can bits delay value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Matching start process" "Rx FIFO->Mailboxes,Mailboxes->Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request frame generate/store" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,IDE and RTR comparison enable" "Disabled,Enabled" else rgroup.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Unrestricted write access to flexcan memory enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx can bits delay value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Matching start process" "Rx FIFO->Mailboxes,Mailboxes->Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request frame generate/store" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,IDE and RTR comparison enable" "Disabled,Enabled" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status Register 2" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number of inactive mailbox" bitfld.long 0x00 14. " VPS ,Contents of IMB and LPTM valid" "Not valid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox available" "Not available,Available" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Tx CRC mailbox number" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if (((per.l(ad:0x30A10000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 29. " FGM[29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" textline " " bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" textline " " bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " elif (((per.l(ad:0x30A10000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 29. " FGM[29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" textline " " bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" textline " " bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" textline " " bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier acceptance filter hit by the received message" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Register" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Glitch filter width" tree.end width 9. tree "Rx Individual Mask Registers 0-63" if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif if (((per.l(ad:0x30A10000))&0x1000000)==0x1000000) group.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " else rgroup.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " RTR ,RTR bit of incoming frame" "0,1" bitfld.long 0x00 30. " IDE ,IDE bit of incoming frame" "0,1" textline " " bitfld.long 0x00 28. " MI[28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" textline " " bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Extended ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Extended ID mask bit 16" "0,1" bitfld.long 0x00 15. " [15] ,Extended ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Extended ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Extended ID mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " [12] ,Extended ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Extended ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Extended ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Extended ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Extended ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Extended ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Extended ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Extended ID mask bit 5" "0,1" textline " " bitfld.long 0x00 4. " [4] ,Extended ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Extended ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Extended ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Extended ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Extended ID mask bit 0" "0,1" textline " " endif tree.end width 0x0B tree.end tree.end tree.open "I2C (I2C Controller)" tree "I2C1" base ad:0x30A20000 width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C2" base ad:0x30A30000 width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C3" base ad:0x30A40000 width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C4" base ad:0x30A50000 width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree.end tree.open "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART1" base ad:0x30860000 width 7. if ((((per.l(ad:0x30860000+0x80))&0x01)==0x00)||(((per.l(ad:0x30860000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30860000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30860000+0x80)&0x01)==0x00)||((per.l(ad:0x30860000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30860000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30860000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30860000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30860000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30860000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30860000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30860000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30860000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30860000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30860000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30860000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30860000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART2" base ad:0x30870000 width 7. if ((((per.l(ad:0x30870000+0x80))&0x01)==0x00)||(((per.l(ad:0x30870000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30870000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30870000+0x80)&0x01)==0x00)||((per.l(ad:0x30870000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30870000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30870000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30870000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30870000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30870000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30870000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30870000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30870000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30870000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30870000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30870000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30870000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART3" base ad:0x30880000 width 7. if ((((per.l(ad:0x30880000+0x80))&0x01)==0x00)||(((per.l(ad:0x30880000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30880000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30880000+0x80)&0x01)==0x00)||((per.l(ad:0x30880000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30880000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30880000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30880000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30880000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30880000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30880000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30880000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30880000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30880000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30880000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30880000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30880000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART4" base ad:0x30A60000 width 7. if ((((per.l(ad:0x30A60000+0x80))&0x01)==0x00)||(((per.l(ad:0x30A60000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30A60000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30A60000+0x80)&0x01)==0x00)||((per.l(ad:0x30A60000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30A60000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30A60000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30A60000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A60000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A60000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30A60000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A60000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A60000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30A60000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A60000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30A60000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A60000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART5" base ad:0x30A70000 width 7. if ((((per.l(ad:0x30A70000+0x80))&0x01)==0x00)||(((per.l(ad:0x30A70000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30A70000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30A70000+0x80)&0x01)==0x00)||((per.l(ad:0x30A70000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30A70000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30A70000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30A70000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A70000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A70000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30A70000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A70000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A70000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30A70000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A70000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30A70000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A70000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART6" base ad:0x30A80000 width 7. if ((((per.l(ad:0x30A80000+0x80))&0x01)==0x00)||(((per.l(ad:0x30A80000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30A80000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30A80000+0x80)&0x01)==0x00)||((per.l(ad:0x30A80000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30A80000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30A80000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30A80000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A80000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A80000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30A80000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A80000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A80000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30A80000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A80000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30A80000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A80000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART7" base ad:0x30A90000 width 7. if ((((per.l(ad:0x30A90000+0x80))&0x01)==0x00)||(((per.l(ad:0x30A90000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x30A90000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity error flag" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character ready" "Not ready,Ready" bitfld.long 0x00 14. " ERR ,Error detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver overrun" "No overrun,Overrun" bitfld.long 0x00 12. " FRMERR ,Frame error" "No error,Error" textline " " bitfld.long 0x00 11. " BRK ,BREAK detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (Bit [8]) of received 9-bit RS-485 data" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received data" endif if (((per.l(ad:0x30A90000+0x80)&0x01)==0x00)||((per.l(ad:0x30A90000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" endif if (((per.l(ad:0x30A90000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic baud rate detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic detection of baud rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " IDEN ,Idle condition detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ICD ,Idle condition detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXDMAEN ,Receive ready DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared interface enable" "Disabled,?..." textline " " bitfld.long 0x00 6. " TXMPTYEN ,Transmitter empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RTSDEN ,RTS delta interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter ready DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA timer enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape sequence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS pin control" "CTS,Receiver" bitfld.long 0x00 12. " CTS ,Clear to send" "High,Low" textline " " bitfld.long 0x00 11. " ESCEN ,Escape enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to send edge control" "Rising,Falling,Any,Any" bitfld.long 0x00 8. " PREN ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity odd/even" "Even,Odd" textline " " bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" bitfld.long 0x00 5. " WS ,Word size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to send interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software reset" "Reset,No reset" if ((((per.l(ad:0x30A90000+0x90))&0x40)==0x40)&&((((per.l(ad:0x30A90000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A90000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A90000+0x90))&0x40)==0x40)&&!((((per.l(ad:0x30A90000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A90000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect - DCDDELT enable" "Disabled,Enabled" bitfld.long 0x00 8. " RI ,Ring indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" elif ((((per.l(ad:0x30A90000+0x90))&0x40)==0x00)&&((((per.l(ad:0x30A90000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A90000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Active low,Active high" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" else group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR interrupt edge control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data terminal ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PARERREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data set ready" "0,1" bitfld.long 0x00 9. " DCD ,Data carrier detect (Dcd logic state)" "0,1" bitfld.long 0x00 8. " RI ,Ring indicator (Ri logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband detection not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data terminal ready delta enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD muxed input selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 0. " ACIEN ,Autobaud counter interrupt enable" "Disabled,Enabled" endif if ((((per.l(ad:0x30A90000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x30A90000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in in irda mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" else group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial infrared interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " WKEN ,WAKE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR special case" "Sampling clock,Reference clock" bitfld.long 0x00 4. " LPBYP ,Low power bypass" "Not bypassed,Bypassed" bitfld.long 0x00 3. " TCEN ,Transmit complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKEN ,BREAK condition detected interrupt enabled" "Disabled,Enabled" bitfld.long 0x00 1. " OREN ,Receiver overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive data ready interrupt enable" "Disabled,Enabled" endif group.long 0x90++0x03 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter trigger level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference frequency divider" "/6,/5,/4,/3,/2,/1,/7,?..." bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." sif (CPUIS("IMX7DUAL-CA7")||CPUIS("IMX7DUAL-CM4")||CPUIS("IMX7SOLO-CA7")||CPUIS("IMX7SOLO-CM4")) group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" textline " " eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" textline " " eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" else group.long 0x94++0x07 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS pin status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter ready interrupt /DMA flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " RTSD ,RTS delta" "Not changed,Changed" textline " " eventfld.long 0x00 11. " ESCF ,Escape sequence interrupt flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame error interrupt flag" "Not detected,Detected" rbitfld.long 0x00 9. " RRDY ,Receiver ready interrupt /DMA flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing timer interrupt flag" "Not active,Active" textline " " eventfld.long 0x00 7. " DTRD ,DTR delta" "Not changed,Changed" rbitfld.long 0x00 6. " RXDS ,Receiver IDLE interrupt flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE pulse detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling edge detection on the RXD serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 slave address detected interrupt flag" "Not detected,Detected" line.long 0x04 "USR2,UART Status Register 2" eventfld.long 0x04 15. " ADET ,Automatic baud rate detect complete" "Not received,Received" rbitfld.long 0x04 14. " TXFE ,Transmit buffer FIFO empty" "Not empty,Empty" eventfld.long 0x04 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" eventfld.long 0x04 12. " IDLE ,Idle condition" "Not detected,Detected" textline " " eventfld.long 0x04 11. " ACST ,Autobaud counter stopped" "Not finished,Finished" eventfld.long 0x04 10. " RIDELT ,Ring indicator delta" "Not changed,Changed" rbitfld.long 0x04 9. " RIIN ,Ring indicator input" "Detected,Not detected" eventfld.long 0x04 8. " IRINT ,Serial infrared interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x04 7. " WAKE ,Wake" "Not detected,Detected" eventfld.long 0x04 6. " DCDDELT ,Data carrier detect delta" "Not changed,Changed" rbitfld.long 0x04 5. " DCDIN ,Data carrier detect input" "Detected,Not detected" eventfld.long 0x04 4. " RTSF ,RTS edge triggered interrupt flag" "Not detected,Detected" textline " " rbitfld.long 0x04 3. " TXDC ,Transmitter complete" "Not completed,Completed" eventfld.long 0x04 2. " BRCD ,BREAK condition detected" "Not detected,Detected" eventfld.long 0x04 1. " ORE ,Overrun error" "No error,Error" rbitfld.long 0x04 0. " RDR ,Receive data ready" "Not ready,Ready" endif group.long 0x9C++0x0F line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART escape character" line.long 0x04 "UTIM,UART Escape Timer Register" hexmask.long.word 0x04 0.--11. 1. " TIM ,UART escape timer" line.long 0x08 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x08 0.--15. 1. " INC ,UART BRM incremental numerator" line.long 0x0C "UBMR,UART BRM Modulator Register" hexmask.long.word 0x0C 0.--15. 1. " MOD ,Modulator dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART baud rate count register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART one millisecond register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force parity error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,/debug_enable" "Enabled,Disabled" bitfld.long 0x04 10. " LOOPIR ,Loop tx and RX for IR test" "Normal,Loop" textline " " bitfld.long 0x04 9. " RXDBG ,Rx_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x04 3. " RXFULL ,Rx FIFO full" "Not full,Full" bitfld.long 0x04 0. " SOFTRST ,Software reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 slave address character" bitfld.long 0x08 3. " SADEN ,RS-485 slave address detected interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" bitfld.long 0x08 1. " SLAM ,RS-485 slave address detect mode selection" "Normal,Automatic" textline " " bitfld.long 0x08 0. " MDEN ,9-bit data or multidrop mode (Rs-485) enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree.end tree "KPP (Keypad Port)" base ad:0x30320000 width 10. group.word 0x00++0x07 line.word 0x00 "KPP_KPCR,Keypad Control Register" bitfld.word 0x00 15. " KCO_7 ,Keypad column strobe Open-Drain enable 7" "Totem pole,Open drain" bitfld.word 0x00 14. " KCO_6 ,Keypad column strobe Open-Drain enable 6" "Totem pole,Open drain" bitfld.word 0x00 13. " KCO_5 ,Keypad column strobe Open-Drain enable 5" "Totem pole,Open drain" bitfld.word 0x00 12. " KCO_4 ,Keypad column strobe Open-Drain enable 4" "Totem pole,Open drain" textline " " bitfld.word 0x00 11. " KCO_3 ,Keypad column strobe Open-Drain enable 3" "Totem pole,Open drain" bitfld.word 0x00 10. " KCO_2 ,Keypad column strobe Open-Drain enable 2" "Totem pole,Open drain" bitfld.word 0x00 9. " KCO_1 ,Keypad column strobe Open-Drain enable 1" "Totem pole,Open drain" bitfld.word 0x00 8. " KCO_0 ,Keypad column strobe Open-Drain enable 0" "Totem pole,Open drain" textline " " bitfld.word 0x00 7. " KRE_7 ,Keypad row enable 7" "Not included,Included" bitfld.word 0x00 6. " KRE_6 ,Keypad row enable 6" "Not included,Included" bitfld.word 0x00 5. " KRE_5 ,Keypad row enable 5" "Not included,Included" bitfld.word 0x00 4. " KRE_4 ,Keypad row enable 4" "Not included,Included" textline " " bitfld.word 0x00 3. " KRE_3 ,Keypad row enable 3" "Not included,Included" bitfld.word 0x00 2. " KRE_2 ,Keypad row enable 2" "Not included,Included" bitfld.word 0x00 1. " KRE_1 ,Keypad row enable 1" "Not included,Included" bitfld.word 0x00 0. " KRE_0 ,Keypad row enable 0" "Not included,Included" line.word 0x02 "KPP_KPSR,Keypad Status Register" bitfld.word 0x02 9. " KRIE ,Keypad release interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 8. " KDIE ,Keypad key depress interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 3. " KRSS ,Key release synchronizer set" "No effect,Release" bitfld.word 0x02 2. " KDSC ,Key depress synchronizer clear" "No effect,Clear" textline " " eventfld.word 0x02 1. " KPKR ,Keypad key release" "Not released,Released" eventfld.word 0x02 0. " KPKD ,Keypad key depress" "Not pressed,Depressed" line.word 0x04 "KPP_KDDR,Keypad Data Direction Register" bitfld.word 0x04 15. " KCCD_7 ,Keypad column data direction register 7" "Input,Output" bitfld.word 0x04 14. " KCCD_6 ,Keypad column data direction register 6" "Input,Output" bitfld.word 0x04 13. " KCCD_5 ,Keypad column data direction register 5" "Input,Output" bitfld.word 0x04 12. " KCCD_4 ,Keypad column data direction register 4" "Input,Output" textline " " bitfld.word 0x04 11. " KCCD_3 ,Keypad column data direction register 3" "Input,Output" bitfld.word 0x04 10. " KCCD_2 ,Keypad column data direction register 2" "Input,Output" bitfld.word 0x04 9. " KCCD_1 ,Keypad column data direction register 1" "Input,Output" bitfld.word 0x04 8. " KCCD_0 ,Keypad column data direction register 0" "Input,Output" textline " " bitfld.word 0x04 7. " KRDD_7 ,Keypad row data direction 7" "Input,Output" bitfld.word 0x04 6. " KRDD_6 ,Keypad row data direction 6" "Input,Output" bitfld.word 0x04 5. " KRDD_5 ,Keypad row data direction 5" "Input,Output" bitfld.word 0x04 4. " KRDD_4 ,Keypad row data direction 4" "Input,Output" textline " " bitfld.word 0x04 3. " KRDD_3 ,Keypad row data direction 3" "Input,Output" bitfld.word 0x04 2. " KRDD_2 ,Keypad row data direction 2" "Input,Output" bitfld.word 0x04 1. " KRDD_1 ,Keypad row data direction 1" "Input,Output" bitfld.word 0x04 0. " KRDD_0 ,Keypad row data direction 0" "Input,Output" line.word 0x06 "KPP_KPDR,Keypad Data Register" bitfld.word 0x06 15. " KCD_7 ,Keypad column data 7" "0,1" bitfld.word 0x06 14. " KCD_6 ,Keypad column data 6" "0,1" bitfld.word 0x06 13. " KCD_5 ,Keypad column data 5" "0,1" bitfld.word 0x06 12. " KCD_4 ,Keypad column data 4" "0,1" textline " " bitfld.word 0x06 11. " KCD_3 ,Keypad column data 3" "0,1" bitfld.word 0x06 10. " KCD_2 ,Keypad column data 2" "0,1" bitfld.word 0x06 9. " KCD_1 ,Keypad column data 1" "0,1" bitfld.word 0x06 8. " KCD_0 ,Keypad column data 0" "0,1" textline " " bitfld.word 0x06 7. " KRD_7 ,Keypad row data 7" "0,1" bitfld.word 0x06 6. " KRD_6 ,Keypad row data 6" "0,1" bitfld.word 0x06 5. " KRD_5 ,Keypad row data 5" "0,1" bitfld.word 0x06 4. " KRD_4 ,Keypad row data 4" "0,1" textline " " bitfld.word 0x06 3. " KRD_3 ,Keypad row data 3" "0,1" bitfld.word 0x06 2. " KRD_2 ,Keypad row data 2" "0,1" bitfld.word 0x06 1. " KRD_1 ,Keypad row data 1" "0,1" bitfld.word 0x06 0. " KRD_0 ,Keypad row data 0" "0,1" width 0x0B tree.end newline